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[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] [rc203/] [rc203_ethcontroller.v] - Blame information for rev 1780

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Ethernet Interface for RC203 board                          ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Manages access from Wishbone to Ethernet SMC91111 Chip      ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing really                                           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Javier Castillo, javier.castillo@urjc.es              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2005 OpenCores                                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2005/05/26 12:25:42  jcastillo
// Added support for ethernet chip
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module wb_eth_controller(clk,reset,
 
                         wb_stb_i,wb_dat_o,wb_dat_i,
                         wb_ack_o,wb_adr_i,wb_we_i,
                         wb_cyc_i,wb_sel_i,
 
                         eth_nREAD,eth_nWRITE,eth_address,eth_data,
                         eth_nBE,eth_reset
                        );
 
input         clk;
input         reset;
//
// WISHBONE INTERFACE
//
input         wb_stb_i;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_ack_o;
input  [31:0] wb_adr_i;
input         wb_we_i;
input         wb_cyc_i;
input  [3:0]  wb_sel_i;
 
//
// SMC91111 PINS
//
output        eth_nREAD;
output        eth_nWRITE;
output [2:0]  eth_address;
inout  [15:0] eth_data;   //INOUT
output [1:0]  eth_nBE;
output        eth_reset;
 
reg  [31:0]   wb_dat_o;
reg           wb_ack_o;
reg           eth_nREAD;
reg           eth_nWRITE;
reg  [2:0]    eth_address;
reg  [1:0]    eth_nBE;
wire [15:0]   eth_data;
wire          eth_ardy;
wire          eth_reset;
 
reg   next_reading;
reg   reading;
reg   next_writing;
reg   writing;
 
//State Machine
parameter IDLE=0,
          ACTIVE_STROBE=1;
 
 
reg [1:0] state,next_state;
reg [4:0] counter,next_counter;
reg [31:0] next_wb_dat_o;
reg [15:0] half_word;
 
reg [7:0] bytes[8:0];
 
assign eth_reset = reset;
assign eth_data = (next_writing | writing) ? half_word : 16'hZ;
 
always @(wb_adr_i or wb_stb_i or wb_sel_i or wb_ack_o or wb_we_i or wb_cyc_i or counter
         or reading or writing or wb_ack_o or state or wb_dat_o or eth_data or wb_dat_i)
 
   begin
 
   next_wb_dat_o=wb_dat_o;
 
   next_reading  = reading;
   next_writing  = writing;
 
   next_state=state;
   next_counter=counter;
 
   eth_address  = wb_adr_i[3:1];
 
   eth_nREAD  = 1'b1;
   eth_nWRITE = 1'b1;
 
   //Allocate the data in correct position for writes
   half_word=16'h0;
 
   bytes[1]=wb_dat_i[7:0];
   bytes[2]=wb_dat_i[15:8];
   bytes[4]=wb_dat_i[23:16];
   bytes[8]=wb_dat_i[31:24];
 
   //Byte write
   eth_nBE[0]=wb_adr_i[0];
   eth_nBE[1]=~wb_adr_i[0];
   case(wb_adr_i[0])
     1'b1:
     begin
       half_word[15:8]=bytes[wb_sel_i];
     end
     1'b0:
         begin
     half_word[7:0]=bytes[wb_sel_i];
     end
   endcase
 
   //Word write
   case(wb_sel_i)
     4'b0011:
     begin
      eth_nBE=2'b00;
      half_word=wb_dat_i[15:0];
     end
     4'b1100:
     begin
      eth_nBE=2'b00;
      half_word=wb_dat_i[31:16];
     end
         default:
         begin
         end
   endcase
 
   case(state)
      IDLE:
      begin
        if (wb_cyc_i && wb_stb_i && !wb_we_i && !wb_ack_o)
        begin
          //Single memory read 
          next_reading  = 1'b1;
          next_writing  = 1'b0;
          next_state=ACTIVE_STROBE;
                  eth_nBE=2'b00;         //Read Always 16 bits
        end
        else if (wb_cyc_i && wb_stb_i && wb_we_i && !wb_ack_o)
        begin
          //Single memory write
          next_writing  = 1'b1;
          next_reading  = 1'b0;
          next_state=ACTIVE_STROBE;
        end
      end
      ACTIVE_STROBE:
      begin
        if(reading)
                begin
                  eth_nBE=2'b00;         //Read Always 16 bits
          eth_nREAD=1'b0;
                end
        else if (writing)
                begin
          eth_nWRITE=1'b0;
                end
        if(counter==5)
        begin
          next_state=IDLE;
          next_counter=0;
          eth_nREAD=1'b1;
          eth_nWRITE=1'b1;
          next_writing=1'b0;
          next_reading=1'b0;
        end
        else if(counter==4 && reading)
        begin
          next_counter=counter+1;
               next_wb_dat_o=32'b0;
                  case(wb_sel_i)
                    //Reallocate bits for wishbone
                    4'b0001:
                        begin
              next_wb_dat_o[7:0]=eth_data[15:8];
                        end
                    4'b0010:
                        begin
              next_wb_dat_o[15:8]=eth_data[7:0];
                        end
                4'b0100:
                        begin
              next_wb_dat_o[23:16]=eth_data[15:8];
                        end
            4'b1000:
                    begin
              next_wb_dat_o[31:24]=eth_data[7:0];
                    end
                    4'b0011:
                    begin
              next_wb_dat_o[15:0]=eth_data;
                    end
                    4'b1100:
                    begin
              next_wb_dat_o[31:16]=eth_data;
                    end
                        4'b1111:
                        begin
                          next_wb_dat_o[15:0]=16'hDEAD;
                        end
            endcase
        end
        else
        begin
          next_counter=counter+1;
        end
      end
 
   endcase
 
 end
 
 
//register_proc:
always @(posedge clk or posedge reset)
 
   begin
 
   if (reset )
      begin
      state    <= #1 0;
      counter  <= #1 0;
      reading  <= #1 1'b0;
      writing  <= #1 1'b0;
      wb_ack_o <= #1 1'b0;
      wb_dat_o <= #1 32'h0;
      end
   else
      begin
      state    <= #1 next_state;
      counter  <= #1 next_counter;
      writing  <= #1 next_writing;
      reading  <= #1 next_reading;
      wb_dat_o <= #1  next_wb_dat_o;
      if((reading | writing) && counter==5)
        wb_ack_o<= #1 1'b1;
      else
        wb_ack_o<= #1 1'b0;
      end
   end
 
endmodule

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[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] [rc203/] [rc203_ethcontroller.v] - Blame information for rev 1780

Line No.	Rev	Author	Line
1	1494	jcastillo	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Ethernet Interface for RC203 board ////`
4			`//// ////`
5			`//// ////`
6			`//// Description ////`
7			`//// Manages access from Wishbone to Ethernet SMC91111 Chip ////`
8			`//// ////`
9			`//// To Do: ////`
10			`//// - nothing really ////`
11			`//// ////`
12			`//// Author(s): ////`
13	1575	jcastillo	`//// - Javier Castillo, javier.castillo@urjc.es ////`
14	1494	jcastillo	`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2005 OpenCores ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45	1575	jcastillo	`// Revision 1.1 2005/05/26 12:25:42 jcastillo`
46			`// Added support for ethernet chip`
47			`//`
48	1494	jcastillo
49			`// synopsys translate_off`
50			`include "timescale.v"
51			`// synopsys translate_on`
52
53			`module wb_eth_controller(clk,reset,`
54
55			`wb_stb_i,wb_dat_o,wb_dat_i,`
56			`wb_ack_o,wb_adr_i,wb_we_i,`
57			`wb_cyc_i,wb_sel_i,`
58
59			`eth_nREAD,eth_nWRITE,eth_address,eth_data,`
60			`eth_nBE,eth_reset`
61			`);`
62
63			`input clk;`
64			`input reset;`
65			`//`
66			`// WISHBONE INTERFACE`
67			`//`
68			`input wb_stb_i;`
69			`output [31:0] wb_dat_o;`
70			`input [31:0] wb_dat_i;`
71			`output wb_ack_o;`
72			`input [31:0] wb_adr_i;`
73			`input wb_we_i;`
74			`input wb_cyc_i;`
75			`input [3:0] wb_sel_i;`
76
77			`//`
78			`// SMC91111 PINS`
79			`//`
80			`output eth_nREAD;`
81			`output eth_nWRITE;`
82			`output [2:0] eth_address;`
83			`inout [15:0] eth_data; //INOUT`
84			`output [1:0] eth_nBE;`
85			`output eth_reset;`
86
87			`reg [31:0] wb_dat_o;`
88			`reg wb_ack_o;`
89			`reg eth_nREAD;`
90			`reg eth_nWRITE;`
91			`reg [2:0] eth_address;`
92			`reg [1:0] eth_nBE;`
93			`wire [15:0] eth_data;`
94			`wire eth_ardy;`
95			`wire eth_reset;`
96
97			`reg next_reading;`
98			`reg reading;`
99			`reg next_writing;`
100			`reg writing;`
101
102			`//State Machine`
103			`parameter IDLE=0,`
104			`ACTIVE_STROBE=1;`
105
106
107			`reg [1:0] state,next_state;`
108			`reg [4:0] counter,next_counter;`
109			`reg [31:0] next_wb_dat_o;`
110			`reg [15:0] half_word;`
111
112			`reg [7:0] bytes[8:0];`
113
114			`assign eth_reset = reset;`
115			`assign eth_data = (next_writing \| writing) ? half_word : 16'hZ;`
116
117			`always @(wb_adr_i or wb_stb_i or wb_sel_i or wb_ack_o or wb_we_i or wb_cyc_i or counter`
118			`or reading or writing or wb_ack_o or state or wb_dat_o or eth_data or wb_dat_i)`
119
120			`begin`
121
122			`next_wb_dat_o=wb_dat_o;`
123
124			`next_reading = reading;`
125			`next_writing = writing;`
126
127			`next_state=state;`
128			`next_counter=counter;`
129
130			`eth_address = wb_adr_i[3:1];`
131
132			`eth_nREAD = 1'b1;`
133			`eth_nWRITE = 1'b1;`
134
135			`//Allocate the data in correct position for writes`
136			`half_word=16'h0;`
137
138			`bytes[1]=wb_dat_i[7:0];`
139			`bytes[2]=wb_dat_i[15:8];`
140			`bytes[4]=wb_dat_i[23:16];`
141			`bytes[8]=wb_dat_i[31:24];`
142
143			`//Byte write`
144			`eth_nBE[0]=wb_adr_i[0];`
145			`eth_nBE[1]=~wb_adr_i[0];`
146			`case(wb_adr_i[0])`
147			`1'b1:`
148			`begin`
149			`half_word[15:8]=bytes[wb_sel_i];`
150			`end`
151			`1'b0:`
152			`begin`
153			`half_word[7:0]=bytes[wb_sel_i];`
154			`end`
155			`endcase`
156
157			`//Word write`
158			`case(wb_sel_i)`
159			`4'b0011:`
160			`begin`
161			`eth_nBE=2'b00;`
162			`half_word=wb_dat_i[15:0];`
163			`end`
164			`4'b1100:`
165			`begin`
166			`eth_nBE=2'b00;`
167			`half_word=wb_dat_i[31:16];`
168			`end`
169			`default:`
170			`begin`
171			`end`
172			`endcase`
173
174			`case(state)`
175			`IDLE:`
176			`begin`
177			`if (wb_cyc_i && wb_stb_i && !wb_we_i && !wb_ack_o)`
178			`begin`
179			`//Single memory read`
180			`next_reading = 1'b1;`
181			`next_writing = 1'b0;`
182			`next_state=ACTIVE_STROBE;`
183			`eth_nBE=2'b00; //Read Always 16 bits`
184			`end`
185			`else if (wb_cyc_i && wb_stb_i && wb_we_i && !wb_ack_o)`
186			`begin`
187			`//Single memory write`
188			`next_writing = 1'b1;`
189			`next_reading = 1'b0;`
190			`next_state=ACTIVE_STROBE;`
191			`end`
192			`end`
193			`ACTIVE_STROBE:`
194			`begin`
195			`if(reading)`
196			`begin`
197			`eth_nBE=2'b00; //Read Always 16 bits`
198			`eth_nREAD=1'b0;`
199			`end`
200			`else if (writing)`
201			`begin`
202			`eth_nWRITE=1'b0;`
203			`end`
204			`if(counter==5)`
205			`begin`
206			`next_state=IDLE;`
207			`next_counter=0;`
208			`eth_nREAD=1'b1;`
209			`eth_nWRITE=1'b1;`
210			`next_writing=1'b0;`
211			`next_reading=1'b0;`
212			`end`
213			`else if(counter==4 && reading)`
214			`begin`
215			`next_counter=counter+1;`
216			`next_wb_dat_o=32'b0;`
217			`case(wb_sel_i)`
218			`//Reallocate bits for wishbone`
219			`4'b0001:`
220			`begin`
221			`next_wb_dat_o[7:0]=eth_data[15:8];`
222			`end`
223			`4'b0010:`
224			`begin`
225			`next_wb_dat_o[15:8]=eth_data[7:0];`
226			`end`
227			`4'b0100:`
228			`begin`
229			`next_wb_dat_o[23:16]=eth_data[15:8];`
230			`end`
231			`4'b1000:`
232			`begin`
233			`next_wb_dat_o[31:24]=eth_data[7:0];`
234			`end`
235			`4'b0011:`
236			`begin`
237			`next_wb_dat_o[15:0]=eth_data;`
238			`end`
239			`4'b1100:`
240			`begin`
241			`next_wb_dat_o[31:16]=eth_data;`
242			`end`
243			`4'b1111:`
244			`begin`
245			`next_wb_dat_o[15:0]=16'hDEAD;`
246			`end`
247			`endcase`
248			`end`
249			`else`
250			`begin`
251			`next_counter=counter+1;`
252			`end`
253			`end`
254
255			`endcase`
256
257			`end`
258
259
260			`//register_proc:`
261			`always @(posedge clk or posedge reset)`
262
263			`begin`
264
265			`if (reset )`
266			`begin`
267			`state <= #1 0;`
268			`counter <= #1 0;`
269			`reading <= #1 1'b0;`
270			`writing <= #1 1'b0;`
271			`wb_ack_o <= #1 1'b0;`
272			`wb_dat_o <= #1 32'h0;`
273			`end`
274			`else`
275			`begin`
276			`state <= #1 next_state;`
277			`counter <= #1 next_counter;`
278			`writing <= #1 next_writing;`
279			`reading <= #1 next_reading;`
280			`wb_dat_o <= #1 next_wb_dat_o;`
281			`if((reading \| writing) && counter==5)`
282			`wb_ack_o<= #1 1'b1;`
283			`else`
284			`wb_ack_o<= #1 1'b0;`
285			`end`
286			`end`
287
288			`endmodule`