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[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] [rc203/] [rc203_romcontroller.v] - Blame information for rev 1771

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  ROM Controller for Coregen ROM block                        ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Manages access from Wishbone to internal ROM                ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing really                                           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Javier Castillo, javier.castillo@urjc.es              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 OpenCores                                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2004/12/13 17:16:09  jcastillo
// Firt import of OR1200 over Celoxica RC203 platform
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module wb_rom_controller(clk,reset,
 
                         wb_stb_i,wb_dat_o,wb_dat_i,
                         wb_ack_o,wb_adr_i,wb_we_i,
                         wb_cyc_i,wb_sel_i,
 
                         address,data
                        );
 
input         clk;
input         reset;
 
input         wb_stb_i;
output [31:0] wb_dat_o;
input  [31:0] wb_dat_i;
output        wb_ack_o;
input  [31:0] wb_adr_i;
input         wb_we_i;
input         wb_cyc_i;
input  [3:0]  wb_sel_i;
 
output [14:0] address;
input  [31:0] data;
 
reg  [31:0]  wb_dat_o;
reg          wb_ack_o;
reg  [14:0]  address;
 
reg        next_reading;
reg        reading;
 
 
//read_data:
always @(posedge clk or posedge reset)
begin
   if(reset==1)
   begin
     wb_ack_o<=#1 1'b0;
     wb_dat_o<=#1 1'b0;
   end
   else
   begin
     wb_dat_o <= #1 1'b0;
     wb_ack_o <= #1 1'b0;
     if (reading)
     begin
       wb_ack_o <= #1 1'b1;
       wb_dat_o <= #1 data;
     end
  end
end
 
reg [31:0] addr_var;
 
always @(wb_adr_i or wb_stb_i or wb_we_i or wb_cyc_i
         or reading or wb_ack_o)
 
   begin
 
   next_reading  = 1'b0;
 
   addr_var = wb_adr_i >> 2;
   address  = addr_var[14:0];
 
   if(~reading && ~wb_ack_o)
   begin
 
     if (wb_cyc_i && wb_stb_i && !wb_we_i)
     begin
       addr_var = wb_adr_i >> 2;
       address  = addr_var[14:0];
       next_reading  = 1'b1;
     end
 
   end
   if(reading)
     next_reading=1'b0;
 
 end
 
 
//register_proc:
always @(posedge clk or posedge reset)
 
   begin
 
   if (reset )
      begin
      reading  <= #1 1'b0;
      end
   else
      begin
      reading  <= #1 next_reading;
      end
   end
 
endmodule

Line No.	Rev	Author	Line
1	1327	jcastillo	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ROM Controller for Coregen ROM block ////`
4			`//// ////`
5			`//// ////`
6			`//// Description ////`
7			`//// Manages access from Wishbone to internal ROM ////`
8			`//// ////`
9			`//// To Do: ////`
10			`//// - nothing really ////`
11			`//// ////`
12			`//// Author(s): ////`
13	1575	jcastillo	`//// - Javier Castillo, javier.castillo@urjc.es ////`
14	1327	jcastillo	`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2004 OpenCores ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45	1575	jcastillo	`// Revision 1.1.1.1 2004/12/13 17:16:09 jcastillo`
46			`// Firt import of OR1200 over Celoxica RC203 platform`
47			`//`
48	1327	jcastillo
49			`// synopsys translate_off`
50			`include "timescale.v"
51			`// synopsys translate_on`
52
53			`module wb_rom_controller(clk,reset,`
54
55			`wb_stb_i,wb_dat_o,wb_dat_i,`
56			`wb_ack_o,wb_adr_i,wb_we_i,`
57			`wb_cyc_i,wb_sel_i,`
58
59			`address,data`
60			`);`
61
62			`input clk;`
63			`input reset;`
64
65			`input wb_stb_i;`
66			`output [31:0] wb_dat_o;`
67			`input [31:0] wb_dat_i;`
68			`output wb_ack_o;`
69			`input [31:0] wb_adr_i;`
70			`input wb_we_i;`
71			`input wb_cyc_i;`
72			`input [3:0] wb_sel_i;`
73
74			`output [14:0] address;`
75			`input [31:0] data;`
76
77			`reg [31:0] wb_dat_o;`
78			`reg wb_ack_o;`
79			`reg [14:0] address;`
80
81			`reg next_reading;`
82			`reg reading;`
83
84
85			`//read_data:`
86			`always @(posedge clk or posedge reset)`
87			`begin`
88			`if(reset==1)`
89			`begin`
90			`wb_ack_o<=#1 1'b0;`
91			`wb_dat_o<=#1 1'b0;`
92			`end`
93			`else`
94			`begin`
95			`wb_dat_o <= #1 1'b0;`
96			`wb_ack_o <= #1 1'b0;`
97			`if (reading)`
98			`begin`
99			`wb_ack_o <= #1 1'b1;`
100			`wb_dat_o <= #1 data;`
101			`end`
102			`end`
103			`end`
104
105			`reg [31:0] addr_var;`
106
107			`always @(wb_adr_i or wb_stb_i or wb_we_i or wb_cyc_i`
108			`or reading or wb_ack_o)`
109
110			`begin`
111
112			`next_reading = 1'b0;`
113
114			`addr_var = wb_adr_i >> 2;`
115			`address = addr_var[14:0];`
116
117			`if(~reading && ~wb_ack_o)`
118			`begin`
119
120			`if (wb_cyc_i && wb_stb_i && !wb_we_i)`
121			`begin`
122			`addr_var = wb_adr_i >> 2;`
123			`address = addr_var[14:0];`
124			`next_reading = 1'b1;`
125			`end`
126
127			`end`
128			`if(reading)`
129			`next_reading=1'b0;`
130
131			`end`
132
133
134			`//register_proc:`
135			`always @(posedge clk or posedge reset)`
136
137			`begin`
138
139			`if (reset )`
140			`begin`
141			`reading <= #1 1'b0;`
142			`end`
143			`else`
144			`begin`
145			`reading <= #1 next_reading;`
146			`end`
147			`end`
148
149			`endmodule`

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[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] [rc203/] [rc203_romcontroller.v] - Blame information for rev 1771