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[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] [uart16550/] [bench/] [verilog/] [uart_device_utilities.v] - Blame information for rev 1765

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_device_utilities.v                                     ////
////                                                              ////
////  This file is part of the "uart16550" project                ////
////  http://www.opencores.org/projects/uart16550/                ////
////                                                              ////
////  Author(s):                                                  ////
////      - tadej@opencores.org (Tadej Markovic)                  ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2004/03/27 03:55:16  tadejm
// Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.
//
//
//
 
 
`include "uart_defines.v"
`include "uart_testbench_defines.v"
`include "wb_model_defines.v"
`include "timescale.v"
 
module uart_device_utilities;
 
// UART receiver setting TASKs
//############################
 
  // Set RX length
  task set_rx_length;
    input   [3:0]  len;
  begin
    `UTILS_MSG("SETTING RX CHAR length.");
    testbench.i_uart_device.rx_length = len;
    `UTILS_VAL1("Length:", len);
  end
  endtask // set_rx_length
 
  // Enable RX odd parity
  task enable_rx_odd_parity;
  begin
    `UTILS_MSG("ENABLING RX CHAR odd parity.");
    testbench.i_uart_device.rx_odd_parity     = 1'b1;
    testbench.i_uart_device.rx_even_parity    = 1'b0;
    testbench.i_uart_device.rx_stick1_parity  = 1'b0;
    testbench.i_uart_device.rx_stick0_parity  = 1'b0;
    testbench.i_uart_device.rx_parity_enabled = 1'b1;
  end
  endtask // enable_rx_odd_parity
 
  // Enable RX even parity
  task enable_rx_even_parity;
  begin
    `UTILS_MSG("ENABLING RX CHAR even parity.");
    testbench.i_uart_device.rx_odd_parity     = 1'b0;
    testbench.i_uart_device.rx_even_parity    = 1'b1;
    testbench.i_uart_device.rx_stick1_parity  = 1'b0;
    testbench.i_uart_device.rx_stick0_parity  = 1'b0;
    testbench.i_uart_device.rx_parity_enabled = 1'b1;
  end
  endtask // enable_rx_even_parity
 
  // Enable RX stick1 parity
  task enable_rx_stick1_parity;
  begin
    `UTILS_MSG("ENABLING RX CHAR stick1 parity.");
    testbench.i_uart_device.rx_odd_parity     = 1'b0;
    testbench.i_uart_device.rx_even_parity    = 1'b0;
    testbench.i_uart_device.rx_stick1_parity  = 1'b1;
    testbench.i_uart_device.rx_stick0_parity  = 1'b0;
    testbench.i_uart_device.rx_parity_enabled = 1'b1;
  end
  endtask // enable_rx_stick1_parity
 
  // Enable RX stick0 parity
  task enable_rx_stick0_parity;
  begin
    `UTILS_MSG("ENABLING RX CHAR stick0 parity.");
    testbench.i_uart_device.rx_odd_parity     = 1'b0;
    testbench.i_uart_device.rx_even_parity    = 1'b0;
    testbench.i_uart_device.rx_stick1_parity  = 1'b0;
    testbench.i_uart_device.rx_stick0_parity  = 1'b1;
    testbench.i_uart_device.rx_parity_enabled = 1'b1;
  end
  endtask // enable_rx_stick0_parity
 
  // Disable RX parity
  task disable_rx_parity;
  begin
    `UTILS_MSG("DISABLING RX CHAR parity.");
    testbench.i_uart_device.rx_odd_parity     = 1'b0;
    testbench.i_uart_device.rx_even_parity    = 1'b0;
    testbench.i_uart_device.rx_stick1_parity  = 1'b0;
    testbench.i_uart_device.rx_stick0_parity  = 1'b0;
    testbench.i_uart_device.rx_parity_enabled = 1'b0;
  end
  endtask // disable_rx_parity
 
  // Set 1 or 2 (1.5) RX stop bits
  task set_rx_second_stop_bit;
    input          second_stop_bit;
  begin
    if (~second_stop_bit)
    begin
      `UTILS_MSG("SETTING RX CHAR 1 stop bit.");
    end
    else if (second_stop_bit && (testbench.i_uart_device.rx_length == 5))
    begin
      `UTILS_MSG("SETTING RX CHAR 1.5 stop bit.");
    end
    else
    begin
      `UTILS_MSG("SETTING RX CHAR 2 stop bits.");
    end
    testbench.i_uart_device.rx_stop_bit_1   = ~second_stop_bit;
    testbench.i_uart_device.rx_stop_bit_1_5 =  second_stop_bit & (testbench.i_uart_device.rx_length == 5);
    testbench.i_uart_device.rx_stop_bit_2   =  second_stop_bit & (testbench.i_uart_device.rx_length != 5);
  end
  endtask // set_rx_second_stop_bit
 
// UART transmitter setting TASKs
//###############################
 
  // Set TX length
  task set_tx_length;
    input   [3:0]  len;
  begin
    `UTILS_MSG("SETTING TX CHAR length.");
    testbench.i_uart_device.tx_length = len;
    `UTILS_VAL1("Length:", len);
  end
  endtask // set_tx_length
 
  // Enable TX odd parity
  task enable_tx_odd_parity;
  begin
    `UTILS_MSG("ENABLING TX CHAR odd parity.");
    testbench.i_uart_device.tx_odd_parity     = 1'b1;
    testbench.i_uart_device.tx_even_parity    = 1'b0;
    testbench.i_uart_device.tx_stick1_parity  = 1'b0;
    testbench.i_uart_device.tx_stick0_parity  = 1'b0;
    testbench.i_uart_device.tx_parity_enabled = 1'b1;
  end
  endtask // enable_tx_odd_parity
 
  // Enable TX even parity
  task enable_tx_even_parity;
  begin
    `UTILS_MSG("ENABLING TX CHAR even parity.");
    testbench.i_uart_device.tx_odd_parity     = 1'b0;
    testbench.i_uart_device.tx_even_parity    = 1'b1;
    testbench.i_uart_device.tx_stick1_parity  = 1'b0;
    testbench.i_uart_device.tx_stick0_parity  = 1'b0;
    testbench.i_uart_device.tx_parity_enabled = 1'b1;
  end
  endtask // enable_tx_even_parity
 
  // Enable TX stick1 parity
  task enable_tx_stick1_parity;
  begin
    `UTILS_MSG("ENABLING TX CHAR stick1 parity.");
    testbench.i_uart_device.tx_odd_parity     = 1'b0;
    testbench.i_uart_device.tx_even_parity    = 1'b0;
    testbench.i_uart_device.tx_stick1_parity  = 1'b1;
    testbench.i_uart_device.tx_stick0_parity  = 1'b0;
    testbench.i_uart_device.tx_parity_enabled = 1'b1;
  end
  endtask // enable_tx_stick1_parity
 
  // Enable TX stick0 parity
  task enable_tx_stick0_parity;
  begin
    `UTILS_MSG("ENABLING TX CHAR stick0 parity.");
    testbench.i_uart_device.tx_odd_parity     = 1'b0;
    testbench.i_uart_device.tx_even_parity    = 1'b0;
    testbench.i_uart_device.tx_stick1_parity  = 1'b0;
    testbench.i_uart_device.tx_stick0_parity  = 1'b1;
    testbench.i_uart_device.tx_parity_enabled = 1'b1;
  end
  endtask // enable_tx_stick0_parity
 
  // Disable TX parity
  task disable_tx_parity;
  begin
    `UTILS_MSG("DISABLING TX CHAR parity.");
    testbench.i_uart_device.tx_odd_parity     = 1'b0;
    testbench.i_uart_device.tx_even_parity    = 1'b0;
    testbench.i_uart_device.tx_stick1_parity  = 1'b0;
    testbench.i_uart_device.tx_stick0_parity  = 1'b0;
    testbench.i_uart_device.tx_parity_enabled = 1'b0;
  end
  endtask // disable_tx_parity
 
  // Correct TX parity
  task correct_tx_parity;
  begin
    `UTILS_MSG("DISABLING WRONG parity generation.");
    testbench.i_uart_device.tx_parity_wrong = 1'b0;
  end
  endtask // correct_tx_parity
 
  // Wrong TX parity
  task wrong_tx_parity;
  begin
    `UTILS_MSG("ENABLING WRONG parity generation.");
    testbench.i_uart_device.tx_parity_wrong = 1'b1;
  end
  endtask // wrong_tx_parity
 
  // Correct TX frame
  task correct_tx_frame;
  begin
    `UTILS_MSG("DISABLING WRONG frame generation.");
    testbench.i_uart_device.tx_framing_wrong = 1'b0;
  end
  endtask // correct_tx_frame
 
  // Wrong TX frame
  task wrong_tx_frame;
  begin
    `UTILS_MSG("ENABLING WRONG frame generation.");
    testbench.i_uart_device.tx_framing_wrong = 1'b1;
  end
  endtask // wrong_tx_frame
 
  // Generate TX glitch
  task generate_tx_glitch;
    input  [23:0]  generate_glitch_num;
  begin
    if (generate_glitch_num == 0)
    begin
      `UTILS_MSG("DISABLING 1 TIME glitch generation with CLKs delay.");
    end
    else
    begin
      `UTILS_MSG("ENABLING 1 TIME glitch generation with CLKs delay.");
    end
    testbench.i_uart_device.tx_glitch_num = generate_glitch_num;
    `UTILS_VAL1("CLKs delay from start bit edge:", generate_glitch_num);
  end
  endtask // generate_tx_glitch
 
  // Enable TX break
  task enable_tx_break;
    input  [15:0]  break_num;
  begin
    `UTILS_MSG("ENABLING brake generation with each TX CHAR with brake length.");
    testbench.i_uart_device.tx_break_enable = 1'b1;
    testbench.i_uart_device.tx_break_num = break_num;
    `UTILS_VAL1("Brake bit length:", break_num);
  end
  endtask // enable_tx_break
 
  // Disable TX break
  task disable_tx_break;
  begin
    `UTILS_MSG("DISABLING brake generation with each TX CHAR.");
    testbench.i_uart_device.tx_break_enable = 1'b0;
  end
  endtask // disable_tx_break
 
// UART transmitter send TASKs
//############################
 
  // Send character
  task send_char;
    input  [7:0]  char;
  begin
    testbench.i_uart_device.send_packet(1'b0, char, 1);
  end
  endtask // Send character
 
  // Send random character
  task send_rnd_char;
  begin
    testbench.i_uart_device.send_packet(1'b1, 8'h0, 1);
  end
  endtask // send_rnd_char
 
  // Send burst random character
  task send_burst_rnd_char;
    input  [31:0] num_of_char;
    integer       i;
  begin
    testbench.i_uart_device.send_packet(1'b1, 8'h0, num_of_char);
  end
  endtask // send_burst_rnd_char
 
 
endmodule

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[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] [uart16550/] [bench/] [verilog/] [uart_device_utilities.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	1327	jcastillo	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// uart_device_utilities.v ////`
4			`//// ////`
5			`//// This file is part of the "uart16550" project ////`
6			`//// http://www.opencores.org/projects/uart16550/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - tadej@opencores.org (Tadej Markovic) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2000 - 2004 authors ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45			`// Revision 1.1 2004/03/27 03:55:16 tadejm`
46			`// Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.`
47			`//`
48			`//`
49			`//`
50
51
52			`include "uart_defines.v"
53			`include "uart_testbench_defines.v"
54			`include "wb_model_defines.v"
55			`include "timescale.v"
56
57			`module uart_device_utilities;`
58
59			`// UART receiver setting TASKs`
60			`//############################`
61
62			`// Set RX length`
63			`task set_rx_length;`
64			`input [3:0] len;`
65			`begin`
66			`UTILS_MSG("SETTING RX CHAR length.");
67			`testbench.i_uart_device.rx_length = len;`
68			`UTILS_VAL1("Length:", len);
69			`end`
70			`endtask // set_rx_length`
71
72			`// Enable RX odd parity`
73			`task enable_rx_odd_parity;`
74			`begin`
75			`UTILS_MSG("ENABLING RX CHAR odd parity.");
76			`testbench.i_uart_device.rx_odd_parity = 1'b1;`
77			`testbench.i_uart_device.rx_even_parity = 1'b0;`
78			`testbench.i_uart_device.rx_stick1_parity = 1'b0;`
79			`testbench.i_uart_device.rx_stick0_parity = 1'b0;`
80			`testbench.i_uart_device.rx_parity_enabled = 1'b1;`
81			`end`
82			`endtask // enable_rx_odd_parity`
83
84			`// Enable RX even parity`
85			`task enable_rx_even_parity;`
86			`begin`
87			`UTILS_MSG("ENABLING RX CHAR even parity.");
88			`testbench.i_uart_device.rx_odd_parity = 1'b0;`
89			`testbench.i_uart_device.rx_even_parity = 1'b1;`
90			`testbench.i_uart_device.rx_stick1_parity = 1'b0;`
91			`testbench.i_uart_device.rx_stick0_parity = 1'b0;`
92			`testbench.i_uart_device.rx_parity_enabled = 1'b1;`
93			`end`
94			`endtask // enable_rx_even_parity`
95
96			`// Enable RX stick1 parity`
97			`task enable_rx_stick1_parity;`
98			`begin`
99			`UTILS_MSG("ENABLING RX CHAR stick1 parity.");
100			`testbench.i_uart_device.rx_odd_parity = 1'b0;`
101			`testbench.i_uart_device.rx_even_parity = 1'b0;`
102			`testbench.i_uart_device.rx_stick1_parity = 1'b1;`
103			`testbench.i_uart_device.rx_stick0_parity = 1'b0;`
104			`testbench.i_uart_device.rx_parity_enabled = 1'b1;`
105			`end`
106			`endtask // enable_rx_stick1_parity`
107
108			`// Enable RX stick0 parity`
109			`task enable_rx_stick0_parity;`
110			`begin`
111			`UTILS_MSG("ENABLING RX CHAR stick0 parity.");
112			`testbench.i_uart_device.rx_odd_parity = 1'b0;`
113			`testbench.i_uart_device.rx_even_parity = 1'b0;`
114			`testbench.i_uart_device.rx_stick1_parity = 1'b0;`
115			`testbench.i_uart_device.rx_stick0_parity = 1'b1;`
116			`testbench.i_uart_device.rx_parity_enabled = 1'b1;`
117			`end`
118			`endtask // enable_rx_stick0_parity`
119
120			`// Disable RX parity`
121			`task disable_rx_parity;`
122			`begin`
123			`UTILS_MSG("DISABLING RX CHAR parity.");
124			`testbench.i_uart_device.rx_odd_parity = 1'b0;`
125			`testbench.i_uart_device.rx_even_parity = 1'b0;`
126			`testbench.i_uart_device.rx_stick1_parity = 1'b0;`
127			`testbench.i_uart_device.rx_stick0_parity = 1'b0;`
128			`testbench.i_uart_device.rx_parity_enabled = 1'b0;`
129			`end`
130			`endtask // disable_rx_parity`
131
132			`// Set 1 or 2 (1.5) RX stop bits`
133			`task set_rx_second_stop_bit;`
134			`input second_stop_bit;`
135			`begin`
136			`if (~second_stop_bit)`
137			`begin`
138			`UTILS_MSG("SETTING RX CHAR 1 stop bit.");
139			`end`
140			`else if (second_stop_bit && (testbench.i_uart_device.rx_length == 5))`
141			`begin`
142			`UTILS_MSG("SETTING RX CHAR 1.5 stop bit.");
143			`end`
144			`else`
145			`begin`
146			`UTILS_MSG("SETTING RX CHAR 2 stop bits.");
147			`end`
148			`testbench.i_uart_device.rx_stop_bit_1 = ~second_stop_bit;`
149			`testbench.i_uart_device.rx_stop_bit_1_5 = second_stop_bit & (testbench.i_uart_device.rx_length == 5);`
150			`testbench.i_uart_device.rx_stop_bit_2 = second_stop_bit & (testbench.i_uart_device.rx_length != 5);`
151			`end`
152			`endtask // set_rx_second_stop_bit`
153
154			`// UART transmitter setting TASKs`
155			`//###############################`
156
157			`// Set TX length`
158			`task set_tx_length;`
159			`input [3:0] len;`
160			`begin`
161			`UTILS_MSG("SETTING TX CHAR length.");
162			`testbench.i_uart_device.tx_length = len;`
163			`UTILS_VAL1("Length:", len);
164			`end`
165			`endtask // set_tx_length`
166
167			`// Enable TX odd parity`
168			`task enable_tx_odd_parity;`
169			`begin`
170			`UTILS_MSG("ENABLING TX CHAR odd parity.");
171			`testbench.i_uart_device.tx_odd_parity = 1'b1;`
172			`testbench.i_uart_device.tx_even_parity = 1'b0;`
173			`testbench.i_uart_device.tx_stick1_parity = 1'b0;`
174			`testbench.i_uart_device.tx_stick0_parity = 1'b0;`
175			`testbench.i_uart_device.tx_parity_enabled = 1'b1;`
176			`end`
177			`endtask // enable_tx_odd_parity`
178
179			`// Enable TX even parity`
180			`task enable_tx_even_parity;`
181			`begin`
182			`UTILS_MSG("ENABLING TX CHAR even parity.");
183			`testbench.i_uart_device.tx_odd_parity = 1'b0;`
184			`testbench.i_uart_device.tx_even_parity = 1'b1;`
185			`testbench.i_uart_device.tx_stick1_parity = 1'b0;`
186			`testbench.i_uart_device.tx_stick0_parity = 1'b0;`
187			`testbench.i_uart_device.tx_parity_enabled = 1'b1;`
188			`end`
189			`endtask // enable_tx_even_parity`
190
191			`// Enable TX stick1 parity`
192			`task enable_tx_stick1_parity;`
193			`begin`
194			`UTILS_MSG("ENABLING TX CHAR stick1 parity.");
195			`testbench.i_uart_device.tx_odd_parity = 1'b0;`
196			`testbench.i_uart_device.tx_even_parity = 1'b0;`
197			`testbench.i_uart_device.tx_stick1_parity = 1'b1;`
198			`testbench.i_uart_device.tx_stick0_parity = 1'b0;`
199			`testbench.i_uart_device.tx_parity_enabled = 1'b1;`
200			`end`
201			`endtask // enable_tx_stick1_parity`
202
203			`// Enable TX stick0 parity`
204			`task enable_tx_stick0_parity;`
205			`begin`
206			`UTILS_MSG("ENABLING TX CHAR stick0 parity.");
207			`testbench.i_uart_device.tx_odd_parity = 1'b0;`
208			`testbench.i_uart_device.tx_even_parity = 1'b0;`
209			`testbench.i_uart_device.tx_stick1_parity = 1'b0;`
210			`testbench.i_uart_device.tx_stick0_parity = 1'b1;`
211			`testbench.i_uart_device.tx_parity_enabled = 1'b1;`
212			`end`
213			`endtask // enable_tx_stick0_parity`
214
215			`// Disable TX parity`
216			`task disable_tx_parity;`
217			`begin`
218			`UTILS_MSG("DISABLING TX CHAR parity.");
219			`testbench.i_uart_device.tx_odd_parity = 1'b0;`
220			`testbench.i_uart_device.tx_even_parity = 1'b0;`
221			`testbench.i_uart_device.tx_stick1_parity = 1'b0;`
222			`testbench.i_uart_device.tx_stick0_parity = 1'b0;`
223			`testbench.i_uart_device.tx_parity_enabled = 1'b0;`
224			`end`
225			`endtask // disable_tx_parity`
226
227			`// Correct TX parity`
228			`task correct_tx_parity;`
229			`begin`
230			`UTILS_MSG("DISABLING WRONG parity generation.");
231			`testbench.i_uart_device.tx_parity_wrong = 1'b0;`
232			`end`
233			`endtask // correct_tx_parity`
234
235			`// Wrong TX parity`
236			`task wrong_tx_parity;`
237			`begin`
238			`UTILS_MSG("ENABLING WRONG parity generation.");
239			`testbench.i_uart_device.tx_parity_wrong = 1'b1;`
240			`end`
241			`endtask // wrong_tx_parity`
242
243			`// Correct TX frame`
244			`task correct_tx_frame;`
245			`begin`
246			`UTILS_MSG("DISABLING WRONG frame generation.");
247			`testbench.i_uart_device.tx_framing_wrong = 1'b0;`
248			`end`
249			`endtask // correct_tx_frame`
250
251			`// Wrong TX frame`
252			`task wrong_tx_frame;`
253			`begin`
254			`UTILS_MSG("ENABLING WRONG frame generation.");
255			`testbench.i_uart_device.tx_framing_wrong = 1'b1;`
256			`end`
257			`endtask // wrong_tx_frame`
258
259			`// Generate TX glitch`
260			`task generate_tx_glitch;`
261			`input [23:0] generate_glitch_num;`
262			`begin`
263			`if (generate_glitch_num == 0)`
264			`begin`
265			`UTILS_MSG("DISABLING 1 TIME glitch generation with CLKs delay.");
266			`end`
267			`else`
268			`begin`
269			`UTILS_MSG("ENABLING 1 TIME glitch generation with CLKs delay.");
270			`end`
271			`testbench.i_uart_device.tx_glitch_num = generate_glitch_num;`
272			`UTILS_VAL1("CLKs delay from start bit edge:", generate_glitch_num);
273			`end`
274			`endtask // generate_tx_glitch`
275
276			`// Enable TX break`
277			`task enable_tx_break;`
278			`input [15:0] break_num;`
279			`begin`
280			`UTILS_MSG("ENABLING brake generation with each TX CHAR with brake length.");
281			`testbench.i_uart_device.tx_break_enable = 1'b1;`
282			`testbench.i_uart_device.tx_break_num = break_num;`
283			`UTILS_VAL1("Brake bit length:", break_num);
284			`end`
285			`endtask // enable_tx_break`
286
287			`// Disable TX break`
288			`task disable_tx_break;`
289			`begin`
290			`UTILS_MSG("DISABLING brake generation with each TX CHAR.");
291			`testbench.i_uart_device.tx_break_enable = 1'b0;`
292			`end`
293			`endtask // disable_tx_break`
294
295			`// UART transmitter send TASKs`
296			`//############################`
297
298			`// Send character`
299			`task send_char;`
300			`input [7:0] char;`
301			`begin`
302			`testbench.i_uart_device.send_packet(1'b0, char, 1);`
303			`end`
304			`endtask // Send character`
305
306			`// Send random character`
307			`task send_rnd_char;`
308			`begin`
309			`testbench.i_uart_device.send_packet(1'b1, 8'h0, 1);`
310			`end`
311			`endtask // send_rnd_char`
312
313			`// Send burst random character`
314			`task send_burst_rnd_char;`
315			`input [31:0] num_of_char;`
316			`integer i;`
317			`begin`
318			`testbench.i_uart_device.send_packet(1'b1, 8'h0, num_of_char);`
319			`end`
320			`endtask // send_burst_rnd_char`
321
322
323			`endmodule`