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[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] [uart16550/] [rtl/] [verilog-backup/] [uart_defines.v] - Blame information for rev 1765

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1 1327 jcastillo
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  uart_defines.v                                              ////
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////                                                              ////
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////                                                              ////
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////  This file is part of the "UART 16550 compatible" project    ////
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////  http://www.opencores.org/cores/uart16550/                   ////
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////                                                              ////
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////  Documentation related to this project:                      ////
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////  - http://www.opencores.org/cores/uart16550/                 ////
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////                                                              ////
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////  Projects compatibility:                                     ////
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////  - WISHBONE                                                  ////
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////  RS232 Protocol                                              ////
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////  16550D uart (mostly supported)                              ////
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////                                                              ////
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////  Overview (main Features):                                   ////
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////  Defines of the Core                                         ////
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////                                                              ////
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////  Known problems (limits):                                    ////
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////  None                                                        ////
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////                                                              ////
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////  To Do:                                                      ////
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////  Nothing.                                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - gorban@opencores.org                                  ////
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////      - Jacob Gorban                                          ////
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////                                                              ////
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////  Created:        2001/05/12                                  ////
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////  Last Updated:   2001/05/17                                  ////
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////                  (See log for the revision history)          ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Jacob Gorban, gorban@opencores.org        ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.5  2001/05/31 20:08:01  gorban
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// FIFO changes and other corrections.
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//
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// Revision 1.4  2001/05/21 19:12:02  gorban
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// Corrected some Linter messages.
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//
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// Revision 1.3  2001/05/17 18:34:18  gorban
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// First 'stable' release. Should be sythesizable now. Also added new header.
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//
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// Revision 1.0  2001-05-17 21:27:11+02  jacob
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// Initial revision
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//
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//
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`define UART_ADDR_WIDTH 3
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// Register addresses
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`define UART_REG_RB     3'd0    // receiver buffer
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`define UART_REG_TR  3'd0       // transmitter
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`define UART_REG_IE     3'd1    // Interrupt enable
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`define UART_REG_II  3'd2       // Interrupt identification
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`define UART_REG_FC  3'd2       // FIFO control
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`define UART_REG_LC     3'd3    // Line Control
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`define UART_REG_MC     3'd4    // Modem control
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`define UART_REG_LS  3'd5       // Line status
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`define UART_REG_MS  3'd6       // Modem status
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`define UART_REG_DL1    3'd0    // Divisor latch bytes (1-4)
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`define UART_REG_DL2    3'd1
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`define UART_REG_DL3    3'd4
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`define UART_REG_DL4    3'd5
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// Interrupt Enable register bits
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`define UART_IE_RDA     0        // Received Data available interrupt
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`define UART_IE_THRE    1       // Transmitter Holding Register empty interrupt
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`define UART_IE_RLS     2       // Receiver Line Status Interrupt
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`define UART_IE_MS      3       // Modem Status Interrupt
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// Interrupt Identification register bits
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`define UART_II_IP      0        // Interrupt pending when 0
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`define UART_II_II      3:1     // Interrupt identification
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// Interrupt identification values for bits 3:1
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`define UART_II_RLS     3'b011  // Receiver Line Status
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`define UART_II_RDA     3'b010  // Receiver Data available
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`define UART_II_TI      3'b110  // Timeout Indication
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`define UART_II_THRE    3'b001  // Transmitter Holding Register empty
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`define UART_II_MS      3'b000  // Modem Status
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// FIFO Control Register bits
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`define UART_FC_TL      1:0      // Trigger level
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// FIFO trigger level values
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`define UART_FC_1       2'b00
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`define UART_FC_4       2'b01
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`define UART_FC_8       2'b10
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`define UART_FC_14      2'b11
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// Line Control register bits
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`define UART_LC_BITS    1:0      // bits in character
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`define UART_LC_SB      2       // stop bits
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`define UART_LC_PE      3       // parity enable
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`define UART_LC_EP      4       // even parity
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`define UART_LC_SP      5       // stick parity
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`define UART_LC_BC      6       // Break control
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`define UART_LC_DL      7       // Divisor Latch access bit
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// Modem Control register bits
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`define UART_MC_DTR     0
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`define UART_MC_RTS     1
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`define UART_MC_OUT1    2
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`define UART_MC_OUT2    3
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`define UART_MC_LB      4       // Loopback mode
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// Line Status Register bits
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`define UART_LS_DR      0        // Data ready
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`define UART_LS_OE      1       // Overrun Error
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`define UART_LS_PE      2       // Parity Error
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`define UART_LS_FE      3       // Framing Error
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`define UART_LS_BI      4       // Break interrupt
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`define UART_LS_TFE     5       // Transmit FIFO is empty
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`define UART_LS_TE      6       // Transmitter Empty indicator
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`define UART_LS_EI      7       // Error indicator
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// Modem Status Register bits
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`define UART_MS_DCTS    0        // Delta signals
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`define UART_MS_DDSR    1
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`define UART_MS_TERI    2
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`define UART_MS_DDCD    3
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`define UART_MS_CCTS    4       // Complement signals
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`define UART_MS_CDSR    5
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`define UART_MS_CRI     6
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`define UART_MS_CDCD    7
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// FIFO parameter defines
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`define UART_FIFO_WIDTH 8
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`define UART_FIFO_DEPTH 16
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`define UART_FIFO_POINTER_W     4
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`define UART_FIFO_COUNTER_W     5
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// receiver fifo has width 10 because it has parity and framing error bits
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`define UART_FIFO_REC_WIDTH  10
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`define VERBOSE_WB  0           // All activity on the WISHBONE is recorded
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`define VERBOSE_LINE_STATUS 0   // Details about the lsr (line status register)
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`define FAST_TEST   1           // 64/1024 packets are sent
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