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jcastillo |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// uart_receiver.v ////
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//// ////
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//// ////
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//// This file is part of the "UART 16550 compatible" project ////
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//// http://www.opencores.org/cores/uart16550/ ////
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//// ////
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//// Documentation related to this project: ////
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//// - http://www.opencores.org/cores/uart16550/ ////
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//// ////
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//// Projects compatibility: ////
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//// - WISHBONE ////
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//// RS232 Protocol ////
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//// 16550D uart (mostly supported) ////
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//// ////
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//// Overview (main Features): ////
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//// UART core receiver logic ////
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//// ////
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//// Known problems (limits): ////
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//// None known ////
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//// ////
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//// To Do: ////
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//// Thourough testing. ////
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//// ////
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//// Author(s): ////
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//// - gorban@opencores.org ////
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//// - Jacob Gorban ////
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//// ////
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//// Created: 2001/05/12 ////
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//// Last Updated: 2001/05/17 ////
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//// (See log for the revision history) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Jacob Gorban, gorban@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2001/06/23 11:21:48 gorban
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// DL made 16-bit long. Fixed transmission/reception bugs.
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//
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// Revision 1.5 2001/06/02 14:28:14 gorban
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// Fixed receiver and transmitter. Major bug fixed.
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//
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// Revision 1.4 2001/05/31 20:08:01 gorban
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// FIFO changes and other corrections.
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//
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// Revision 1.3 2001/05/27 17:37:49 gorban
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// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
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//
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// Revision 1.2 2001/05/21 19:12:02 gorban
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// Corrected some Linter messages.
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//
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// Revision 1.1 2001/05/17 18:34:18 gorban
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// First 'stable' release. Should be sythesizable now. Also added new header.
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//
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// Revision 1.0 2001-05-17 21:27:11+02 jacob
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// Initial revision
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//
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//
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`include "timescale.v"
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`include "uart_defines.v"
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module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, rda_int,
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counter_t, counter_b, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, rx_lsr_mask);
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input clk;
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input wb_rst_i;
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input [7:0] lcr;
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input rf_pop;
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input srx_pad_i;
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input enable;
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input rda_int;
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input rx_reset;
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input rx_lsr_mask;
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output [5:0] counter_t;
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output [3:0] counter_b;
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output [`UART_FIFO_COUNTER_W-1:0] rf_count;
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output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
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output rf_overrun;
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output rf_error_bit;
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reg [3:0] rstate;
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reg [3:0] rcounter16;
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reg [2:0] rbit_counter;
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reg [7:0] rshift; // receiver shift register
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reg rparity; // received parity
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reg rparity_error;
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reg rframing_error; // framing error flag
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reg rbit_in;
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reg rparity_xor;
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// RX FIFO signals
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reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;
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wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
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reg rf_push;
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wire rf_pop;
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wire rf_underrun;
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wire rf_overrun;
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wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
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wire rf_error_bit; // an error (parity or framing) is inside the fifo
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// RX FIFO instance
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uart_fifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
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.clk( clk ),
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.wb_rst_i( wb_rst_i ),
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.data_in( rf_data_in ),
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.data_out( rf_data_out ),
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.push( rf_push ),
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.pop( rf_pop ),
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.underrun( rf_underrun ),
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.overrun( rf_overrun ),
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.count( rf_count ),
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.error_bit( rf_error_bit ),
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.fifo_reset( rx_reset ),
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.reset_status(rx_lsr_mask)
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);
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wire rcounter16_eq_7 = (rcounter16 == 4'd7);
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wire rcounter16_eq_0 = (rcounter16 == 4'd0);
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wire rcounter16_eq_1 = (rcounter16 == 4'd1);
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wire [3:0] rcounter16_minus_1 = rcounter16 - 4'd1;
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parameter sr_idle = 4'd0;
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parameter sr_rec_start = 4'd1;
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parameter sr_rec_bit = 4'd2;
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parameter sr_rec_parity = 4'd3;
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parameter sr_rec_stop = 4'd4;
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parameter sr_check_parity = 4'd5;
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parameter sr_rec_prepare = 4'd6;
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parameter sr_end_bit = 4'd7;
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parameter sr_ca_lc_parity = 4'd8;
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parameter sr_wait1 = 4'd9;
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parameter sr_push = 4'd10;
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parameter sr_last = 4'd11;
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always @(posedge clk or posedge wb_rst_i)
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begin
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if (wb_rst_i)
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begin
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rstate <= #1 sr_idle;
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rbit_in <= #1 1'b0;
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rcounter16 <= #1 0;
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rbit_counter <= #1 0;
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rparity_xor <= #1 1'b0;
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rframing_error <= #1 1'b0;
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rparity_error <= #1 1'b0;
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rparity <= #1 1'b0;
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rshift <= #1 0;
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rf_push <= #1 1'b0;
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rf_data_in <= #1 0;
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end
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else
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if (enable)
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begin
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case (rstate)
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sr_idle : if (srx_pad_i==1'b0) // detected a pulse (start bit?)
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begin
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rstate <= #1 sr_rec_start;
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rcounter16 <= #1 4'b1110;
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end
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else
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rstate <= #1 sr_idle;
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sr_rec_start : begin
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if (rcounter16_eq_7) // check the pulse
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if (srx_pad_i==1'b1) // no start bit
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rstate <= #1 sr_idle;
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else // start bit detected
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rstate <= #1 sr_rec_prepare;
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rcounter16 <= #1 rcounter16_minus_1;
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end
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sr_rec_prepare:begin
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case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
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2'b00 : rbit_counter <= #1 3'b100;
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2'b01 : rbit_counter <= #1 3'b101;
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2'b10 : rbit_counter <= #1 3'b110;
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2'b11 : rbit_counter <= #1 3'b111;
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endcase
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if (rcounter16_eq_0)
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begin
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rstate <= #1 sr_rec_bit;
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rcounter16 <= #1 4'b1110;
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rshift <= #1 0;
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end
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else
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rstate <= #1 sr_rec_prepare;
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rcounter16 <= #1 rcounter16_minus_1;
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end
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sr_rec_bit : begin
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if (rcounter16_eq_0)
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rstate <= #1 sr_end_bit;
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if (rcounter16_eq_7) // read the bit
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case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
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2'b00 : rshift[4:0] <= #1 {srx_pad_i, rshift[4:1]};
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2'b01 : rshift[5:0] <= #1 {srx_pad_i, rshift[5:1]};
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2'b10 : rshift[6:0] <= #1 {srx_pad_i, rshift[6:1]};
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2'b11 : rshift[7:0] <= #1 {srx_pad_i, rshift[7:1]};
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endcase
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rcounter16 <= #1 rcounter16_minus_1;
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end
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sr_end_bit : begin
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if (rbit_counter==3'b0) // no more bits in word
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if (lcr[`UART_LC_PE]) // choose state based on parity
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rstate <= #1 sr_rec_parity;
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else
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begin
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rstate <= #1 sr_rec_stop;
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rparity_error <= #1 1'b0; // no parity - no error :)
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end
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else // else we have more bits to read
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begin
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rstate <= #1 sr_rec_bit;
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rbit_counter <= #1 rbit_counter - 3'b1;
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end
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rcounter16 <= #1 4'b1110;
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end
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sr_rec_parity: begin
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if (rcounter16_eq_7) // read the parity
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begin
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rparity <= #1 srx_pad_i;
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rstate <= #1 sr_ca_lc_parity;
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end
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rcounter16 <= #1 rcounter16_minus_1;
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end
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sr_ca_lc_parity : begin // rcounter equals 6
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rcounter16 <= #1 rcounter16_minus_1;
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rparity_xor <= #1 ^{rshift,rparity}; // calculate parity on all incoming data
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rstate <= #1 sr_check_parity;
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end
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sr_check_parity: begin // rcounter equals 5
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case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
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// 2'b00: rparity_error <= #1 ~rparity_xor; // no error if parity 1
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// 2'b01: rparity_error <= #1 ~rparity; // parity should sticked to 1
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// 2'b10: rparity_error <= #1 rparity_xor; // error if parity is odd
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// 2'b11: rparity_error <= #1 rparity; // parity should be sticked to 0
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2'b00: rparity_error <= #1 rparity_xor; // no error if parity 1
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2'b01: rparity_error <= #1 1'b1; // parity should sticked to 1
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2'b10: rparity_error <= #1 ~rparity_xor; // error if parity is odd
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2'b11: rparity_error <= #1 1'b0; // parity should be sticked to 0
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endcase
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rcounter16 <= #1 rcounter16_minus_1;
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rstate <= #1 sr_wait1;
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end
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sr_wait1 : if (rcounter16_eq_0)
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begin
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| 275 |
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rstate <= #1 sr_rec_stop;
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rcounter16 <= #1 4'b1110;
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end
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else
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rcounter16 <= #1 rcounter16_minus_1;
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sr_rec_stop : begin
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if (rcounter16_eq_7) // read the parity
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begin
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| 283 |
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rframing_error <= #1 !srx_pad_i; // no framing error if input is 1 (stop bit)
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| 284 |
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rf_data_in <= #1 {rshift, rparity_error, rframing_error};
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rstate <= #1 sr_push;
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end
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| 287 |
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rcounter16 <= #1 rcounter16_minus_1;
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end
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sr_push : begin
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///////////////////////////////////////
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// $display($time, ": received: %b", rf_data_in);
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rf_push <= #1 1'b1;
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rstate <= #1 sr_last;
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end
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sr_last : begin
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if (rcounter16_eq_1)
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rstate <= #1 sr_idle;
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rcounter16 <= #1 rcounter16_minus_1;
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rf_push <= #1 1'b0;
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end
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default : rstate <= #1 sr_idle;
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endcase
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end // if (enable)
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end // always of receiver
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| 305 |
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//
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| 307 |
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// Break condition detection.
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// Works in conjuction with the receiver state machine
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| 309 |
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reg [3:0] counter_b; // counts the 1 (idle) signals
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| 310 |
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| 311 |
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always @(posedge clk or posedge wb_rst_i)
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begin
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if (wb_rst_i)
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counter_b <= #1 4'd11;
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else
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if (enable) // only work on enable times
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if (!srx_pad_i) // Ta vrstica je bila spremenjena igor !!!
|
| 318 |
|
|
counter_b <= #1 4'd11; // maximum character time length - 1
|
| 319 |
|
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else
|
| 320 |
|
|
if (counter_b != 4'b0) // break reached
|
| 321 |
|
|
counter_b <= #1 counter_b - 4'd1; // decrement break counter
|
| 322 |
|
|
end // always of break condition detection
|
| 323 |
|
|
|
| 324 |
|
|
///
|
| 325 |
|
|
/// Timeout condition detection
|
| 326 |
|
|
reg [5:0] counter_t; // counts the timeout condition clocks
|
| 327 |
|
|
|
| 328 |
|
|
always @(posedge clk or posedge wb_rst_i)
|
| 329 |
|
|
begin
|
| 330 |
|
|
if (wb_rst_i)
|
| 331 |
|
|
counter_t <= #1 6'd44;
|
| 332 |
|
|
else
|
| 333 |
|
|
if (enable)
|
| 334 |
|
|
if(rf_push || rf_pop || rda_int) // counter is reset when RX FIFO is accessed or above trigger level
|
| 335 |
|
|
counter_t <= #1 6'd44;
|
| 336 |
|
|
else
|
| 337 |
|
|
if (counter_t != 6'b0) // we don't want to underflow
|
| 338 |
|
|
counter_t <= #1 counter_t - 6'd1;
|
| 339 |
|
|
end
|
| 340 |
|
|
|
| 341 |
|
|
endmodule
|
