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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [jtag/] [jp2.c] - Blame information for rev 1772

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Line No. Rev Author Line
1 1581 jcastillo 
/* jp2-linux.c -- JTAG protocol via parallel port for linux
2 
   Copyright(C) 2001 Marko Mlinar, markom@opencores.org
3 
   Code for TCP/IP copied from gdb, by Chris Ziomkowski
4 
 
5 
This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
This program is free software; you can redistribute it and/or modify
8 
it under the terms of the GNU General Public License as published by
9 
the Free Software Foundation; either version 2 of the License, or
10 
(at your option) any later version.
11 
 
12 
This program is distributed in the hope that it will be useful,
13 
but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
GNU General Public License for more details.
16 
 
17 
You should have received a copy of the GNU General Public License
18 
along with this program; if not, write to the Free Software
19 
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
20 
 
21 
/* Establishes jtag proxy server and communicates with parallel
22 
 port directly.  Requires root access. */
23 
 
24 
#include <assert.h>
25 
#include <stdio.h>
26 
#include <ctype.h>
27 
#include <string.h>
28 
#include <stdlib.h>
29 
#include <unistd.h>
30 
#include <stdarg.h>
31 
#include <sys/stat.h>
32 
#include <sys/types.h>
33 
 
34 
#include "mc.h"
35 
#include "gdb.h"
36 
#include "jp2.h"
37 
#include "jp.h"
38 
 
39 
#define TC_RESET           0
40 
#define TC_BRIGHT          1
41 
#define TC_DIM             2
42 
#define TC_UNDERLINE       3
43 
#define TC_BLINK           4
44 
#define TC_REVERSE         7
45 
#define TC_HIDDEN          8
46 
 
47 
#define TC_BLACK           0
48 
#define TC_RED             1
49 
#define TC_GREEN           2
50 
#define TC_YELLOW          3
51 
#define TC_BLUE            4
52 
#define TC_MAGENTA         5
53 
#define TC_CYAN            6
54 
#define TC_WHITE           7
55 
 
56 
#define SDRAM_BASE       0x00000000
57 
#define SDRAM_SIZE       0x04000000
58 
#define SRAM_BASE        0x40000000
59 
#define SRAM_SIZE        0x04000000 // This is not ok
60 
 
61 
 
62 
int err = 0;
63 
int set_pc = 0;
64 
int set_step = 0;
65 
int waiting = 0;
66 
 
67 
/* Scan chain info. */
68 
static int chain_addr_size[] = { 0,  32, 0,  0,  5,  32, 32};
69 
static int chain_data_size[] = { 0,  32, 0,  32, 32, 32, 32};
70 
static int chain_is_valid[]  = { 0,  1,  0,  1,  1,  1,   1};
71 
static int chain_has_crc[]   = { 0,  1,  0,  1,  1,  1,   1};
72 
static int chain_has_rw[]    = { 0,  1,  0,  0,  1,  1,   1};
73 
 
74 
/* Currently selected scan chain - just to prevent unnecessary
75 
   transfers. */
76 
static int current_chain = -1;
77 
 
78 
/* The chain that should be currently selected. */
79 
static int dbg_chain = -1;
80 
 
81 
/* Crc of current read or written data.  */
82 
static int crc_r, crc_w = 0;
83 
 
84 
/* Address of previous read */
85 
static unsigned long prev_regno = 0;
86 
 
87 
/* Generates new crc, sending in new bit input_bit */
88 
static unsigned long crc_calc(unsigned long crc, int input_bit) {
89 
  unsigned long d = (input_bit&1) ? 0xfffffff : 0x0000000;
90 
  unsigned long crc_32 = ((crc >> 31)&1) ? 0xfffffff : 0x0000000;
91 
  crc <<= 1;
92 
  return crc ^ (d ^ crc_32) & DBG_CRC_POLY;
93 
}
94 
 
95 
/* Writes TCLK=0, TRST=1, TMS=bit1, TDI=bit0
96 
   and    TCLK=1, TRST=1, TMS=bit1, TDI=bit0 */
97 
static void jp2_write_JTAG(uint8_t packet) {
98 
  uint8_t data = TRST_BIT;
99 
  if(packet & 1) data |= TDI_BIT;
100 
  if(packet & 2) data |= TMS_BIT;
101 
 
102 
  jp_out(data);
103 
  jp_wait();
104 
  crc_w = crc_calc(crc_w, packet&1);
105 
 
106 
  /* rise clock */
107 
  jp_out(data | TCLK_BIT);
108 
  jp_wait();
109 
}
110 
 
111 
/* Reads TDI.  */
112 
static int jp2_read_JTAG() {
113 
  uint8_t data;
114 
  data = jp_in();
115 
  crc_r = crc_calc(crc_r, data);
116 
  return data;
117 
}
118 
 
119 
/* Writes bitstream.  LS bit first if len < 0, MS bit first if len > 0.  */
120 
static void jp2_write_stream(ULONGEST stream, int len, int set_last_bit) {
121 
  int i;
122 
  if (len < 0) {
123 
    len = -len;
124 
    debug("writeL%d(", len);
125 
    for(i = 0; i < len - 1; i++)
126 
      jp2_write_JTAG((stream >> i) & 1);
127 
 
128 
    if(set_last_bit) jp2_write_JTAG((stream >>(len - 1))& 1 | TMS);
129 
    else jp2_write_JTAG((stream >>(len - 1))& 1);
130 
  } else {
131 
    debug("write%d(", len);
132 
    for(i = 0; i < len - 1; i++)
133 
      jp2_write_JTAG((stream >> (len - 1 - i)) & 1);
134 
 
135 
    if(set_last_bit) jp2_write_JTAG((stream >> 0) & 1 | TMS);
136 
    else jp2_write_JTAG((stream >> 0)& 1);
137 
  }
138 
  debug(")\n");
139 
}
140 
 
141 
/* Gets bitstream.  LS bit first if len < 0, MS bit first if len > 0.  */
142 
static ULONGEST jp2_read_stream(unsigned long stream, int len, int set_last_bit) {
143 
  int i;
144 
  ULONGEST data = 0;
145 
  if (len < 0) {
146 
    debug("readL(");
147 
    for(i = 0; i < len - 1; i++) {
148 
      jp2_write_JTAG((stream >> i) & 1);   /* LSB first */
149 
      data |= jp2_read_JTAG() << i; /* LSB first */
150 
    }
151 
 
152 
    if (set_last_bit) jp2_write_JTAG((stream >> (len - 1)) & 1 | TMS);
153 
    else jp2_write_JTAG((stream >> (len - 1)) & 1);
154 
    data |= jp2_read_JTAG() << (len - 1);
155 
  } else {
156 
    debug("read(");
157 
    for(i = 0; i < len - 1; i++) {
158 
      jp2_write_JTAG((stream >> (len - 1 - i)) & 1);   /* MSB first */
159 
      data |= jp2_read_JTAG() << (len - 1 - i); /* MSB first */
160 
    }
161 
 
162 
    if (set_last_bit) jp2_write_JTAG((stream >> 0) & 1 | TMS);
163 
    else jp2_write_JTAG((stream >> 0) & 1);
164 
    data |= jp2_read_JTAG() << 0;
165 
  }
166 
  debug(")\n");
167 
  return data;
168 
}
169 
 
170 
/* Sets scan chain.  */
171 
void jtag_set_ir(int ir) {
172 
  jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
173 
  jp2_write_JTAG(TMS); /* SELECT_IR SCAN */
174 
 
175 
  jp2_write_JTAG(0); /* CAPTURE_IR */
176 
  jp2_write_JTAG(0); /* SHIFT_IR */
177 
 
178 
  /* write data, EXIT1_IR */
179 
  jp2_write_stream(ir, -JI_SIZE, 1);
180 
 
181 
  jp2_write_JTAG(TMS); /* UPDATE_IR */
182 
  jp2_write_JTAG(0); /* IDLE */
183 
  current_chain = -1;
184 
}
185 
 
186 
/* Resets JTAG
187 
   Writes TRST=0
188 
   and    TRST=1 */
189 
static void jp2_reset_JTAG() {
190 
  int i;
191 
  debug2("\nreset(");
192 
  jp_out(0);
193 
  JTAG_RETRY_WAIT();
194 
  /* In case we don't have TRST reset it manually */
195 
  for(i = 0; i < 8; i++) jp2_write_JTAG(TMS);
196 
  jp_out(TRST_BIT);
197 
  JTAG_RETRY_WAIT();
198 
  jp2_write_JTAG(0);
199 
  debug2(")\n");
200 
}
201 
 
202 
/* Resets JTAG, and sets DEBUG scan chain */
203 
static int dbg_reset() {
204 
  int err;
205 
  unsigned long id;
206 
  jp2_reset_JTAG();
207 
 
208 
  /* read ID */
209 
  jtag_set_ir(JI_IDCODE);
210 
  jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
211 
  jp2_write_JTAG(0); /* CAPTURE_DR */
212 
  jp2_write_JTAG(0); /* SHIFT_DR */
213 
  /* read ID, EXIT1_DR */
214 
  crc_w = 0xffffffff;
215 
  id = jp2_read_stream(0, 32, 1);
216 
  jp2_write_JTAG(TMS); /* UPDATE_DR */
217 
  jp2_write_JTAG(0); /* IDLE */
218 
  printf("JTAG ID = %08x\n", id);
219 
 
220 
  /* select debug scan chain and stay in it forever */
221 
  jtag_set_ir(JI_DEBUG);
222 
  current_chain = -1;
223 
  return DBG_ERR_OK;
224 
}
225 
 
226 
/* counts retries and returns zero if we should abort */
227 
/* TODO: dinamically adjust timings for jp2 */
228 
static int retry_no = 0;
229 
int retry_do() {
230 
  int i, err;
231 
  printf("RETRY\n");
232 
  //exit(2);
233 
  if (retry_no >= NUM_SOFT_RETRIES) {
234 
    if ((err = dbg_reset())) return err;
235 
  } else { /* quick reset */
236 
    for(i = 0; i < 8; i++) jp2_write_JTAG(TMS);
237 
    jp2_write_JTAG(0); /* go into IDLE state */
238 
  }
239 
  if (retry_no >= NUM_SOFT_RETRIES + NUM_HARD_RETRIES) {
240 
    retry_no = 0;
241 
    return 0;
242 
  }
243 
  retry_no++;
244 
  return 1;
245 
}
246 
 
247 
/* resets retry counter */
248 
void retry_ok() {
249 
  retry_no = 0;
250 
}
251 
 
252 
/* Sets scan chain.  */
253 
int dbg_set_chain(int chain) {
254 
  int status, crc_generated, crc_read;
255 
  dbg_chain = chain;
256 
 
257 
try_again:
258 
  if (current_chain == chain) return DBG_ERR_OK;
259 
  current_chain = -1;
260 
  debug("\n");
261 
  debug2("set_chain %i\n", chain);
262 
  jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
263 
  jp2_write_JTAG(0); /* CAPTURE_DR */
264 
  jp2_write_JTAG(0); /* SHIFT_DR */
265 
 
266 
  /* write data, EXIT1_DR */
267 
  crc_w = 0xffffffff;
268 
  jp2_write_stream((chain & 0xf | (1<<DC_SIZE)), DC_SIZE + 1, 0);
269 
  jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
270 
  crc_r = 0xffffffff;
271 
  status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
272 
  crc_generated = crc_r;
273 
  crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
274 
 
275 
  //printf("%x %x %x\n", status, crc_read, crc_generated);
276 
  /* CRCs must match, otherwise retry */
277 
  if (crc_read != crc_generated) {
278 
    if (retry_do()) goto try_again;
279 
    else return DBG_ERR_CRC;
280 
  }
281 
  /* we should read expected status value, otherwise retry */
282 
  if (status != 0) {
283 
    if (retry_do()) goto try_again;
284 
    else return status;
285 
  }
286 
 
287 
  /* reset retry counter */
288 
  retry_ok();
289 
 
290 
  jp2_write_JTAG(TMS); /* UPDATE_DR */
291 
  jp2_write_JTAG(0); /* IDLE */
292 
  current_chain = chain;
293 
  return DBG_ERR_OK;
294 
}
295 
 
296 
/* sends out a command with 32bit address and 16bit length, if len >= 0 */
297 
int dbg_command(int type, unsigned long adr, int len) {
298 
  int status, crc_generated, crc_read;
299 
 
300 
try_again:
301 
  dbg_set_chain(dbg_chain);
302 
  debug("\n");
303 
  debug2("comm %i\n", type);
304 
 
305 
  /***** WRITEx *****/
306 
  jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
307 
  jp2_write_JTAG(0); /* CAPTURE_DR */
308 
  jp2_write_JTAG(0); /* SHIFT_DR */
309 
 
310 
  /* write data, EXIT1_DR */
311 
  crc_w = 0xffffffff;
312 
  jp2_write_stream((DI_WRITE_CMD & 0xf | (0<<DC_SIZE)), DC_SIZE + 1, 0);
313 
  jp2_write_stream(type, 4, 0);
314 
  jp2_write_stream(adr, 32, 0);
315 
  assert(len > 0);
316 
  jp2_write_stream(len - 1, 16, 0);
317 
  jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
318 
  crc_r = 0xffffffff;
319 
  status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
320 
  crc_generated = crc_r;
321 
  crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
322 
 
323 
  /* CRCs must match, otherwise retry */
324 
  if (crc_read != crc_generated) {
325 
    if (retry_do()) goto try_again;
326 
    else return DBG_ERR_CRC;
327 
  }
328 
  /* we should read expected status value, otherwise retry */
329 
  if (status != 0) {
330 
    if (retry_do()) goto try_again;
331 
    else return status;
332 
  }
333 
  jp2_write_JTAG(TMS); /* UPDATE_DR */
334 
  jp2_write_JTAG(0); /* IDLE */
335 
 
336 
  /* reset retry counter */
337 
  retry_ok();
338 
  return DBG_ERR_OK;
339 
}
340 
 
341 
/* writes a ctrl reg */
342 
int dbg_ctrl(int reset, int stall) {
343 
  int status, crc_generated, crc_read;
344 
 
345 
try_again:
346 
  dbg_set_chain(dbg_chain);
347 
  debug("\n");
348 
  debug2("ctrl\n");
349 
 
350 
  /***** WRITEx *****/
351 
  jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
352 
  jp2_write_JTAG(0); /* CAPTURE_DR */
353 
  jp2_write_JTAG(0); /* SHIFT_DR */
354 
 
355 
  /* write data, EXIT1_DR */
356 
  crc_w = 0xffffffff;
357 
  jp2_write_stream((DI_WRITE_CTRL & 0xf | (0<<DC_SIZE)), DC_SIZE + 1, 0);
358 
  jp2_write_stream(reset, 1, 0);
359 
  jp2_write_stream(stall, 1, 0);
360 
  jp2_write_stream(0, 50, 0);
361 
  jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
362 
  crc_r = 0xffffffff;
363 
  status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
364 
  crc_generated = crc_r;
365 
  crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
366 
 
367 
  /* CRCs must match, otherwise retry */
368 
  //printf("%x %x %x\n", status, crc_read, crc_generated);
369 
  if (crc_read != crc_generated) {
370 
    if (retry_do()) goto try_again;
371 
    else return DBG_ERR_CRC;
372 
  }
373 
  /* we should read expected status value, otherwise retry */
374 
  if (status != 0) {
375 
    if (retry_do()) goto try_again;
376 
    else return status;
377 
  }
378 
  jp2_write_JTAG(TMS); /* UPDATE_DR */
379 
  jp2_write_JTAG(0); /* IDLE */
380 
 
381 
  /* reset retry counter */
382 
  retry_ok();
383 
  return DBG_ERR_OK;
384 
}
385 
 
386 
/* reads control register */
387 
int dbg_ctrl_read(int *reset, int *stall) {
388 
  int status, crc_generated, crc_read;
389 
 
390 
try_again:
391 
  dbg_set_chain(dbg_chain);
392 
  debug("\n");
393 
  debug2("ctrl_read\n");
394 
 
395 
  jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
396 
  jp2_write_JTAG(0); /* CAPTURE_DR */
397 
  jp2_write_JTAG(0); /* SHIFT_DR */
398 
 
399 
  /* write data, EXIT1_DR */
400 
  crc_w = 0xffffffff;
401 
  jp2_write_stream(DI_READ_CTRL | (0<<DC_SIZE), DC_SIZE + 1, 0);
402 
  jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
403 
  crc_r = 0xffffffff;
404 
  *reset = jp2_read_stream(0, 1, 0);
405 
  *stall = jp2_read_stream(0, 1, 0);
406 
  jp2_read_stream(0, 50, 0);
407 
  status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
408 
  crc_generated = crc_r;
409 
  crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
410 
 
411 
  /* CRCs must match, otherwise retry */
412 
  //printf("%x %x %x\n", status, crc_read, crc_generated);
413 
  if (crc_read != crc_generated) {
414 
    if (retry_do()) goto try_again;
415 
    else return DBG_ERR_CRC;
416 
  }
417 
  /* we should read expected status value, otherwise retry */
418 
  if (status != 0) {
419 
    if (retry_do()) goto try_again;
420 
    else return status;
421 
  }
422 
  jp2_write_JTAG(TMS); /* UPDATE_DR */
423 
  jp2_write_JTAG(0); /* IDLE */
424 
 
425 
  /* reset retry counter */
426 
  retry_ok();
427 
  return DBG_ERR_OK;
428 
}
429 
/* issues a burst read/write */
430 
int dbg_go(unsigned char *data, unsigned short len, int read) {
431 
  int status, crc_generated, crc_read;
432 
  int i;
433 
 
434 
try_again:
435 
  dbg_set_chain(dbg_chain);
436 
  debug("\n");
437 
  debug2("go len = %d\n", len);
438 
 
439 
  jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
440 
  jp2_write_JTAG(0); /* CAPTURE_DR */
441 
  jp2_write_JTAG(0); /* SHIFT_DR */
442 
 
443 
  /* write data, EXIT1_DR */
444 
  crc_w = 0xffffffff;
445 
  jp2_write_stream(DI_GO | (0<<DC_SIZE), DC_SIZE + 1, 0);
446 
  if (!read) {
447 
    /* reverse byte ordering, since we must send in big endian */
448 
    for (i = 0; i < len; i++)
449 
      jp2_write_stream(data[i], 8, 0);
450 
  }
451 
  jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
452 
  crc_r = 0xffffffff;
453 
  if (read) {
454 
    /* reverse byte ordering, since we must send in big endian */
455 
    for (i = 0; i < len; i++)
456 
      data[i] = jp2_read_stream(data[i], 8, 0);
457 
  }
458 
  status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
459 
  crc_generated = crc_r;
460 
  crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
461 
 
462 
  /* CRCs must match, otherwise retry */
463 
  //printf("%x %x %x\n", status, crc_read, crc_generated);
464 
  if (crc_read != crc_generated) {
465 
    if (retry_do()) goto try_again;
466 
    else return DBG_ERR_CRC;
467 
  }
468 
  /* we should read expected status value, otherwise retry */
469 
  if (status != 0) {
470 
    if (retry_do()) goto try_again;
471 
    else return status;
472 
  }
473 
  jp2_write_JTAG(TMS); /* UPDATE_DR */
474 
  jp2_write_JTAG(0); /* IDLE */
475 
 
476 
  /* reset retry counter */
477 
  retry_ok();
478 
  return DBG_ERR_OK;
479 
}
480 
 
481 
/* read a word from wishbone */
482 
int dbg_wb_read32(unsigned long adr, unsigned long *data) {
483 
  int err;
484 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
485 
  if ((err = dbg_command(0x6, adr, 4))) return err;
486 
  if ((err = dbg_go((unsigned char*)data, 4, 1))) return err;
487 
  *data = ntohl(*data);
488 
  return err;
489 
}
490 
 
491 
/* write a word to wishbone */
492 
int dbg_wb_write32(unsigned long adr, unsigned long data) {
493 
  int err;
494 
  data = ntohl(data);
495 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
496 
  if ((err = dbg_command(0x2, adr, 4))) return err;
497 
  if ((err = dbg_go((unsigned char*)&data, 4, 0))) return err;
498 
  return DBG_ERR_OK;
499 
}
500 
 
501 
/* write a word to wishbone */
502 
int dbg_wb_write16(unsigned long adr, unsigned short data) {
503 
  int err;
504 
  data = ntohs(data);
505 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
506 
  if ((err = dbg_command(0x1, adr, 2))) return err;
507 
  if ((err = dbg_go((unsigned char*)&data, 2, 0))) return err;
508 
  return DBG_ERR_OK;
509 
}
510 
 
511 
/* write a word to wishbone */
512 
int dbg_wb_write8(unsigned long adr, unsigned long data) {
513 
  int err;
514 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
515 
  if ((err = dbg_command(0x0, adr, 1))) return err;
516 
  if ((err = dbg_go((unsigned char*)&data, 1, 0))) return err;
517 
  return DBG_ERR_OK;
518 
}
519 
 
520 
/* read a block from wishbone */
521 
int dbg_wb_read_block32(unsigned long adr, unsigned long *data, int len) {
522 
  int i, err;
523 
  //printf("%08x %08x\n", adr, len);
524 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
525 
  if ((err = dbg_command(0x6, adr, len))) return err;
526 
  if ((err = dbg_go((unsigned char*)data, len, 1))) return err;
527 
  for (i = 0; i < len / 4; i ++) data[i] = ntohl(data[i]);
528 
  //printf("%08x\n", err);
529 
  return DBG_ERR_OK;
530 
}
531 
 
532 
/* read a block from wishbone */
533 
int dbg_wb_read_block16(unsigned long adr, unsigned short *data, int len) {
534 
  int i, err;
535 
  //printf("%08x %08x\n", adr, len);
536 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
537 
  if ((err = dbg_command(0x5, adr, len))) return err;
538 
  if ((err = dbg_go((unsigned char*)data, len, 1))) return err;
539 
  for (i = 0; i < len / 2; i ++) data[i] = ntohs(data[i]);
540 
  //printf("%08x\n", err);
541 
  return DBG_ERR_OK;
542 
}
543 
 
544 
/* read a block from wishbone */
545 
int dbg_wb_read_block8(unsigned long adr, unsigned char *data, int len) {
546 
  int i, err;
547 
  //printf("%08x %08x\n", adr, len);
548 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
549 
  if ((err = dbg_command(0x4, adr, len))) return err;
550 
  if ((err = dbg_go((unsigned char*)data, len, 1))) return err;
551 
  //printf("%08x\n", err);
552 
  return DBG_ERR_OK;
553 
}
554 
 
555 
/* write a block to wishbone */
556 
int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len) {
557 
  int i, err;
558 
  for (i = 0; i < len / 4; i ++) data[i] = ntohl(data[i]);
559 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
560 
  if ((err = dbg_command(0x2, adr, len))) return err;
561 
  if ((err = dbg_go((unsigned char*)data, len, 0))) return err;
562 
  return DBG_ERR_OK;
563 
}
564 
 
565 
/* write a block to wishbone */
566 
int dbg_wb_write_block16(unsigned long adr, unsigned short *data, int len) {
567 
  int i, err;
568 
  for (i = 0; i < len / 2; i ++) data[i] = ntohs(data[i]);
569 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
570 
  if ((err = dbg_command(0x1, adr, len))) return err;
571 
  if ((err = dbg_go((unsigned char*)data, len, 0))) return err;
572 
  return DBG_ERR_OK;
573 
}
574 
 
575 
/* write a block to wishbone */
576 
int dbg_wb_write_block8(unsigned long adr, unsigned char *data, int len) {
577 
  int i, err;
578 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
579 
  if ((err = dbg_command(0x0, adr, len))) return err;
580 
  if ((err = dbg_go((unsigned char*)data, len, 0))) return err;
581 
  return DBG_ERR_OK;
582 
}
583 
 
584 
/* read a register from cpu */
585 
int dbg_cpu0_read(unsigned long adr, unsigned long *data) {
586 
  int err;
587 
  if ((err = dbg_set_chain(DC_CPU0))) return err;
588 
  if ((err = dbg_command(0x6, adr, 4))) return err;
589 
  if ((err = dbg_go((unsigned char*)data, 4, 1))) return err;
590 
  *data = ntohl(*data);
591 
  return DBG_ERR_OK;
592 
}
593 
 
594 
/* write a cpu register */
595 
int dbg_cpu0_write(unsigned long adr, unsigned long data) {
596 
  int err;
597 
  data = ntohl(data);
598 
  if ((err = dbg_set_chain(DC_CPU0))) return err;
599 
  if ((err = dbg_command(0x2, adr, 4))) return err;
600 
  if ((err = dbg_go((unsigned char*)&data, 4, 0))) return err;
601 
  return DBG_ERR_OK;
602 
}
603 
 
604 
/* read a register from cpu */
605 
int dbg_cpu1_read(unsigned long adr, unsigned long *data) {
606 
  int err;
607 
  if ((err = dbg_set_chain(DC_CPU1))) return err;
608 
  if ((err = dbg_command(0x6, adr, 4))) return err;
609 
  if ((err = dbg_go((unsigned char*)data, 4, 1))) return err;
610 
  *data = ntohl(*data);
611 
  return DBG_ERR_OK;
612 
}
613 
 
614 
/* write a cpu register */
615 
int dbg_cpu1_write(unsigned long adr, unsigned long data) {
616 
  int err;
617 
  data = ntohl(data);
618 
  if ((err = dbg_set_chain(DC_CPU1))) return err;
619 
  if ((err = dbg_command(0x2, adr, 4))) return err;
620 
  if ((err = dbg_go((unsigned char*)&data, 4, 0))) return err;
621 
  return DBG_ERR_OK;
622 
}
623 
 
624 
/* write a cpu module register */
625 
int dbg_cpu1_write_reg(unsigned long adr, unsigned char data) {
626 
  int err;
627 
  if ((err = dbg_set_chain(DC_CPU1))) return err;
628 
  if ((err = dbg_ctrl(data & 2, data &1))) return err;
629 
  return DBG_ERR_OK;
630 
}
631 
 
632 
/* read a register from cpu module */
633 
int dbg_cpu1_read_ctrl(unsigned long adr, unsigned char *data) {
634 
  int err;
635 
  int r, s;
636 
  if ((err = dbg_set_chain(DC_CPU1))) return err;
637 
  if ((err = dbg_ctrl_read(&r, &s))) return err;
638 
  *data = (r << 1) | s;
639 
  return DBG_ERR_OK;
640 
}
641 
 
642 
/* write a cpu module register */
643 
int dbg_cpu0_write_ctrl(unsigned long adr, unsigned char data) {
644 
  int err;
645 
  if ((err = dbg_set_chain(DC_CPU0))) return err;
646 
  if ((err = dbg_ctrl(data & 2, data &1))) return err;
647 
  return DBG_ERR_OK;
648 
}
649 
 
650 
/* read a register from cpu module */
651 
int dbg_cpu0_read_ctrl(unsigned long adr, unsigned char *data) {
652 
  int err;
653 
  int r, s;
654 
  if ((err = dbg_set_chain(DC_CPU0))) return err;
655 
  if ((err = dbg_ctrl_read(&r, &s))) return err;
656 
  *data = (r << 1) | s;
657 
  return DBG_ERR_OK;
658 
}
659 
 
660 
void check(char *fn, int l, int i) {
661 
  if (i != DBG_ERR_OK) {
662 
    fprintf(stderr, "%s:%d: Jtag error %d occured; exiting.\n", fn, l, i);
663 
    exit(1);
664 
  }
665 
}
666 
 
667 
 
668 
void test_sdram (void) {
669 
  unsigned long insn;
670 
  unsigned long i;
671 
  unsigned long data4_out[0x08];
672 
  unsigned long data4_in[0x08];
673 
  unsigned short data2_out[0x10];
674 
  unsigned short data2_in[0x10];
675 
  unsigned char data1_out[0x20];
676 
  unsigned char data1_in[0x20];
677 
 
678 
  printf("Start SDRAM WR\n");
679 
  for (i=0x10; i<(SDRAM_SIZE+SDRAM_BASE); i=i<<1) {
680 
    //printf("0x%x: 0x%x\n", SDRAM_BASE+i, i);
681 
    CHECK(dbg_wb_write32(SDRAM_BASE+i, i));
682 
  }
683 
 
684 
  printf("Start SDRAM RD\n");
685 
  for (i=0x10; i<(SDRAM_SIZE+SDRAM_BASE); i=i<<1) {
686 
    CHECK(dbg_wb_read32(SDRAM_BASE+i, &insn));
687 
    //printf("0x%x: 0x%x\n", SDRAM_BASE+i, insn);
688 
    if (i != insn) {
689 
      printf("SDRAM not OK");
690 
      exit (1);
691 
    }
692 
  }
693 
 
694 
  printf("32-bit block write from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
695 
  for (i=0; i<(0x20/4); i++) {
696 
    data4_out[i] = data4_in[i] = ((4*i+3)<<24) | ((4*i+2)<<16) | ((4*i+1)<<8) | (4*i);
697 
    //printf("data_out = %0x\n", data4_out[i]);
698 
  }
699 
 
700 
  //printf("Press a key for write\n"); getchar();
701 
  CHECK(dbg_wb_write_block32(SDRAM_BASE, &data4_out[0], 0x20));
702 
 
703 
  // 32-bit block read is used for checking
704 
  printf("32-bit block read from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
705 
  CHECK(dbg_wb_read_block32(SDRAM_BASE, &data4_out[0], 0x20));
706 
  for (i=0; i<(0x20/4); i++) {
707 
    //printf("0x%x: 0x%x\n", SDRAM_BASE+(i*4), data_out[i]);
708 
    if (data4_in[i] != data4_out[i]) {
709 
      printf("SDRAM data differs. Expected: 0x%0x, read: 0x%0x\n", data4_in[i], data4_out[i]);
710 
      exit(1);
711 
    }
712 
  }
713 
 
714 
  printf("16-bit block write from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
715 
  for (i=0; i<(0x20/2); i++) {
716 
    data2_out[i] = data2_in[i] = ((4*i+1)<<8) | (4*i);
717 
    //printf("data_out = %0x\n", data_out[i]);
718 
  }
719 
  CHECK(dbg_wb_write_block16(SDRAM_BASE, &data2_out[0], 0x20));
720 
 
721 
  // 16-bit block read is used for checking
722 
  printf("16-bit block read from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
723 
  CHECK(dbg_wb_read_block16(SDRAM_BASE, &data2_out[0], 0x20));
724 
  for (i=0; i<(0x20/2); i++) {
725 
    //printf("0x%x: 0x%x\n", SDRAM_BASE+(i*4), data_out[i]);
726 
    if (data2_in[i] != data2_out[i]) {
727 
      printf("SDRAM data differs. Expected: 0x%0x, read: 0x%0x\n", data2_in[i], data2_out[i]);
728 
      exit(1);
729 
    }
730 
  }
731 
 
732 
  printf("8-bit block write from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
733 
  for (i=0; i<(0x20/1); i++) {
734 
    data1_out[i] = data1_in[i] = (4*i);
735 
    //printf("data_out = %0x\n", data_out[i]);
736 
  }
737 
  CHECK(dbg_wb_write_block8(SDRAM_BASE, &data1_out[0], 0x20));
738 
 
739 
  // 32-bit block read is used for checking
740 
  printf("8-bit block read from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
741 
  CHECK(dbg_wb_read_block8(SDRAM_BASE, &data1_out[0], 0x20));
742 
  for (i=0; i<(0x20/1); i++) {
743 
    //printf("0x%x: 0x%x\n", SDRAM_BASE+(i*4), data_out[i]);
744 
    if (data1_in[i] != data1_out[i]) {
745 
      printf("SDRAM data differs. Expected: 0x%0x, read: 0x%0x\n", data1_in[i], data1_out[i]);
746 
      exit(1);
747 
    }
748 
  }
749 
}
750 
 
751 
 
752 
void dbg_test() {
753 
  int i;
754 
  unsigned long npc, ppc, r1, insn, result;
755 
  unsigned char stalled;
756 
#if 1
757 
#define MC_BASE_ADDR     0x93000000
758 
#define FLASH_BASE_ADDR  0xf0000000
759 
#define FLASH_BAR_VAL    FLASH_BASE_ADDR
760 
#define FLASH_AMR_VAL    0xf0000000
761 
#define FLASH_WTR_VAL    0x00011009
762 
#define FLASH_RTR_VAL    0x01002009
763 
#define SDRAM_BASE_ADDR  0x00000000
764 
#define SDRAM_BAR_VAL    SDRAM_BASE_ADDR
765 
//#define SDRAM_SIZE       0x04000000  defined at the start of this program
766 
#define SDRAM_AMR_VAL    (~(SDRAM_SIZE -1))
767 
#define SDRAM_RATR_VAL   0x00000006
768 
#define SDRAM_RCDR_VAL   0x00000002
769 
#define SDRAM_RCTR_VAL   0x00000006
770 
#define SDRAM_REFCTR_VAL 0x00000006
771 
#define SDRAM_PTR_VAL    0x00000001
772 
#define SDRAM_RRDR_VAL   0x00000000
773 
#define SDRAM_RIR_VAL    0x000000C0
774 
 
775 
#define MC_BAR_0         0x00
776 
#define MC_AMR_0         0x04
777 
#define MC_WTR_0         0x30
778 
#define MC_RTR_0         0x34
779 
#define MC_OSR           0xe8
780 
#define MC_BAR_1         0x08
781 
#define MC_BAR_4         0x80
782 
#define MC_AMR_1         0x0c
783 
#define MC_AMR_4         0x84
784 
#define MC_CCR_1         0x24
785 
#define MC_CCR_4         0xa0
786 
#define MC_RATR          0xb0
787 
#define MC_RCDR          0xc8
788 
#define MC_RCTR          0xb4
789 
#define MC_REFCTR        0xc4
790 
#define MC_PTR           0xbc
791 
#define MC_RRDR          0xb8
792 
#define MC_RIR           0xcc
793 
#define MC_ORR           0xe4
794 
 
795 
  //usleep(1000000);
796 
 
797 
  printf("Stall 8051\n");
798 
  CHECK(dbg_cpu1_write_reg(0, 0x01)); // stall 8051
799 
 
800 
  printf("Stall or1k\n");
801 
  CHECK(dbg_cpu0_write_ctrl(0, 0x01));      // stall or1k
802 
 
803 
  CHECK(dbg_cpu1_read_ctrl(0, &stalled));
804 
  if (!(stalled & 0x1)) {
805 
    printf("8051 should be stalled\n");   // check stall 8051
806 
    exit(1);
807 
  }
808 
 
809 
  CHECK(dbg_cpu0_read_ctrl(0, &stalled));
810 
  if (!(stalled & 0x1)) {
811 
    printf("or1k should be stalled\n");   // check stall or1k
812 
    exit(1);
813 
  }
814 
 
815 
  printf("Initialize Memory Controller\n");
816 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_0, FLASH_BAR_VAL & 0xffff0000));
817 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_0, FLASH_AMR_VAL & 0xffff0000));
818 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_WTR_0, FLASH_WTR_VAL));
819 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RTR_0, FLASH_RTR_VAL));
820 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x40000000));
821 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_4, SDRAM_BAR_VAL & 0xffff0000));
822 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_4, SDRAM_AMR_VAL & 0xffff0000));
823 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_4, 0x00bf0005));
824 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RATR, SDRAM_RATR_VAL));
825 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RCDR, SDRAM_RCDR_VAL));
826 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RCTR, SDRAM_RCTR_VAL));
827 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_REFCTR, SDRAM_REFCTR_VAL));
828 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_PTR, SDRAM_PTR_VAL));
829 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RRDR, SDRAM_RRDR_VAL));
830 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RIR, SDRAM_RIR_VAL));
831 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x5e000000));
832 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x5e000000));
833 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x6e000000));
834 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
835 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
836 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
837 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
838 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
839 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
840 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
841 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
842 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x7e000033));
843 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x7e000033));
844 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_4, 0xc0bf0005));
845 
 
846 
  CHECK(dbg_wb_read32(MC_BASE_ADDR+MC_CCR_4, &insn));
847 
  printf("expected %x, read %x\n", 0xc0bf0005, insn);
848 
 
849 
  // SRAM initialized to 0x40000000
850 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_1, SRAM_BASE & 0xffff0000));
851 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_1, ~(SRAM_SIZE - 1) & 0xffff0000));
852 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_1, 0xc020001f));
853 
#endif
854 
 
855 
#if 1
856 
#define CPU_OP_ADR  0
857 
#define CPU_SEL_ADR 1
858 
 
859 
  /* unstall the or1200 in highland_sys */
860 
  printf("Unstall or1k\n");
861 
  CHECK(dbg_wb_write32(0xb8070000, 2));
862 
 
863 
  CHECK(dbg_cpu1_read_ctrl(0, &stalled));
864 
  if (!(stalled & 0x1)) {
865 
    printf("8051 should be stalled\n");   // check stall 8051
866 
    exit(1);
867 
  }
868 
 
869 
  printf("Stall or1k\n");
870 
  CHECK(dbg_cpu0_write_ctrl(0, 0x01));         // stall or1k
871 
 
872 
  printf("SDRAM test: \n");
873 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x00, 0x12345678));
874 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x00, &insn));
875 
  printf("expected %x, read %x\n", 0x12345678, insn);
876 
  if (insn != 0x12345678) exit(1);
877 
 
878 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0000, 0x11112222));
879 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0000, &insn));
880 
  printf("expected %x, read %x\n", 0x11112222, insn);
881 
  if (insn != 0x11112222) exit(1);
882 
 
883 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0004, 0x33334444));
884 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0008, 0x55556666));
885 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x000c, 0x77778888));
886 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0010, 0x9999aaaa));
887 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0014, 0xbbbbcccc));
888 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0018, 0xddddeeee));
889 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x001c, 0xffff0000));
890 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0020, 0xdeadbeef));
891 
 
892 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0000, &insn));
893 
  printf("expected %x, read %x\n", 0x11112222, insn);
894 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0004, &insn));
895 
  printf("expected %x, read %x\n", 0x33334444, insn);
896 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0008, &insn));
897 
  printf("expected %x, read %x\n", 0x55556666, insn);
898 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x000c, &insn));
899 
  printf("expected %x, read %x\n", 0x77778888, insn);
900 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0010, &insn));
901 
  printf("expected %x, read %x\n", 0x9999aaaa, insn);
902 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0014, &insn));
903 
  printf("expected %x, read %x\n", 0xbbbbcccc, insn);
904 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0018, &insn));
905 
  printf("expected %x, read %x\n", 0xddddeeee, insn);
906 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x001c, &insn));
907 
  printf("expected %x, read %x\n", 0xffff0000, insn);
908 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0020, &insn));
909 
  printf("expected %x, read %x\n", 0xdeadbeef, insn);
910 
 
911 
  if (insn != 0xdeadbeef) {
912 
    printf("SDRAM test failed !!!\n");
913 
    exit(1);
914 
  }
915 
    else
916 
    printf("SDRAM test passed\n");
917 
 
918 
  printf("SRAM test: \n");
919 
  CHECK(dbg_wb_write32(SRAM_BASE+0x0000, 0x11112222));
920 
  CHECK(dbg_wb_write32(SRAM_BASE+0x0004, 0x33334444));
921 
  CHECK(dbg_wb_write32(SRAM_BASE+0x0008, 0x55556666));
922 
  CHECK(dbg_wb_write32(SRAM_BASE+0x000c, 0x77778888));
923 
  CHECK(dbg_wb_write32(SRAM_BASE+0x0010, 0x9999aaaa));
924 
  CHECK(dbg_wb_write32(SRAM_BASE+0x0014, 0xbbbbcccc));
925 
  CHECK(dbg_wb_write32(SRAM_BASE+0x0018, 0xddddeeee));
926 
  CHECK(dbg_wb_write32(SRAM_BASE+0x001c, 0xffff0000));
927 
  CHECK(dbg_wb_write32(SRAM_BASE+0x0020, 0xdedababa));
928 
 
929 
  CHECK(dbg_wb_read32(SRAM_BASE+0x0000, &insn));
930 
  printf("expected %x, read %x\n", 0x11112222, insn);
931 
  CHECK(dbg_wb_read32(SRAM_BASE+0x0004, &insn));
932 
  printf("expected %x, read %x\n", 0x33334444, insn);
933 
  CHECK(dbg_wb_read32(SRAM_BASE+0x0008, &insn));
934 
  printf("expected %x, read %x\n", 0x55556666, insn);
935 
  CHECK(dbg_wb_read32(SRAM_BASE+0x000c, &insn));
936 
  printf("expected %x, read %x\n", 0x77778888, insn);
937 
  CHECK(dbg_wb_read32(SRAM_BASE+0x0010, &insn));
938 
  printf("expected %x, read %x\n", 0x9999aaaa, insn);
939 
  CHECK(dbg_wb_read32(SRAM_BASE+0x0014, &insn));
940 
  printf("expected %x, read %x\n", 0xbbbbcccc, insn);
941 
  CHECK(dbg_wb_read32(SRAM_BASE+0x0018, &insn));
942 
  printf("expected %x, read %x\n", 0xddddeeee, insn);
943 
  CHECK(dbg_wb_read32(SRAM_BASE+0x001c, &insn));
944 
  printf("expected %x, read %x\n", 0xffff0000, insn);
945 
  CHECK(dbg_wb_read32(SRAM_BASE+0x0020, &insn));
946 
  printf("expected %x, read %x\n", 0xdedababa, insn);
947 
 
948 
  if (insn != 0xdedababa) {
949 
    printf("SRAN test failed!!!\n");
950 
    exit(1);
951 
  }
952 
    else
953 
    printf("SRAM test passed\n");
954 
 
955 
  #if 1
956 
    test_sdram();
957 
  #endif
958 
 
959 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x00, 0xe0000005));   /* l.xor   r0,r0,r0   */
960 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x04, 0x9c200000));   /* l.addi  r1,r0,0x0  */
961 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x08, 0x18400000));   /* l.movhi r2,0x4000  */
962 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0c, 0xa8420030));   /* l.ori   r2,r2,0x30 */
963 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x10, 0x9c210001));   /* l.addi  r1,r1,1    */
964 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x14, 0x9c210001));   /* l.addi  r1,r1,1    */
965 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x18, 0xd4020800));   /* l.sw    0(r2),r1   */
966 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x1c, 0x9c210001));   /* l.addi  r1,r1,1    */
967 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x20, 0x84620000));   /* l.lwz   r3,0(r2)   */
968 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x24, 0x03fffffb));   /* l.j     loop2      */
969 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x28, 0xe0211800));   /* l.add   r1,r1,r3   */
970 
 
971 
  CHECK(dbg_cpu0_write((0 << 11) + 17, 0x01));  /* Enable exceptions */
972 
  CHECK(dbg_cpu0_write((6 << 11) + 20, 0x2000));  /* Trap causes stall */
973 
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE));  /* Set PC */
974 
  CHECK(dbg_cpu0_write((6 << 11) + 16, 1 << 22));  /* Set step bit */
975 
  for(i = 0; i < 11; i++) {
976 
    CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* 11x Unstall */
977 
    do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
978 
  }
979 
 
980 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
981 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
982 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
983 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
984 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000010, 0x00000028, 5);
985 
  result = npc + ppc + r1;
986 
 
987 
  CHECK(dbg_cpu0_write((6 << 11) + 16, 0));  /* Reset step bit */
988 
  CHECK(dbg_wb_read32(SDRAM_BASE + 0x28, &insn));  /* Set trap insn in delay slot */
989 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x28, 0x21000001));
990 
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
991 
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
992 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
993 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
994 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
995 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x28, insn));  /* Set back original insn */
996 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
997 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000010, 0x00000028, 8);
998 
  result = npc + ppc + r1 + result;
999 
 
1000 
  CHECK(dbg_wb_read32(SDRAM_BASE + 0x24, &insn));  /* Set trap insn in place of branch insn */
1001 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x24, 0x21000001));
1002 
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x10));  /* Set PC */
1003 
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
1004 
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
1005 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
1006 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
1007 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
1008 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x24, insn));  /* Set back original insn */
1009 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
1010 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000028, 0x00000024, 11);
1011 
  result = npc + ppc + r1 + result;
1012 
 
1013 
  CHECK(dbg_wb_read32(SDRAM_BASE + 0x20, &insn));  /* Set trap insn before branch insn */
1014 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, 0x21000001));
1015 
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x24));  /* Set PC */
1016 
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
1017 
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
1018 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
1019 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
1020 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
1021 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, insn));  /* Set back original insn */
1022 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
1023 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000024, 0x00000020, 24);
1024 
  result = npc + ppc + r1 + result;
1025 
 
1026 
  CHECK(dbg_wb_read32(SDRAM_BASE + 0x1c, &insn));  /* Set trap insn behind lsu insn */
1027 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x1c, 0x21000001));
1028 
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x20));  /* Set PC */
1029 
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
1030 
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
1031 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
1032 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
1033 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
1034 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x1c, insn));  /* Set back original insn */
1035 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
1036 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000020, 0x0000001c, 49);
1037 
  result = npc + ppc + r1 + result;
1038 
 
1039 
  CHECK(dbg_wb_read32(SDRAM_BASE + 0x20, &insn));  /* Set trap insn very near previous one */
1040 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, 0x21000001));
1041 
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x1c));  /* Set PC */
1042 
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
1043 
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
1044 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
1045 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
1046 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
1047 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, insn));  /* Set back original insn */
1048 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
1049 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000024, 0x00000020, 50);
1050 
  result = npc + ppc + r1 + result;
1051 
 
1052 
  CHECK(dbg_wb_read32(SDRAM_BASE + 0x10, &insn));  /* Set trap insn to the start */
1053 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x10, 0x21000001));
1054 
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x20)  /* Set PC */);
1055 
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
1056 
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
1057 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
1058 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
1059 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
1060 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x10, insn));  /* Set back original insn */
1061 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
1062 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000014, 0x00000010, 99);
1063 
  result = npc + ppc + r1 + result;
1064 
 
1065 
  CHECK(dbg_cpu0_write((6 << 11) + 16, 1 << 22));  /* Set step bit */
1066 
  for(i = 0; i < 5; i++) {
1067 
    CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
1068 
    do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
1069 
  }
1070 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
1071 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
1072 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
1073 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
1074 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000028, 0x00000024, 101);
1075 
  result = npc + ppc + r1 + result;
1076 
 
1077 
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x24));  /* Set PC */
1078 
  for(i = 0; i < 2; i++) {
1079 
    CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
1080 
    do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
1081 
  }
1082 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
1083 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
1084 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
1085 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
1086 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000010, 0x00000028, 201);
1087 
  result = npc + ppc + r1 + result;
1088 
  printf("result = %.8lx\n", result ^ 0xdeaddae1);
1089 
 
1090 
 
1091 
  { // 8051 TEST
1092 
    unsigned long npc[3], tmp;
1093 
 
1094 
    // WRITE ACC
1095 
    CHECK(dbg_cpu1_write(0x20e0, 0xa6));
1096 
 
1097 
    // READ ACC
1098 
    CHECK(dbg_cpu1_read(0x20e0, &tmp));   // select SFR space
1099 
    printf("Read  8051   ACC = %0x (expected a6)\n", tmp);
1100 
    result = result + tmp;
1101 
 
1102 
    // set exception to single step to jump over a loop
1103 
    CHECK(dbg_cpu1_write(0x3010, 0xa0)); // set single step and global enable in EER
1104 
    CHECK(dbg_cpu1_write(0x3011, 0x40)); // set evec = 24'h000040
1105 
    CHECK(dbg_cpu1_write(0x3012, 0x00)); // (already reset value)
1106 
    CHECK(dbg_cpu1_write(0x3013, 0x00)); // (already reset value)
1107 
 
1108 
    // set HW breakpoint at PC == 0x41
1109 
    CHECK(dbg_cpu1_write(0x3020, 0x41)); // DVR0 = 24'h000041
1110 
    CHECK(dbg_cpu1_write(0x3023, 0x39)); // DCR0 = valid, == PC
1111 
    CHECK(dbg_cpu1_write(0x3001, 0x04)); // DSR = watchpoint
1112 
 
1113 
    // flush 8051 instruction cache
1114 
    CHECK(dbg_cpu1_write(0x209f, 0x00));
1115 
 
1116 
    // Put some instructions in ram (8-bit mode on wishbone)
1117 
    CHECK(dbg_wb_write8 (0x40, 0x04));  // inc a
1118 
    CHECK(dbg_wb_write8 (0x41, 0x03));  // rr a;
1119 
    CHECK(dbg_wb_write8 (0x42, 0x14));  // dec a;
1120 
    CHECK(dbg_wb_write8 (0x43, 0xf5));  // mov 0e5h, a;
1121 
    CHECK(dbg_wb_write8 (0x44, 0xe5));
1122 
 
1123 
    // unstall just 8051
1124 
    CHECK(dbg_cpu1_write_reg(0, 0));
1125 
 
1126 
    // read PC
1127 
    CHECK(dbg_cpu1_read(0, &npc[0]));
1128 
    CHECK(dbg_cpu1_read(1, &npc[1]));
1129 
    CHECK(dbg_cpu1_read(2, &npc[2]));
1130 
    printf("Read  8051   npc = %02x%02x%02x (expected 41)\n", npc[2], npc[1], npc[0]);
1131 
    result = result + (npc[2] << 16) + (npc[1] << 8) + npc[0];
1132 
 
1133 
    // READ ACC
1134 
    CHECK(dbg_cpu1_read(0x20e0, &tmp));   // select SFR space
1135 
    printf("Read  8051   ACC = %0x (expected a7)\n", tmp);
1136 
    result = result + tmp;
1137 
 
1138 
    // set sigle step to stop execution
1139 
    CHECK(dbg_cpu1_write(0x3001, 0x20)); // set single step and global enable in DSR
1140 
 
1141 
    // clear DRR
1142 
    CHECK(dbg_cpu1_write(0x3000, 0x00)); // set single step and global enable in DRR
1143 
 
1144 
    // unstall just 8051
1145 
    CHECK(dbg_cpu1_write_reg(0, 0));
1146 
 
1147 
    // read PC
1148 
    CHECK(dbg_cpu1_read(0, &npc[0]));
1149 
    CHECK(dbg_cpu1_read(1, &npc[1]));
1150 
    CHECK(dbg_cpu1_read(2, &npc[2]));
1151 
    printf("Read  8051   npc = %02x%02x%02x (expected 42)\n", npc[2], npc[1], npc[0]);
1152 
    result = result + (npc[2] << 16) + (npc[1] << 8) + npc[0];
1153 
 
1154 
    // READ ACC
1155 
    CHECK(dbg_cpu1_read(0x20e0, &tmp));   // select SFR space
1156 
    printf("Read  8051   ACC = %0x (expected d3)\n", tmp);
1157 
    result = result + tmp;
1158 
 
1159 
    printf("report (%x)\n", result ^ 0x6c1 ^ 0xdeaddead);
1160 
  }
1161 
#endif
1162 
}
1163 
 
1164 
int main(int argc,  char *argv[]) {
1165 
  char *redirstr;
1166 
  int trace_fd = 0;
1167 
  char *s;
1168 
  int err = DBG_ERR_OK;
1169 
 
1170 
  int c;
1171 
  const char *args;
1172 
  char *port;
1173 
  char *cable;
1174 
 
1175 
  srand(getpid());
1176 
  if ((argc < 3) || (argv[1][0] == '-') || (argv[2][0] == '-')) {
1177 
    printf("JTAG protocol via parallel port for linux.\n");
1178 
    printf("Copyright (C) 2001 Marko Mlinar, markom@opencores.org\n\n");
1179 
    printf("Usage: %s [cable] [JTAG port_number]\n", argv[0]);
1180 
    jp_print_cable_help();
1181 
    return -1;
1182 
  }
1183 
 
1184 
  cable = argv[1];
1185 
  port = argv[2];
1186 
 
1187 
  if (!jp_select_cable(cable)) {
1188 
    fprintf(stderr,"Error selecting cable %s\n", cable);
1189 
    return -1;
1190 
  }
1191 
 
1192 
  /* Get the cable-arguments */
1193 
  args = jp_get_cable_args();
1194 
 
1195 
  /* Parse the cable arguments (if-any) */
1196 
  for(;;) {
1197 
    c = getopt(argc, argv, args);
1198 
    if(c == -1)
1199 
      break;
1200 
    if(c == '?')
1201 
      return 1;
1202 
    if(!jp_cable_opt(c, optarg))
1203 
      return 1;
1204 
  }
1205 
  if(!jp_init_cable())
1206 
    return 1;
1207 
 
1208 
  /* Initialize a new connection to the or1k board, and make sure we are
1209 
     really connected.  */
1210 
  current_chain = -1;
1211 
  if ((err = dbg_reset())) goto error;
1212 
 
1213 
  /* Test the connection.  */
1214 
  /*dbg_test();*/
1215 
 
1216 
  /* We have a connection.  Establish server.  */
1217 
  serverPort = strtol(port,&s,10);
1218 
  if(*s) return -1;
1219 
 
1220 
  if(server_fd = GetServerSocket("or1ksim","tcp", serverPort)) {
1221 
    printf("JTAG Proxy server started on port %d\n", serverPort);
1222 
    printf("Press CTRL+c to exit.\n");
1223 
  } else {
1224 
    fprintf(stderr,"Cannot start JTAG Proxy server on port %d\n", serverPort);
1225 
    exit(-1);
1226 
  }
1227 
 
1228 
  /* Do endless loop of checking and handle GDB requests.  Ctrl-c exits.  */
1229 
  HandleServerSocket(true);
1230 
  return 0;
1231 
error:
1232 
  fprintf(stderr,"Connection with jtag via parallel port failed (err = %d).\n", err);
1233 
  exit(-1);
1234 
}
1235 
 

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