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1622 |
jcastillo |
/*
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* bios32.c - PCI BIOS functions for Alpha systems not using BIOS
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* emulation code.
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*
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* Written by Dave Rusling (david.rusling@reo.mts.dec.com)
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*
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* Adapted to 64-bit kernel and then rewritten by David Mosberger
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* (davidm@cs.arizona.edu)
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*
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* For more information, please consult
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*
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* PCI BIOS Specification Revision
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* PCI Local Bus Specification
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* PCI System Design Guide
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*
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* PCI Special Interest Group
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* M/S HF3-15A
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* 5200 N.E. Elam Young Parkway
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* Hillsboro, Oregon 97124-6497
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* +1 (503) 696-2000
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* +1 (800) 433-5177
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*
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* Manuals are $25 each or $50 for all three, plus $7 shipping
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* within the United States, $35 abroad.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#if 0
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# define DBG_DEVS(args) printk args
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#else
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# define DBG_DEVS(args)
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#endif
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#ifndef CONFIG_PCI
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int pcibios_present(void)
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{
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return 0;
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}
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asmlinkage int sys_pciconfig_read()
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{
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return 0;
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}
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asmlinkage int sys_pciconfig_write()
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{
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return 0;
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}
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#else /* CONFIG_PCI */
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#include <linux/bios32.h>
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#include <linux/pci.h>
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#include <linux/malloc.h>
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#include <linux/mm.h>
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#include <asm/hwrpb.h>
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#include <asm/io.h>
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#include <asm/segment.h>
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#include <asm/dma.h>
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#define KB 1024
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#define MB (1024*KB)
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#define GB (1024*MB)
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#define MAJOR_REV 0
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#define MINOR_REV 3
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/*
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* Align VAL to ALIGN, which must be a power of two.
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*/
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#define ALIGN(val,align) (((val) + ((align) - 1)) & ~((align) - 1))
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/*
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* PCI_MODIFY
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*
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* Temporary internal macro. If this 0, then do not write to any of
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* the PCI registers, merely read them (i.e., use configuration as
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* determined by SRM). The SRM seem do be doing a less than perfect
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* job in configuring PCI devices, so for now we do it ourselves.
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* Reconfiguring PCI devices breaks console (RPB) callbacks, but
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* those don't work properly with 64 bit addresses anyways.
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*
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* The accepted convention seems to be that the console (POST
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* software) should fully configure boot devices and configure the
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* interrupt routing of *all* devices. In particular, the base
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* addresses of non-boot devices need not be initialized. For
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* example, on the AXPpci33 board, the base address a #9 GXE PCI
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* graphics card reads as zero (this may, however, be due to a bug in
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* the graphics card---there have been some rumor that the #9 BIOS
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* incorrectly resets that address to 0...).
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*/
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#ifdef CONFIG_ALPHA_SRM_SETUP
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#define PCI_MODIFY 0
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static struct pci_dev *irq_dev_to_reset[16];
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static unsigned char irq_to_reset[16];
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static int irq_reset_count = 0;
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static struct pci_dev *io_dev_to_reset[16];
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static unsigned char io_reg_to_reset[16];
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static unsigned int io_to_reset[16];
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static int io_reset_count = 0;
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#else /* SRM_SETUP */
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#define PCI_MODIFY 1
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#endif /* SRM_SETUP */
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extern struct hwrpb_struct *hwrpb;
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#if PCI_MODIFY
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/* NOTE: we can't just blindly use 64K for machines with EISA busses; they
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may also have PCI-PCI bridges present, and then we'd configure the bridge
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incorrectly */
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/* NOTE also that we may need this stuff for SRM_SETUP also, since certain
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SRM consoles screw up and allocate I/O space addresses > 64K behind
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PCI-to_PCI bridges, which can't pass addresses larger than 64K... */
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#if defined(CONFIG_ALPHA_EISA)
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static unsigned int io_base = 0x9000; /* start above 8th slot */
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#else
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static unsigned int io_base = 0x8000;
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#endif
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#if defined(CONFIG_ALPHA_XL)
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/*
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An XL is AVANTI (APECS) family, *but* it has only 27 bits of ISA address
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that get passed through the PCI<->ISA bridge chip. Although this causes
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us to set the PCI->Mem window bases lower than normal, we still allocate
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PCI bus devices' memory addresses *below* the low DMA mapping window,
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and hope they fit below 64Mb (to avoid conflicts), and so that they can
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be accessed via SPARSE space.
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We accept the risk that a broken Myrinet card will be put into a true XL
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and thus can more easily run into the problem described below.
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*/
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static unsigned int mem_base = 16*MB + 2*MB; /* 16M to 64M-1 is avail */
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#elif defined(CONFIG_ALPHA_LCA) || defined(CONFIG_ALPHA_APECS)
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/*
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We try to make this address *always* have more than 1 bit set.
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this is so that devices like the broken Myrinet card will always have
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a PCI memory address that will never match a IDSEL address in
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PCI Config space, which can cause problems with early rev cards.
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However, APECS and LCA have only 34 bits for physical addresses, thus
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limiting PCI bus memory addresses for SPARSE access to be less than 128Mb.
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*/
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static unsigned int mem_base = 64*MB + 2*MB;
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#else
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/*
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We try to make this address *always* have more than 1 bit set.
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this is so that devices like the broken Myrinet card will always have
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a PCI memory address that will never match a IDSEL address in
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PCI Config space, which can cause problems with early rev cards.
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Because CIA and PYXIS and T2 have more bits for physical addresses,
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they support an expanded range of SPARSE memory addresses.
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*/
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static unsigned int mem_base = 128*MB + 16*MB;
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#endif /* CONFIG_ALPHA_XL */
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/*
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* Disable PCI device DEV so that it does not respond to I/O or memory
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* accesses.
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*/
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static void disable_dev(struct pci_dev *dev)
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{
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struct pci_bus *bus;
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unsigned short cmd;
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#if defined(CONFIG_ALPHA_EISA)
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/*
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* HACK: the PCI-to-EISA bridge does not seem to identify
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* itself as a bridge... :-(
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*/
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if (dev->vendor == 0x8086 && dev->device == 0x0482) {
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DBG_DEVS(("disable_dev: ignoring PCEB...\n"));
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return;
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}
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#endif
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/*
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* we don't have code that will init the CYPRESS bridge correctly
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* so we do the next best thing, and depend on the previous
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* console code to do the right thing, and ignore it here... :-\
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*/
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if ((dev->vendor == 0x1080) && (dev->device == 0xC693)) {
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#if 0
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printk("disable_dev: ignoring CYPRESS bridge...\n");
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#endif
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return;
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}
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bus = dev->bus;
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pcibios_read_config_word(bus->number, dev->devfn, PCI_COMMAND, &cmd);
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/* hack, turn it off first... */
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cmd &= (~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY & ~PCI_COMMAND_MASTER);
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pcibios_write_config_word(bus->number, dev->devfn, PCI_COMMAND, cmd);
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}
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/*
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* Layout memory and I/O for a device:
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*/
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#define MAX(val1, val2) ( ((val1) > (val2)) ? val1 : val2)
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static void layout_dev(struct pci_dev *dev)
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{
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struct pci_bus *bus;
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unsigned short cmd;
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unsigned int base, mask, size, reg;
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unsigned int alignto;
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#if defined(CONFIG_ALPHA_EISA)
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/*
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* HACK: the PCI-to-EISA bridge does not seem to identify
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* itself as a bridge... :-(
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*/
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if (dev->vendor == 0x8086 && dev->device == 0x0482) {
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DBG_DEVS(("layout_dev: ignoring PCEB...\n"));
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return;
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}
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#endif
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/*
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* we don't have code that will init the CYPRESS bridge correctly
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* so we do the next best thing, and depend on the previous
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* console code to do the right thing, and ignore it here... :-\
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*/
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if ((dev->vendor == 0x1080) && (dev->device == 0xC693)) {
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#if 0
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printk("layout_dev: ignoring CYPRESS bridge...\n");
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#endif
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return;
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| 236 |
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}
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| 237 |
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| 238 |
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bus = dev->bus;
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pcibios_read_config_word(bus->number, dev->devfn, PCI_COMMAND, &cmd);
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| 240 |
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| 241 |
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for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
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| 242 |
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| 243 |
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#ifdef NOT_NOW
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| 244 |
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if ((dev->vendor == 0x1080) && (dev->device == 0xC693) &&
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| 245 |
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((PCI_FUNC(dev->devfn) == 1) || (PCI_FUNC(dev->devfn) == 2)))
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| 246 |
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{ /* if primary or secondary IDE on the CYPRESS bridge */
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| 247 |
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if ((reg == PCI_BASE_ADDRESS_0) || (reg == PCI_BASE_ADDRESS_1)) {
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| 248 |
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#if 0
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| 249 |
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printk("layout_dev: ignoring CYPRESS IDE base reg 0/1\n");
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| 250 |
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#endif
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| 251 |
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continue; /* ignore first two registers */
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| 252 |
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}
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| 253 |
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}
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| 254 |
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#endif /* NOT_NOW */
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| 255 |
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| 256 |
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/*
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| 257 |
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* Figure out how much space and of what type this
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| 258 |
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* device wants.
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| 259 |
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*/
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| 260 |
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pcibios_write_config_dword(bus->number, dev->devfn, reg,
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| 261 |
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0xffffffff);
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| 262 |
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pcibios_read_config_dword(bus->number, dev->devfn, reg, &base);
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| 263 |
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#if 0
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| 264 |
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printk("layout_dev: slot %d fn %d off 0x%x base 0x%x\n",
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| 265 |
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PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), reg, base);
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| 266 |
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#endif
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| 267 |
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if (!base) {
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| 268 |
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/* this base-address register is unused */
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| 269 |
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continue;
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| 270 |
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}
|
| 271 |
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|
| 272 |
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/*
|
| 273 |
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* We've read the base address register back after
|
| 274 |
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* writing all ones and so now we must decode it.
|
| 275 |
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*/
|
| 276 |
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if (base & PCI_BASE_ADDRESS_SPACE_IO) {
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| 277 |
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/*
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| 278 |
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* I/O space base address register.
|
| 279 |
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*/
|
| 280 |
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cmd |= PCI_COMMAND_IO;
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| 281 |
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|
| 282 |
|
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base &= PCI_BASE_ADDRESS_IO_MASK;
|
| 283 |
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mask = (~base << 1) | 0x1;
|
| 284 |
|
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size = (mask & base) & 0xffffffff;
|
| 285 |
|
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/* align to multiple of size of minimum base */
|
| 286 |
|
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#if 0
|
| 287 |
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alignto = MAX(0x400, size) ;
|
| 288 |
|
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#else
|
| 289 |
|
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/*
|
| 290 |
|
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If we align to 0x800 bounds, we probably avoid
|
| 291 |
|
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having devices in any 0xzCzz range, which is
|
| 292 |
|
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where the DE4X5 driver probes for EISA cards.
|
| 293 |
|
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Adaptecs, especially, resent such intrusions. :-(
|
| 294 |
|
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*/
|
| 295 |
|
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alignto = MAX(0x800, size) ;
|
| 296 |
|
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#endif
|
| 297 |
|
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base = ALIGN(io_base, alignto );
|
| 298 |
|
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io_base = base + size;
|
| 299 |
|
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pcibios_write_config_dword(bus->number, dev->devfn,
|
| 300 |
|
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reg, base | 0x1);
|
| 301 |
|
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DBG_DEVS(("layout_dev: dev 0x%x IO @ 0x%x (0x%x)\n",
|
| 302 |
|
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dev->device, base, size));
|
| 303 |
|
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} else {
|
| 304 |
|
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unsigned int type;
|
| 305 |
|
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/*
|
| 306 |
|
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* Memory space base address register.
|
| 307 |
|
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*/
|
| 308 |
|
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cmd |= PCI_COMMAND_MEMORY;
|
| 309 |
|
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type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
|
| 310 |
|
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base &= PCI_BASE_ADDRESS_MEM_MASK;
|
| 311 |
|
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mask = (~base << 1) | 0x1;
|
| 312 |
|
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size = (mask & base) & 0xffffffff;
|
| 313 |
|
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switch (type) {
|
| 314 |
|
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case PCI_BASE_ADDRESS_MEM_TYPE_32:
|
| 315 |
|
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break;
|
| 316 |
|
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|
| 317 |
|
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case PCI_BASE_ADDRESS_MEM_TYPE_64:
|
| 318 |
|
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printk("bios32 WARNING: "
|
| 319 |
|
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"ignoring 64-bit device in "
|
| 320 |
|
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"slot %d, function %d: \n",
|
| 321 |
|
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PCI_SLOT(dev->devfn),
|
| 322 |
|
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PCI_FUNC(dev->devfn));
|
| 323 |
|
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reg += 4; /* skip extra 4 bytes */
|
| 324 |
|
|
continue;
|
| 325 |
|
|
|
| 326 |
|
|
case PCI_BASE_ADDRESS_MEM_TYPE_1M:
|
| 327 |
|
|
/*
|
| 328 |
|
|
* Allocating memory below 1MB is *very*
|
| 329 |
|
|
* tricky, as there may be all kinds of
|
| 330 |
|
|
* ISA devices lurking that we don't know
|
| 331 |
|
|
* about. For now, we just cross fingers
|
| 332 |
|
|
* and hope nobody tries to do this on an
|
| 333 |
|
|
* Alpha (or that the console has set it
|
| 334 |
|
|
* up properly).
|
| 335 |
|
|
*/
|
| 336 |
|
|
printk("bios32 WARNING: slot %d, function %d "
|
| 337 |
|
|
"requests memory below 1MB---don't "
|
| 338 |
|
|
"know how to do that.\n",
|
| 339 |
|
|
PCI_SLOT(dev->devfn),
|
| 340 |
|
|
PCI_FUNC(dev->devfn));
|
| 341 |
|
|
continue;
|
| 342 |
|
|
}
|
| 343 |
|
|
/*
|
| 344 |
|
|
* The following holds at least for the Low Cost
|
| 345 |
|
|
* Alpha implementation of the PCI interface:
|
| 346 |
|
|
*
|
| 347 |
|
|
* In sparse memory address space, the first
|
| 348 |
|
|
* octant (16 MB) of every 128 MB segment is
|
| 349 |
|
|
* aliased to the very first 16 MB of the
|
| 350 |
|
|
* address space (i.e., it aliases the ISA
|
| 351 |
|
|
* memory address space). Thus, we try to
|
| 352 |
|
|
* avoid allocating PCI devices in that range.
|
| 353 |
|
|
* Can be allocated in 2nd-7th octant only.
|
| 354 |
|
|
* Devices that need more than 112 MB of
|
| 355 |
|
|
* address space must be accessed through
|
| 356 |
|
|
* dense memory space only!
|
| 357 |
|
|
*/
|
| 358 |
|
|
/* align to multiple of size of minimum base */
|
| 359 |
|
|
alignto = MAX(0x1000, size) ;
|
| 360 |
|
|
base = ALIGN(mem_base, alignto);
|
| 361 |
|
|
if (size > 7 * 16*MB) {
|
| 362 |
|
|
printk("bios32 WARNING: slot %d, function %d "
|
| 363 |
|
|
"requests 0x%x bytes of contig address "
|
| 364 |
|
|
" space---don't use sparse memory "
|
| 365 |
|
|
" accesses on this device!!\n",
|
| 366 |
|
|
PCI_SLOT(dev->devfn),
|
| 367 |
|
|
PCI_FUNC(dev->devfn), size);
|
| 368 |
|
|
} else {
|
| 369 |
|
|
if (((base / (16*MB)) & 0x7) == 0) {
|
| 370 |
|
|
base &= ~(128*MB - 1);
|
| 371 |
|
|
base += 16*MB;
|
| 372 |
|
|
base = ALIGN(base, alignto);
|
| 373 |
|
|
}
|
| 374 |
|
|
if (base / (128*MB) != (base + size) / (128*MB))
|
| 375 |
|
|
{
|
| 376 |
|
|
base &= ~(128*MB - 1);
|
| 377 |
|
|
base += (128 + 16)*MB;
|
| 378 |
|
|
base = ALIGN(base, alignto);
|
| 379 |
|
|
}
|
| 380 |
|
|
}
|
| 381 |
|
|
mem_base = base + size;
|
| 382 |
|
|
pcibios_write_config_dword(bus->number, dev->devfn,
|
| 383 |
|
|
reg, base);
|
| 384 |
|
|
DBG_DEVS(("layout_dev: dev 0x%x MEM @ 0x%x (0x%x)\n",
|
| 385 |
|
|
dev->device, base, size));
|
| 386 |
|
|
}
|
| 387 |
|
|
} /* end for-loop */
|
| 388 |
|
|
/* enable device: */
|
| 389 |
|
|
if (dev->class >> 8 == PCI_CLASS_NOT_DEFINED ||
|
| 390 |
|
|
dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA ||
|
| 391 |
|
|
dev->class >> 8 == PCI_CLASS_STORAGE_IDE ||
|
| 392 |
|
|
dev->class >> 16 == PCI_BASE_CLASS_DISPLAY)
|
| 393 |
|
|
{
|
| 394 |
|
|
/*
|
| 395 |
|
|
* All of these (may) have I/O scattered all around
|
| 396 |
|
|
* and may not use i/o-base address registers at all.
|
| 397 |
|
|
* So we just have to always enable I/O to these
|
| 398 |
|
|
* devices.
|
| 399 |
|
|
*/
|
| 400 |
|
|
cmd |= PCI_COMMAND_IO;
|
| 401 |
|
|
}
|
| 402 |
|
|
|
| 403 |
|
|
pcibios_write_config_word(bus->number, dev->devfn, PCI_COMMAND,
|
| 404 |
|
|
cmd | PCI_COMMAND_MASTER);
|
| 405 |
|
|
|
| 406 |
|
|
DBG_DEVS(("layout_dev: bus %d slot %d VID 0x%x DID 0x%x class 0x%x cmd 0x%x\n",
|
| 407 |
|
|
bus->number, PCI_SLOT(dev->devfn), dev->vendor, dev->device,
|
| 408 |
|
|
dev->class, cmd|PCI_COMMAND_MASTER));
|
| 409 |
|
|
}
|
| 410 |
|
|
|
| 411 |
|
|
|
| 412 |
|
|
static int layout_bus(struct pci_bus *bus)
|
| 413 |
|
|
{
|
| 414 |
|
|
unsigned int l, tio, bio, tmem, bmem;
|
| 415 |
|
|
struct pci_bus *child;
|
| 416 |
|
|
struct pci_dev *dev;
|
| 417 |
|
|
int found_vga = 0;
|
| 418 |
|
|
|
| 419 |
|
|
DBG_DEVS(("layout_bus: starting bus %d\n", bus->number));
|
| 420 |
|
|
|
| 421 |
|
|
if (!bus->devices && !bus->children)
|
| 422 |
|
|
return 0;
|
| 423 |
|
|
|
| 424 |
|
|
/*
|
| 425 |
|
|
* Align the current bases on appropriate boundaries (4K for
|
| 426 |
|
|
* IO and 1MB for memory).
|
| 427 |
|
|
*/
|
| 428 |
|
|
bio = io_base = ALIGN(io_base, 4*KB);
|
| 429 |
|
|
bmem = mem_base = ALIGN(mem_base, 1*MB);
|
| 430 |
|
|
|
| 431 |
|
|
/*
|
| 432 |
|
|
* There are times when the PCI devices have already been
|
| 433 |
|
|
* setup (e.g., by MILO or SRM). In these cases there is a
|
| 434 |
|
|
* window during which two devices may have an overlapping
|
| 435 |
|
|
* address range. To avoid this causing trouble, we first
|
| 436 |
|
|
* turn off the I/O and memory address decoders for all PCI
|
| 437 |
|
|
* devices. They'll be re-enabled only once all address
|
| 438 |
|
|
* decoders are programmed consistently.
|
| 439 |
|
|
*/
|
| 440 |
|
|
for (dev = bus->devices; dev; dev = dev->sibling) {
|
| 441 |
|
|
if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE)
|
| 442 |
|
|
#ifdef CONFIG_ALPHA_BOOK1
|
| 443 |
|
|
|| (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA)
|
| 444 |
|
|
#endif /* CONFIG_ALPHA_BOOK1 */
|
| 445 |
|
|
) {
|
| 446 |
|
|
disable_dev(dev) ;
|
| 447 |
|
|
}
|
| 448 |
|
|
}
|
| 449 |
|
|
|
| 450 |
|
|
/*
|
| 451 |
|
|
* Allocate space to each device:
|
| 452 |
|
|
*/
|
| 453 |
|
|
DBG_DEVS(("layout_bus: starting bus %d devices\n", bus->number));
|
| 454 |
|
|
|
| 455 |
|
|
for (dev = bus->devices; dev; dev = dev->sibling) {
|
| 456 |
|
|
if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE)
|
| 457 |
|
|
#ifdef CONFIG_ALPHA_BOOK1
|
| 458 |
|
|
|| (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA)
|
| 459 |
|
|
#endif /* CONFIG_ALPHA_BOOK1 */
|
| 460 |
|
|
) {
|
| 461 |
|
|
layout_dev(dev);
|
| 462 |
|
|
}
|
| 463 |
|
|
if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
|
| 464 |
|
|
found_vga = 1;
|
| 465 |
|
|
}
|
| 466 |
|
|
/*
|
| 467 |
|
|
* Recursively allocate space for all of the sub-buses:
|
| 468 |
|
|
*/
|
| 469 |
|
|
DBG_DEVS(("layout_bus: starting bus %d children\n", bus->number));
|
| 470 |
|
|
|
| 471 |
|
|
for (child = bus->children; child; child = child->next) {
|
| 472 |
|
|
found_vga += layout_bus(child);
|
| 473 |
|
|
}
|
| 474 |
|
|
/*
|
| 475 |
|
|
* Align the current bases on 4K and 1MB boundaries:
|
| 476 |
|
|
*/
|
| 477 |
|
|
tio = io_base = ALIGN(io_base, 4*KB);
|
| 478 |
|
|
tmem = mem_base = ALIGN(mem_base, 1*MB);
|
| 479 |
|
|
|
| 480 |
|
|
if (bus->self) {
|
| 481 |
|
|
struct pci_dev *bridge = bus->self;
|
| 482 |
|
|
/*
|
| 483 |
|
|
* Set up the top and bottom of the PCI I/O segment
|
| 484 |
|
|
* for this bus.
|
| 485 |
|
|
*/
|
| 486 |
|
|
pcibios_read_config_dword(bridge->bus->number, bridge->devfn,
|
| 487 |
|
|
0x1c, &l);
|
| 488 |
|
|
l = (l & 0xffff0000) | ((bio >> 8) & 0x00f0) |
|
| 489 |
|
|
((tio - 1) & 0xf000);
|
| 490 |
|
|
pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
|
| 491 |
|
|
0x1c, l);
|
| 492 |
|
|
/*
|
| 493 |
|
|
* Set up the top and bottom of the PCI Memory segment
|
| 494 |
|
|
* for this bus.
|
| 495 |
|
|
*/
|
| 496 |
|
|
l = ((bmem & 0xfff00000) >> 16) | ((tmem - 1) & 0xfff00000);
|
| 497 |
|
|
pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
|
| 498 |
|
|
0x20, l);
|
| 499 |
|
|
/*
|
| 500 |
|
|
* Turn off downstream PF memory address range:
|
| 501 |
|
|
*/
|
| 502 |
|
|
pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
|
| 503 |
|
|
0x24, 0x0000ffff);
|
| 504 |
|
|
/*
|
| 505 |
|
|
* Tell bridge that there is an ISA bus in the system,
|
| 506 |
|
|
* and (possibly) a VGA as well.
|
| 507 |
|
|
*/
|
| 508 |
|
|
l = 0x00040000; /* ISA present */
|
| 509 |
|
|
if (found_vga) l |= 0x00080000; /* VGA present */
|
| 510 |
|
|
pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
|
| 511 |
|
|
0x3c, l);
|
| 512 |
|
|
/*
|
| 513 |
|
|
* Clear status bits, enable I/O (for downstream I/O),
|
| 514 |
|
|
* turn on master enable (for upstream I/O), turn on
|
| 515 |
|
|
* memory enable (for downstream memory), turn on
|
| 516 |
|
|
* master enable (for upstream memory and I/O).
|
| 517 |
|
|
*/
|
| 518 |
|
|
pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
|
| 519 |
|
|
0x4, 0xffff0007);
|
| 520 |
|
|
}
|
| 521 |
|
|
return found_vga;
|
| 522 |
|
|
}
|
| 523 |
|
|
|
| 524 |
|
|
#endif /* !PCI_MODIFY */
|
| 525 |
|
|
|
| 526 |
|
|
|
| 527 |
|
|
/*
|
| 528 |
|
|
* Given the vendor and device ids, find the n'th instance of that device
|
| 529 |
|
|
* in the system.
|
| 530 |
|
|
*/
|
| 531 |
|
|
int pcibios_find_device (unsigned short vendor, unsigned short device_id,
|
| 532 |
|
|
unsigned short index, unsigned char *bus,
|
| 533 |
|
|
unsigned char *devfn)
|
| 534 |
|
|
{
|
| 535 |
|
|
unsigned int curr = 0;
|
| 536 |
|
|
struct pci_dev *dev;
|
| 537 |
|
|
|
| 538 |
|
|
for (dev = pci_devices; dev; dev = dev->next) {
|
| 539 |
|
|
if (dev->vendor == vendor && dev->device == device_id) {
|
| 540 |
|
|
if (curr == index) {
|
| 541 |
|
|
*devfn = dev->devfn;
|
| 542 |
|
|
*bus = dev->bus->number;
|
| 543 |
|
|
return PCIBIOS_SUCCESSFUL;
|
| 544 |
|
|
}
|
| 545 |
|
|
++curr;
|
| 546 |
|
|
}
|
| 547 |
|
|
}
|
| 548 |
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
| 549 |
|
|
}
|
| 550 |
|
|
|
| 551 |
|
|
|
| 552 |
|
|
/*
|
| 553 |
|
|
* Given the class, find the n'th instance of that device
|
| 554 |
|
|
* in the system.
|
| 555 |
|
|
*/
|
| 556 |
|
|
int pcibios_find_class (unsigned int class_code, unsigned short index,
|
| 557 |
|
|
unsigned char *bus, unsigned char *devfn)
|
| 558 |
|
|
{
|
| 559 |
|
|
unsigned int curr = 0;
|
| 560 |
|
|
struct pci_dev *dev;
|
| 561 |
|
|
|
| 562 |
|
|
for (dev = pci_devices; dev; dev = dev->next) {
|
| 563 |
|
|
if (dev->class == class_code) {
|
| 564 |
|
|
if (curr == index) {
|
| 565 |
|
|
*devfn = dev->devfn;
|
| 566 |
|
|
*bus = dev->bus->number;
|
| 567 |
|
|
return PCIBIOS_SUCCESSFUL;
|
| 568 |
|
|
}
|
| 569 |
|
|
++curr;
|
| 570 |
|
|
}
|
| 571 |
|
|
}
|
| 572 |
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
| 573 |
|
|
}
|
| 574 |
|
|
|
| 575 |
|
|
|
| 576 |
|
|
int pcibios_present(void)
|
| 577 |
|
|
{
|
| 578 |
|
|
return 1;
|
| 579 |
|
|
}
|
| 580 |
|
|
|
| 581 |
|
|
|
| 582 |
|
|
unsigned long pcibios_init(unsigned long mem_start,
|
| 583 |
|
|
unsigned long mem_end)
|
| 584 |
|
|
{
|
| 585 |
|
|
printk("Alpha PCI BIOS32 revision %x.%02x\n", MAJOR_REV, MINOR_REV);
|
| 586 |
|
|
|
| 587 |
|
|
#if !PCI_MODIFY
|
| 588 |
|
|
printk("...NOT modifying existing (SRM) PCI configuration\n");
|
| 589 |
|
|
#endif
|
| 590 |
|
|
return mem_start;
|
| 591 |
|
|
}
|
| 592 |
|
|
|
| 593 |
|
|
/*
|
| 594 |
|
|
* The SRM console *disables* the IDE interface, this code ensures it's
|
| 595 |
|
|
* enabled.
|
| 596 |
|
|
*
|
| 597 |
|
|
* This code bangs on a control register of the 87312 Super I/O chip
|
| 598 |
|
|
* that implements parallel port/serial ports/IDE/FDI. Depending on
|
| 599 |
|
|
* the motherboard, the Super I/O chip can be configured through a
|
| 600 |
|
|
* pair of registers that are located either at I/O ports 0x26e/0x26f
|
| 601 |
|
|
* or 0x398/0x399. Unfortunately, autodetecting which base address is
|
| 602 |
|
|
* in use works only once (right after a reset). The Super I/O chip
|
| 603 |
|
|
* has the additional quirk that configuration register data must be
|
| 604 |
|
|
* written twice (I believe this is a safety feature to prevent
|
| 605 |
|
|
* accidental modification---fun, isn't it?).
|
| 606 |
|
|
*/
|
| 607 |
|
|
static inline void enable_ide(long ide_base)
|
| 608 |
|
|
{
|
| 609 |
|
|
int data;
|
| 610 |
|
|
|
| 611 |
|
|
outb(0, ide_base); /* set the index register for reg #0 */
|
| 612 |
|
|
data = inb(ide_base+1); /* read the current contents */
|
| 613 |
|
|
outb(0, ide_base); /* set the index register for reg #0 */
|
| 614 |
|
|
outb(data | 0x40, ide_base+1); /* turn on IDE */
|
| 615 |
|
|
outb(data | 0x40, ide_base+1); /* turn on IDE, really! */
|
| 616 |
|
|
}
|
| 617 |
|
|
|
| 618 |
|
|
/*
|
| 619 |
|
|
* A small note about bridges and interrupts. The DC 21050 (and later chips)
|
| 620 |
|
|
* adheres to the PCI-PCI bridge specification. This says that the interrupts
|
| 621 |
|
|
* on the other side of a bridge are swizzled in the following manner:
|
| 622 |
|
|
*
|
| 623 |
|
|
* Dev Interrupt Interrupt
|
| 624 |
|
|
* Pin on Pin on
|
| 625 |
|
|
* Device Connector
|
| 626 |
|
|
*
|
| 627 |
|
|
* 4 A A
|
| 628 |
|
|
* B B
|
| 629 |
|
|
* C C
|
| 630 |
|
|
* D D
|
| 631 |
|
|
*
|
| 632 |
|
|
* 5 A B
|
| 633 |
|
|
* B C
|
| 634 |
|
|
* C D
|
| 635 |
|
|
* D A
|
| 636 |
|
|
*
|
| 637 |
|
|
* 6 A C
|
| 638 |
|
|
* B D
|
| 639 |
|
|
* C A
|
| 640 |
|
|
* D B
|
| 641 |
|
|
*
|
| 642 |
|
|
* 7 A D
|
| 643 |
|
|
* B A
|
| 644 |
|
|
* C B
|
| 645 |
|
|
* D C
|
| 646 |
|
|
*
|
| 647 |
|
|
* Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
|
| 648 |
|
|
* Thus, each swizzle is ((pin-1) + (device#-4)) % 4
|
| 649 |
|
|
*
|
| 650 |
|
|
* The following code is somewhat simplistic as it assumes only one bridge.
|
| 651 |
|
|
* I will fix it later (david.rusling@reo.mts.dec.com).
|
| 652 |
|
|
*/
|
| 653 |
|
|
static inline unsigned char bridge_swizzle(unsigned char pin, unsigned int slot)
|
| 654 |
|
|
{
|
| 655 |
|
|
/* swizzle */
|
| 656 |
|
|
return (((pin-1) + slot) % 4) + 1 ;
|
| 657 |
|
|
}
|
| 658 |
|
|
|
| 659 |
|
|
#ifdef CONFIG_ALPHA_SRM_SETUP
|
| 660 |
|
|
/* look for mis-configured devices' IO space addresses behind bridges */
|
| 661 |
|
|
static void check_behind_io(struct pci_dev *dev)
|
| 662 |
|
|
{
|
| 663 |
|
|
struct pci_bus *bus = dev->bus;
|
| 664 |
|
|
unsigned int reg, orig_base, new_base, found_one = 0;
|
| 665 |
|
|
|
| 666 |
|
|
for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
|
| 667 |
|
|
/* read the current setting, check for I/O space and >= 64K */
|
| 668 |
|
|
pcibios_read_config_dword(bus->number, dev->devfn, reg, &orig_base);
|
| 669 |
|
|
if (!orig_base || !(orig_base & PCI_BASE_ADDRESS_SPACE_IO))
|
| 670 |
|
|
continue; /* unused or non-IO */
|
| 671 |
|
|
if (orig_base < 64*1024) {
|
| 672 |
|
|
#if 1
|
| 673 |
|
|
printk("check_behind_io: ALREADY OK! bus %d slot %d base 0x%x\n",
|
| 674 |
|
|
bus->number, PCI_SLOT(dev->devfn), orig_base);
|
| 675 |
|
|
#endif
|
| 676 |
|
|
if (orig_base & ~1)
|
| 677 |
|
|
continue; /* OK! */
|
| 678 |
|
|
orig_base = 0x12001; /* HACK! FIXME!! */
|
| 679 |
|
|
}
|
| 680 |
|
|
|
| 681 |
|
|
/* HACK ALERT! for now, just subtract 32K from the
|
| 682 |
|
|
original address, which should give us addresses
|
| 683 |
|
|
in the range 0x8000 and up */
|
| 684 |
|
|
new_base = orig_base - 0x8000;
|
| 685 |
|
|
#if 1
|
| 686 |
|
|
printk("check_behind_io: ALERT! bus %d slot %d old 0x%x new 0x%x\n",
|
| 687 |
|
|
bus->number, PCI_SLOT(dev->devfn), orig_base, new_base);
|
| 688 |
|
|
#endif
|
| 689 |
|
|
pcibios_write_config_dword(bus->number, dev->devfn,
|
| 690 |
|
|
reg, new_base);
|
| 691 |
|
|
|
| 692 |
|
|
io_dev_to_reset[io_reset_count] = dev;
|
| 693 |
|
|
io_reg_to_reset[io_reset_count] = reg;
|
| 694 |
|
|
io_to_reset[io_reset_count] = orig_base;
|
| 695 |
|
|
io_reset_count++;
|
| 696 |
|
|
found_one++;
|
| 697 |
|
|
} /* end for-loop */
|
| 698 |
|
|
|
| 699 |
|
|
/* if any were modified, gotta hack the bridge IO limits too... */
|
| 700 |
|
|
if (found_one) {
|
| 701 |
|
|
if (bus->self) {
|
| 702 |
|
|
struct pci_dev *bridge = bus->self;
|
| 703 |
|
|
unsigned int l;
|
| 704 |
|
|
/*
|
| 705 |
|
|
* Set up the top and bottom of the PCI I/O segment
|
| 706 |
|
|
* for this bus.
|
| 707 |
|
|
*/
|
| 708 |
|
|
pcibios_read_config_dword(bridge->bus->number,
|
| 709 |
|
|
bridge->devfn, 0x1c, &l);
|
| 710 |
|
|
#if 1
|
| 711 |
|
|
printk("check_behind_io: ALERT! bus %d slot %d oldLIM 0x%x\n",
|
| 712 |
|
|
bus->number, PCI_SLOT(bridge->devfn), l);
|
| 713 |
|
|
#endif
|
| 714 |
|
|
l = (l & 0xffff0000U) | 0xf080U; /* give it ALL */
|
| 715 |
|
|
pcibios_write_config_dword(bridge->bus->number,
|
| 716 |
|
|
bridge->devfn, 0x1c, l);
|
| 717 |
|
|
pcibios_write_config_dword(bridge->bus->number,
|
| 718 |
|
|
bridge->devfn,
|
| 719 |
|
|
0x3c, 0x00040000);
|
| 720 |
|
|
pcibios_write_config_dword(bridge->bus->number,
|
| 721 |
|
|
bridge->devfn,
|
| 722 |
|
|
0x4, 0xffff0007);
|
| 723 |
|
|
} else
|
| 724 |
|
|
printk("check_behind_io: WARNING! bus->self NULL\n");
|
| 725 |
|
|
}
|
| 726 |
|
|
}
|
| 727 |
|
|
#endif /* CONFIG_ALPHA_SRM_SETUP */
|
| 728 |
|
|
|
| 729 |
|
|
/*
|
| 730 |
|
|
* Most evaluation boards share most of the fixup code, which is isolated here.
|
| 731 |
|
|
* This function is declared "inline" as only one platform will ever be selected
|
| 732 |
|
|
* in any given kernel. If that platform doesn't need this code, we don't want
|
| 733 |
|
|
* it around as dead code.
|
| 734 |
|
|
*/
|
| 735 |
|
|
static inline void common_fixup(
|
| 736 |
|
|
long min_idsel,
|
| 737 |
|
|
long max_idsel,
|
| 738 |
|
|
long irqs_per_slot,
|
| 739 |
|
|
char irq_tab[max_idsel - min_idsel + 1][irqs_per_slot],
|
| 740 |
|
|
long ide_base)
|
| 741 |
|
|
{
|
| 742 |
|
|
struct pci_dev *dev;
|
| 743 |
|
|
unsigned char pin;
|
| 744 |
|
|
unsigned char slot ;
|
| 745 |
|
|
|
| 746 |
|
|
/*
|
| 747 |
|
|
* Go through all devices, fixing up irqs as we see fit:
|
| 748 |
|
|
*/
|
| 749 |
|
|
for (dev = pci_devices; dev; dev = dev->next) {
|
| 750 |
|
|
if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE)
|
| 751 |
|
|
#if defined(CONFIG_ALPHA_EISA)
|
| 752 |
|
|
/* PCEB (PCI to EISA bridge) does not identify
|
| 753 |
|
|
itself as a bridge... :-( */
|
| 754 |
|
|
&& !((dev->vendor==0x8086) && (dev->device==0x482))
|
| 755 |
|
|
#endif
|
| 756 |
|
|
#ifdef CONFIG_ALPHA_BOOK1
|
| 757 |
|
|
|| (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA)
|
| 758 |
|
|
#endif /* CONFIG_ALPHA_BOOK1 */
|
| 759 |
|
|
) {
|
| 760 |
|
|
dev->irq = 0;
|
| 761 |
|
|
/*
|
| 762 |
|
|
* This device is not on the primary bus,
|
| 763 |
|
|
* we need to figure out which
|
| 764 |
|
|
* interrupt pin it will come in on.
|
| 765 |
|
|
* We know which slot it will come
|
| 766 |
|
|
* in on 'cuz that slot is where the bridge is.
|
| 767 |
|
|
* Each time the interrupt
|
| 768 |
|
|
* line passes through a PCI-PCI bridge
|
| 769 |
|
|
* we must apply the swizzle function
|
| 770 |
|
|
* (see the inline static routine above).
|
| 771 |
|
|
*/
|
| 772 |
|
|
if (dev->bus->number != 0) {
|
| 773 |
|
|
/* read the pin and do the PCI-PCI bridge
|
| 774 |
|
|
interrupt pin swizzle */
|
| 775 |
|
|
pcibios_read_config_byte(dev->bus->number,
|
| 776 |
|
|
dev->devfn,
|
| 777 |
|
|
PCI_INTERRUPT_PIN,
|
| 778 |
|
|
&pin);
|
| 779 |
|
|
/* cope with 0 */
|
| 780 |
|
|
if (pin == 0) pin = 1 ;
|
| 781 |
|
|
/* follow the chain of bridges,
|
| 782 |
|
|
swizzling as we go */
|
| 783 |
|
|
#if defined(CONFIG_ALPHA_MIATA)
|
| 784 |
|
|
/* check first for the built-in bridge */
|
| 785 |
|
|
if ((PCI_SLOT(dev->bus->self->devfn) == 8) ||
|
| 786 |
|
|
(PCI_SLOT(dev->bus->self->devfn) == 20)) {
|
| 787 |
|
|
slot = PCI_SLOT(dev->devfn) + 9;
|
| 788 |
|
|
#if 0
|
| 789 |
|
|
printk("MIATA: bus 1 slot %d pin %d irq %d "
|
| 790 |
|
|
"min_idsel %d\n",
|
| 791 |
|
|
PCI_SLOT(dev->devfn), pin,
|
| 792 |
|
|
irq_tab[slot - min_idsel][pin],
|
| 793 |
|
|
min_idsel);
|
| 794 |
|
|
#endif
|
| 795 |
|
|
}
|
| 796 |
|
|
else /* must be a card-based bridge */
|
| 797 |
|
|
{
|
| 798 |
|
|
struct pci_dev *curr = dev ;
|
| 799 |
|
|
do {
|
| 800 |
|
|
if ((PCI_SLOT(curr->bus->self->devfn) == 8) ||
|
| 801 |
|
|
(PCI_SLOT(curr->bus->self->devfn) == 20))
|
| 802 |
|
|
{
|
| 803 |
|
|
slot = PCI_SLOT(curr->devfn) + 5;
|
| 804 |
|
|
break;
|
| 805 |
|
|
}
|
| 806 |
|
|
/* swizzle */
|
| 807 |
|
|
pin = bridge_swizzle(
|
| 808 |
|
|
pin, PCI_SLOT(curr->devfn)) ;
|
| 809 |
|
|
/* move up the chain of bridges */
|
| 810 |
|
|
curr = curr->bus->self ;
|
| 811 |
|
|
/* slot of the next bridge. */
|
| 812 |
|
|
slot = PCI_SLOT(curr->devfn);
|
| 813 |
|
|
} while (curr->bus->self) ;
|
| 814 |
|
|
}
|
| 815 |
|
|
#elif defined(CONFIG_ALPHA_NORITAKE)
|
| 816 |
|
|
/* check first for the built-in bridge */
|
| 817 |
|
|
if (PCI_SLOT(dev->bus->self->devfn) == 8) {
|
| 818 |
|
|
slot = PCI_SLOT(dev->devfn) + 15; /* WAG! */
|
| 819 |
|
|
#if 0
|
| 820 |
|
|
printk("NORITAKE: bus 1 slot %d pin %d "
|
| 821 |
|
|
"irq %d min_idsel %d\n",
|
| 822 |
|
|
PCI_SLOT(dev->devfn), pin,
|
| 823 |
|
|
irq_tab[slot - min_idsel][pin],
|
| 824 |
|
|
min_idsel);
|
| 825 |
|
|
#endif
|
| 826 |
|
|
}
|
| 827 |
|
|
else /* must be a card-based bridge */
|
| 828 |
|
|
{
|
| 829 |
|
|
struct pci_dev *curr = dev ;
|
| 830 |
|
|
do {
|
| 831 |
|
|
if (PCI_SLOT(curr->bus->self->devfn) == 8) {
|
| 832 |
|
|
slot = PCI_SLOT(curr->devfn) + 15;
|
| 833 |
|
|
break;
|
| 834 |
|
|
}
|
| 835 |
|
|
/* swizzle */
|
| 836 |
|
|
pin = bridge_swizzle(
|
| 837 |
|
|
pin, PCI_SLOT(curr->devfn)) ;
|
| 838 |
|
|
/* move up the chain of bridges */
|
| 839 |
|
|
curr = curr->bus->self ;
|
| 840 |
|
|
/* slot of the next bridge. */
|
| 841 |
|
|
slot = PCI_SLOT(curr->devfn);
|
| 842 |
|
|
} while (curr->bus->self) ;
|
| 843 |
|
|
}
|
| 844 |
|
|
#else /* not MIATA or NORITAKE */
|
| 845 |
|
|
{
|
| 846 |
|
|
struct pci_dev *curr = dev ;
|
| 847 |
|
|
do {
|
| 848 |
|
|
/* swizzle */
|
| 849 |
|
|
pin = bridge_swizzle(
|
| 850 |
|
|
pin, PCI_SLOT(curr->devfn)) ;
|
| 851 |
|
|
/* move up the chain of bridges */
|
| 852 |
|
|
curr = curr->bus->self ;
|
| 853 |
|
|
} while (curr->bus->self) ;
|
| 854 |
|
|
/* The slot is the slot of the last bridge. */
|
| 855 |
|
|
slot = PCI_SLOT(curr->devfn) ;
|
| 856 |
|
|
}
|
| 857 |
|
|
#endif /* not MIATA or NORITAKE */
|
| 858 |
|
|
#ifdef CONFIG_ALPHA_SRM_SETUP
|
| 859 |
|
|
/*
|
| 860 |
|
|
must make sure that SRM didn't screw up
|
| 861 |
|
|
and allocate an address > 64K for I/O
|
| 862 |
|
|
space behind a PCI-PCI bridge
|
| 863 |
|
|
*/
|
| 864 |
|
|
check_behind_io(dev);
|
| 865 |
|
|
#endif /* CONFIG_ALPHA_SRM_SETUP */
|
| 866 |
|
|
} else {
|
| 867 |
|
|
/* work out the slot */
|
| 868 |
|
|
slot = PCI_SLOT(dev->devfn) ;
|
| 869 |
|
|
/* read the pin */
|
| 870 |
|
|
pcibios_read_config_byte(dev->bus->number,
|
| 871 |
|
|
dev->devfn,
|
| 872 |
|
|
PCI_INTERRUPT_PIN,
|
| 873 |
|
|
&pin);
|
| 874 |
|
|
}
|
| 875 |
|
|
if (irq_tab[slot - min_idsel][pin] != -1)
|
| 876 |
|
|
dev->irq = irq_tab[slot - min_idsel][pin];
|
| 877 |
|
|
|
| 878 |
|
|
#ifdef CONFIG_ALPHA_SRM
|
| 879 |
|
|
{
|
| 880 |
|
|
unsigned char irq_orig;
|
| 881 |
|
|
/* read the original SRM-set IRQ and tell */
|
| 882 |
|
|
pcibios_read_config_byte(dev->bus->number,
|
| 883 |
|
|
dev->devfn,
|
| 884 |
|
|
PCI_INTERRUPT_LINE,
|
| 885 |
|
|
&irq_orig);
|
| 886 |
|
|
if (irq_orig != dev->irq) {
|
| 887 |
|
|
printk("common_fixup: bus %d slot 0x%x "
|
| 888 |
|
|
"SRM IRQ 0x%x changed to 0x%x\n",
|
| 889 |
|
|
dev->bus->number,PCI_SLOT(dev->devfn),
|
| 890 |
|
|
irq_orig, dev->irq);
|
| 891 |
|
|
#ifdef CONFIG_ALPHA_SRM_SETUP
|
| 892 |
|
|
irq_dev_to_reset[irq_reset_count] = dev;
|
| 893 |
|
|
irq_to_reset[irq_reset_count] = irq_orig;
|
| 894 |
|
|
irq_reset_count++;
|
| 895 |
|
|
#endif /* CONFIG_ALPHA_SRM_SETUP */
|
| 896 |
|
|
}
|
| 897 |
|
|
}
|
| 898 |
|
|
#endif /* SRM */
|
| 899 |
|
|
|
| 900 |
|
|
/* always tell the device, so the driver knows */
|
| 901 |
|
|
pcibios_write_config_byte(dev->bus->number, dev->devfn,
|
| 902 |
|
|
PCI_INTERRUPT_LINE, dev->irq);
|
| 903 |
|
|
|
| 904 |
|
|
DBG_DEVS(("common_fixup: bus %d slot 0x%x VID 0x%x DID 0x%x\n"
|
| 905 |
|
|
" int_slot 0x%x pin 0x%x irq 0x%x\n",
|
| 906 |
|
|
dev->bus->number, PCI_SLOT(dev->devfn), dev->vendor,
|
| 907 |
|
|
dev->device, slot, pin, dev->irq));
|
| 908 |
|
|
|
| 909 |
|
|
/*
|
| 910 |
|
|
* if it's a VGA, enable its BIOS ROM at C0000
|
| 911 |
|
|
*/
|
| 912 |
|
|
if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
|
| 913 |
|
|
/* but if its a Cirrus 543x/544x DISABLE it, */
|
| 914 |
|
|
/* since enabling ROM disables the memory... */
|
| 915 |
|
|
if ((dev->vendor == PCI_VENDOR_ID_CIRRUS) &&
|
| 916 |
|
|
(dev->device >= 0x00a0) &&
|
| 917 |
|
|
(dev->device <= 0x00ac)) {
|
| 918 |
|
|
pcibios_write_config_dword(
|
| 919 |
|
|
dev->bus->number,
|
| 920 |
|
|
dev->devfn,
|
| 921 |
|
|
PCI_ROM_ADDRESS,
|
| 922 |
|
|
0x00000000);
|
| 923 |
|
|
} else {
|
| 924 |
|
|
pcibios_write_config_dword(
|
| 925 |
|
|
dev->bus->number,
|
| 926 |
|
|
dev->devfn,
|
| 927 |
|
|
PCI_ROM_ADDRESS,
|
| 928 |
|
|
0x000c0000 | PCI_ROM_ADDRESS_ENABLE);
|
| 929 |
|
|
}
|
| 930 |
|
|
}
|
| 931 |
|
|
/*
|
| 932 |
|
|
* if it's a SCSI, disable its BIOS ROM
|
| 933 |
|
|
*/
|
| 934 |
|
|
if ((dev->class >> 8) == PCI_CLASS_STORAGE_SCSI) {
|
| 935 |
|
|
pcibios_write_config_dword(dev->bus->number,
|
| 936 |
|
|
dev->devfn,
|
| 937 |
|
|
PCI_ROM_ADDRESS,
|
| 938 |
|
|
0x0000000);
|
| 939 |
|
|
}
|
| 940 |
|
|
#ifdef NOT_NOW
|
| 941 |
|
|
if ((dev->vendor == 0x1080) && (dev->device == 0xC693)
|
| 942 |
|
|
&& (PCI_FUNC(dev->devfn) == 1))
|
| 943 |
|
|
{
|
| 944 |
|
|
#if 0
|
| 945 |
|
|
{
|
| 946 |
|
|
int i; unsigned char b; unsigned short w; unsigned int d;
|
| 947 |
|
|
pcibios_read_config_word(dev->bus->number, dev->devfn, 4, &w);
|
| 948 |
|
|
printk("common_fixup: CYPRESS fn 1: PCI CMD reg = 0x%x\n", w);
|
| 949 |
|
|
pcibios_read_config_word(dev->bus->number, dev->devfn, 6, &w);
|
| 950 |
|
|
printk("common_fixup: CYPRESS fn 1: PCI STS reg = 0x%x\n", w);
|
| 951 |
|
|
for (i = 0x10; i <= 0x14; i+=4) {
|
| 952 |
|
|
pcibios_read_config_dword(dev->bus->number, dev->devfn, i, &d);
|
| 953 |
|
|
printk("common_fixup: CYPRESS fn 1: PCI register offset 0x%x = 0x%x\n",i,d);
|
| 954 |
|
|
}
|
| 955 |
|
|
pcibios_read_config_dword(dev->bus->number, dev->devfn, 0x20, &d);
|
| 956 |
|
|
printk("common_fixup: CYPRESS fn 1: PCI register offset 0x20 = 0x%x\n", d);
|
| 957 |
|
|
for (i = 0x3c; i <= 0x3d; i++) {
|
| 958 |
|
|
pcibios_read_config_byte(dev->bus->number, dev->devfn, i, &b);
|
| 959 |
|
|
printk("common_fixup: CYPRESS fn 1: PCI register offset 0x%x = 0x%x\n",i,b);
|
| 960 |
|
|
}
|
| 961 |
|
|
pcibios_read_config_dword(dev->bus->number, dev->devfn, 0x40, &d);
|
| 962 |
|
|
printk("common_fixup: CYPRESS fn 1: PCI register offset 0x40 = 0x%x\n",d);
|
| 963 |
|
|
}
|
| 964 |
|
|
#endif
|
| 965 |
|
|
}
|
| 966 |
|
|
if ((dev->vendor == 0x1080) && (dev->device == 0xC693)
|
| 967 |
|
|
&& (PCI_FUNC(dev->devfn) == 2))
|
| 968 |
|
|
{
|
| 969 |
|
|
#if 0
|
| 970 |
|
|
{
|
| 971 |
|
|
int i; unsigned char b; unsigned short w; unsigned int d;
|
| 972 |
|
|
pcibios_read_config_word(dev->bus->number, dev->devfn, 4, &w);
|
| 973 |
|
|
printk("common_fixup: CYPRESS fn 2: PCI CMD reg = 0x%x\n", w);
|
| 974 |
|
|
pcibios_read_config_word(dev->bus->number, dev->devfn, 6, &w);
|
| 975 |
|
|
printk("common_fixup: CYPRESS fn 2: PCI STS reg = 0x%x\n", w);
|
| 976 |
|
|
for (i = 0x10; i <= 0x14; i+=4) {
|
| 977 |
|
|
pcibios_read_config_dword(dev->bus->number, dev->devfn, i, &d);
|
| 978 |
|
|
printk("common_fixup: CYPRESS fn 2: PCI register offset 0x%x = 0x%x\n",i,d);
|
| 979 |
|
|
}
|
| 980 |
|
|
pcibios_read_config_dword(dev->bus->number, dev->devfn, 0x20, &d);
|
| 981 |
|
|
printk("common_fixup: CYPRESS fn 2: PCI register offset 0x20 = 0x%x\n", d);
|
| 982 |
|
|
for (i = 0x3c; i <= 0x3d; i++) {
|
| 983 |
|
|
pcibios_read_config_byte(dev->bus->number, dev->devfn, i, &b);
|
| 984 |
|
|
printk("common_fixup: CYPRESS fn 2: PCI register offset 0x%x = 0x%x\n",i,b);
|
| 985 |
|
|
}
|
| 986 |
|
|
pcibios_read_config_dword(dev->bus->number, dev->devfn, 0x40, &d);
|
| 987 |
|
|
printk("common_fixup: CYPRESS fn 2: PCI register offset 0x40 = 0x%x\n",d);
|
| 988 |
|
|
}
|
| 989 |
|
|
#endif
|
| 990 |
|
|
}
|
| 991 |
|
|
#endif /* NOT_NOW */
|
| 992 |
|
|
} else { /* it *is* a bridge... */
|
| 993 |
|
|
#ifdef NOT_NOW
|
| 994 |
|
|
/*
|
| 995 |
|
|
* if it's CYPRESS PCI-ISA bridge, disable IDE
|
| 996 |
|
|
* interrupt routing through PCI (ie do through PIC)
|
| 997 |
|
|
*/
|
| 998 |
|
|
if ((dev->vendor == 0x1080) && (dev->device == 0xC693)
|
| 999 |
|
|
&& (PCI_FUNC(dev->devfn) == 0))
|
| 1000 |
|
|
{
|
| 1001 |
|
|
#if 0
|
| 1002 |
|
|
{
|
| 1003 |
|
|
int i; unsigned char d; unsigned short w;
|
| 1004 |
|
|
pcibios_read_config_word(dev->bus->number, dev->devfn, 4, &w);
|
| 1005 |
|
|
printk("common_fixup: CYPRESS fn 0: PCI CMD reg = 0x%x\n", w);
|
| 1006 |
|
|
for (i = 0x40; i < 0x50; i++) {
|
| 1007 |
|
|
pcibios_read_config_byte(dev->bus->number, dev->devfn, i, &d);
|
| 1008 |
|
|
printk("common_fixup: CYPRESS fn 0: PCI register offset 0x%x = 0x%x\n",
|
| 1009 |
|
|
i, d);
|
| 1010 |
|
|
}
|
| 1011 |
|
|
for (i=1; i <= 5; i++) {
|
| 1012 |
|
|
outb(i, 0x22);
|
| 1013 |
|
|
printk("CY control reg %d: 0x%02x\n", i, inb(0x23));
|
| 1014 |
|
|
}
|
| 1015 |
|
|
}
|
| 1016 |
|
|
#endif
|
| 1017 |
|
|
#if 0
|
| 1018 |
|
|
pcibios_write_config_word(dev->bus->number,
|
| 1019 |
|
|
dev->devfn, 0x04, 0x0007);
|
| 1020 |
|
|
|
| 1021 |
|
|
pcibios_write_config_byte(dev->bus->number,
|
| 1022 |
|
|
dev->devfn, 0x40, 0x80);
|
| 1023 |
|
|
pcibios_write_config_byte(dev->bus->number,
|
| 1024 |
|
|
dev->devfn, 0x41, 0x80);
|
| 1025 |
|
|
pcibios_write_config_byte(dev->bus->number,
|
| 1026 |
|
|
dev->devfn, 0x42, 0x80);
|
| 1027 |
|
|
pcibios_write_config_byte(dev->bus->number,
|
| 1028 |
|
|
dev->devfn, 0x43, 0x80);
|
| 1029 |
|
|
pcibios_write_config_byte(dev->bus->number,
|
| 1030 |
|
|
dev->devfn, 0x44, 0x27);
|
| 1031 |
|
|
pcibios_write_config_byte(dev->bus->number,
|
| 1032 |
|
|
dev->devfn, 0x45, 0xe0);
|
| 1033 |
|
|
pcibios_write_config_byte(dev->bus->number,
|
| 1034 |
|
|
dev->devfn, 0x48, 0xf0);
|
| 1035 |
|
|
pcibios_write_config_byte(dev->bus->number,
|
| 1036 |
|
|
dev->devfn, 0x49, 0x40);
|
| 1037 |
|
|
pcibios_write_config_byte(dev->bus->number,
|
| 1038 |
|
|
dev->devfn, 0x4a, 0x00);
|
| 1039 |
|
|
pcibios_write_config_byte(dev->bus->number,
|
| 1040 |
|
|
dev->devfn, 0x4b, 0x80);
|
| 1041 |
|
|
pcibios_write_config_byte(dev->bus->number,
|
| 1042 |
|
|
dev->devfn, 0x4c, 0x80);
|
| 1043 |
|
|
pcibios_write_config_byte(dev->bus->number,
|
| 1044 |
|
|
dev->devfn, 0x4d, 0x70);
|
| 1045 |
|
|
#endif
|
| 1046 |
|
|
outb(0, DMA1_RESET_REG);
|
| 1047 |
|
|
outb(0, DMA2_RESET_REG);
|
| 1048 |
|
|
outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
|
| 1049 |
|
|
outb(0, DMA2_MASK_REG);
|
| 1050 |
|
|
#if 0
|
| 1051 |
|
|
outb(0, DMA1_CLR_MASK_REG);
|
| 1052 |
|
|
outb(0, DMA2_CLR_MASK_REG);
|
| 1053 |
|
|
#endif
|
| 1054 |
|
|
}
|
| 1055 |
|
|
#endif /* NOT_NOW */
|
| 1056 |
|
|
}
|
| 1057 |
|
|
}
|
| 1058 |
|
|
if (ide_base) {
|
| 1059 |
|
|
enable_ide(ide_base);
|
| 1060 |
|
|
}
|
| 1061 |
|
|
}
|
| 1062 |
|
|
|
| 1063 |
|
|
|
| 1064 |
|
|
/*
|
| 1065 |
|
|
* The EB66+ is very similar to the EB66 except that it does not have
|
| 1066 |
|
|
* the on-board NCR and Tulip chips. In the code below, I have used
|
| 1067 |
|
|
* slot number to refer to the id select line and *not* the slot
|
| 1068 |
|
|
* number used in the EB66+ documentation. However, in the table,
|
| 1069 |
|
|
* I've given the slot number, the id select line and the Jxx number
|
| 1070 |
|
|
* that's printed on the board. The interrupt pins from the PCI slots
|
| 1071 |
|
|
* are wired into 3 interrupt summary registers at 0x804, 0x805 and
|
| 1072 |
|
|
* 0x806 ISA.
|
| 1073 |
|
|
*
|
| 1074 |
|
|
* In the table, -1 means don't assign an IRQ number. This is usually
|
| 1075 |
|
|
* because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
|
| 1076 |
|
|
*/
|
| 1077 |
|
|
static inline void eb66p_fixup(void)
|
| 1078 |
|
|
{
|
| 1079 |
|
|
char irq_tab[5][5] = {
|
| 1080 |
|
|
/*INT INTA INTB INTC INTD */
|
| 1081 |
|
|
{16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J25 */
|
| 1082 |
|
|
{16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J26 */
|
| 1083 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
|
| 1084 |
|
|
{16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 9, slot 2, J27 */
|
| 1085 |
|
|
{16+3, 16+3, 16+8, 16+12, 16+6} /* IdSel 10, slot 3, J28 */
|
| 1086 |
|
|
};
|
| 1087 |
|
|
common_fixup(6, 10, 5, irq_tab, 0x398);
|
| 1088 |
|
|
}
|
| 1089 |
|
|
|
| 1090 |
|
|
|
| 1091 |
|
|
/*
|
| 1092 |
|
|
* The PC164/LX164 have 19 PCI interrupts, four from each of the four PCI
|
| 1093 |
|
|
* slots, the SIO, PCI/IDE, and USB.
|
| 1094 |
|
|
*
|
| 1095 |
|
|
* Each of the interrupts can be individually masked. This is
|
| 1096 |
|
|
* accomplished by setting the appropriate bit in the mask register.
|
| 1097 |
|
|
* A bit is set by writing a "1" to the desired position in the mask
|
| 1098 |
|
|
* register and cleared by writing a "0". There are 3 mask registers
|
| 1099 |
|
|
* located at ISA address 804h, 805h and 806h.
|
| 1100 |
|
|
*
|
| 1101 |
|
|
* An I/O read at ISA address 804h, 805h, 806h will return the
|
| 1102 |
|
|
* state of the 11 PCI interrupts and not the state of the MASKED
|
| 1103 |
|
|
* interrupts.
|
| 1104 |
|
|
*
|
| 1105 |
|
|
* Note: A write to I/O 804h, 805h, and 806h the mask register will be
|
| 1106 |
|
|
* updated.
|
| 1107 |
|
|
*
|
| 1108 |
|
|
*
|
| 1109 |
|
|
* ISA DATA<7:0>
|
| 1110 |
|
|
* ISA +--------------------------------------------------------------+
|
| 1111 |
|
|
* ADDRESS | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
| 1112 |
|
|
* +==============================================================+
|
| 1113 |
|
|
* 0x804 | INTB0 | USB | IDE | SIO | INTA3 |INTA2 | INTA1 | INTA0 |
|
| 1114 |
|
|
* +--------------------------------------------------------------+
|
| 1115 |
|
|
* 0x805 | INTD0 | INTC3 | INTC2 | INTC1 | INTC0 |INTB3 | INTB2 | INTB1 |
|
| 1116 |
|
|
* +--------------------------------------------------------------+
|
| 1117 |
|
|
* 0x806 | Rsrv | Rsrv | Rsrv | Rsrv | Rsrv |INTD3 | INTD2 | INTD1 |
|
| 1118 |
|
|
* +--------------------------------------------------------------+
|
| 1119 |
|
|
* * Rsrv = reserved bits
|
| 1120 |
|
|
* Note: The mask register is write-only.
|
| 1121 |
|
|
*
|
| 1122 |
|
|
* IdSel
|
| 1123 |
|
|
* 5 32 bit PCI option slot 2
|
| 1124 |
|
|
* 6 64 bit PCI option slot 0
|
| 1125 |
|
|
* 7 64 bit PCI option slot 1
|
| 1126 |
|
|
* 8 Saturn I/O
|
| 1127 |
|
|
* 9 32 bit PCI option slot 3
|
| 1128 |
|
|
* 10 USB
|
| 1129 |
|
|
* 11 IDE
|
| 1130 |
|
|
*
|
| 1131 |
|
|
*/
|
| 1132 |
|
|
|
| 1133 |
|
|
static inline void alphapc164_fixup(void)
|
| 1134 |
|
|
{
|
| 1135 |
|
|
extern void SMC93X_Init(void);
|
| 1136 |
|
|
char irq_tab[7][5] = {
|
| 1137 |
|
|
/*INT INTA INTB INTC INTD */
|
| 1138 |
|
|
{ 16+2, 16+2, 16+9, 16+13, 16+17}, /* IdSel 5, slot 2, J20 */
|
| 1139 |
|
|
{ 16+0, 16+0, 16+7, 16+11, 16+15}, /* IdSel 6, slot 0, J29 */
|
| 1140 |
|
|
{ 16+1, 16+1, 16+8, 16+12, 16+16}, /* IdSel 7, slot 1, J26 */
|
| 1141 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
|
| 1142 |
|
|
{ 16+3, 16+3, 16+10, 16+14, 16+18}, /* IdSel 9, slot 3, J19 */
|
| 1143 |
|
|
{ 16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 10, USB */
|
| 1144 |
|
|
{ 16+5, 16+5, 16+5, 16+5, 16+5} /* IdSel 11, IDE */
|
| 1145 |
|
|
};
|
| 1146 |
|
|
|
| 1147 |
|
|
common_fixup(5, 11, 5, irq_tab, 0);
|
| 1148 |
|
|
|
| 1149 |
|
|
SMC93X_Init();
|
| 1150 |
|
|
}
|
| 1151 |
|
|
|
| 1152 |
|
|
/*
|
| 1153 |
|
|
* The AlphaPC64 is very similar to the EB66+ except that its slots
|
| 1154 |
|
|
* are numbered differently. In the code below, I have used slot
|
| 1155 |
|
|
* number to refer to the id select line and *not* the slot number
|
| 1156 |
|
|
* used in the AlphaPC64 documentation. However, in the table, I've
|
| 1157 |
|
|
* given the slot number, the id select line and the Jxx number that's
|
| 1158 |
|
|
* printed on the board. The interrupt pins from the PCI slots are
|
| 1159 |
|
|
* wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806
|
| 1160 |
|
|
* ISA.
|
| 1161 |
|
|
*
|
| 1162 |
|
|
* In the table, -1 means don't assign an IRQ number. This is usually
|
| 1163 |
|
|
* because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
|
| 1164 |
|
|
*/
|
| 1165 |
|
|
static inline void cabriolet_fixup(void)
|
| 1166 |
|
|
{
|
| 1167 |
|
|
char irq_tab[5][5] = {
|
| 1168 |
|
|
/*INT INTA INTB INTC INTD */
|
| 1169 |
|
|
{ 16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 5, slot 2, J21 */
|
| 1170 |
|
|
{ 16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J19 */
|
| 1171 |
|
|
{ 16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J20 */
|
| 1172 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
|
| 1173 |
|
|
{ 16+3, 16+3, 16+8, 16+12, 16+16} /* IdSel 9, slot 3, J22 */
|
| 1174 |
|
|
};
|
| 1175 |
|
|
|
| 1176 |
|
|
common_fixup(5, 9, 5, irq_tab, 0x398);
|
| 1177 |
|
|
}
|
| 1178 |
|
|
|
| 1179 |
|
|
|
| 1180 |
|
|
/*
|
| 1181 |
|
|
* Fixup configuration for EB66/EB64+ boards.
|
| 1182 |
|
|
*
|
| 1183 |
|
|
* Both these boards use the same interrupt summary scheme. There are
|
| 1184 |
|
|
* two 8 bit external summary registers as follows:
|
| 1185 |
|
|
*
|
| 1186 |
|
|
* Summary @ 0x26:
|
| 1187 |
|
|
* Bit Meaning
|
| 1188 |
|
|
* 0 Interrupt Line A from slot 0
|
| 1189 |
|
|
* 1 Interrupt Line A from slot 1
|
| 1190 |
|
|
* 2 Interrupt Line B from slot 0
|
| 1191 |
|
|
* 3 Interrupt Line B from slot 1
|
| 1192 |
|
|
* 4 Interrupt Line C from slot 0
|
| 1193 |
|
|
* 5 Interrupt line from the two ISA PICs
|
| 1194 |
|
|
* 6 Tulip (slot
|
| 1195 |
|
|
* 7 NCR SCSI
|
| 1196 |
|
|
*
|
| 1197 |
|
|
* Summary @ 0x27
|
| 1198 |
|
|
* Bit Meaning
|
| 1199 |
|
|
* 0 Interrupt Line C from slot 1
|
| 1200 |
|
|
* 1 Interrupt Line D from slot 0
|
| 1201 |
|
|
* 2 Interrupt Line D from slot 1
|
| 1202 |
|
|
* 3 RAZ
|
| 1203 |
|
|
* 4 RAZ
|
| 1204 |
|
|
* 5 RAZ
|
| 1205 |
|
|
* 6 RAZ
|
| 1206 |
|
|
* 7 RAZ
|
| 1207 |
|
|
*
|
| 1208 |
|
|
* The device to slot mapping looks like:
|
| 1209 |
|
|
*
|
| 1210 |
|
|
* Slot Device
|
| 1211 |
|
|
* 5 NCR SCSI controller
|
| 1212 |
|
|
* 6 PCI on board slot 0
|
| 1213 |
|
|
* 7 PCI on board slot 1
|
| 1214 |
|
|
* 8 Intel SIO PCI-ISA bridge chip
|
| 1215 |
|
|
* 9 Tulip - DECchip 21040 ethernet controller
|
| 1216 |
|
|
*
|
| 1217 |
|
|
*
|
| 1218 |
|
|
* This two layered interrupt approach means that we allocate IRQ 16 and
|
| 1219 |
|
|
* above for PCI interrupts. The IRQ relates to which bit the interrupt
|
| 1220 |
|
|
* comes in on. This makes interrupt processing much easier.
|
| 1221 |
|
|
*/
|
| 1222 |
|
|
static inline void eb66_and_eb64p_fixup(void)
|
| 1223 |
|
|
{
|
| 1224 |
|
|
char irq_tab[5][5] = {
|
| 1225 |
|
|
/*INT INTA INTB INTC INTD */
|
| 1226 |
|
|
{16+7, 16+7, 16+7, 16+7, 16+7}, /* IdSel 5, slot ?, ?? */
|
| 1227 |
|
|
{16+0, 16+0, 16+2, 16+4, 16+9}, /* IdSel 6, slot ?, ?? */
|
| 1228 |
|
|
{16+1, 16+1, 16+3, 16+8, 16+10}, /* IdSel 7, slot ?, ?? */
|
| 1229 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
|
| 1230 |
|
|
{16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 9, TULIP */
|
| 1231 |
|
|
};
|
| 1232 |
|
|
common_fixup(5, 9, 5, irq_tab, 0);
|
| 1233 |
|
|
}
|
| 1234 |
|
|
|
| 1235 |
|
|
|
| 1236 |
|
|
/*
|
| 1237 |
|
|
* Fixup configuration for MIKASA
|
| 1238 |
|
|
*
|
| 1239 |
|
|
* Summary @ 0x536:
|
| 1240 |
|
|
* Bit Meaning
|
| 1241 |
|
|
* 0 Interrupt Line A from slot 0
|
| 1242 |
|
|
* 1 Interrupt Line B from slot 0
|
| 1243 |
|
|
* 2 Interrupt Line C from slot 0
|
| 1244 |
|
|
* 3 Interrupt Line D from slot 0
|
| 1245 |
|
|
* 4 Interrupt Line A from slot 1
|
| 1246 |
|
|
* 5 Interrupt line B from slot 1
|
| 1247 |
|
|
* 6 Interrupt Line C from slot 1
|
| 1248 |
|
|
* 7 Interrupt Line D from slot 1
|
| 1249 |
|
|
* 8 Interrupt Line A from slot 2
|
| 1250 |
|
|
* 9 Interrupt Line B from slot 2
|
| 1251 |
|
|
*10 Interrupt Line C from slot 2
|
| 1252 |
|
|
*11 Interrupt Line D from slot 2
|
| 1253 |
|
|
*12 NCR 810 SCSI
|
| 1254 |
|
|
*13 Power Supply Fail
|
| 1255 |
|
|
*14 Temperature Warn
|
| 1256 |
|
|
*15 Reserved
|
| 1257 |
|
|
*
|
| 1258 |
|
|
* The device to slot mapping looks like:
|
| 1259 |
|
|
*
|
| 1260 |
|
|
* Slot Device
|
| 1261 |
|
|
* 6 NCR SCSI controller
|
| 1262 |
|
|
* 7 Intel PCI-EISA bridge chip
|
| 1263 |
|
|
* 11 PCI on board slot 0
|
| 1264 |
|
|
* 12 PCI on board slot 1
|
| 1265 |
|
|
* 13 PCI on board slot 2
|
| 1266 |
|
|
*
|
| 1267 |
|
|
*
|
| 1268 |
|
|
* This two layered interrupt approach means that we allocate IRQ 16 and
|
| 1269 |
|
|
* above for PCI interrupts. The IRQ relates to which bit the interrupt
|
| 1270 |
|
|
* comes in on. This makes interrupt processing much easier.
|
| 1271 |
|
|
*/
|
| 1272 |
|
|
static inline void mikasa_fixup(void)
|
| 1273 |
|
|
{
|
| 1274 |
|
|
char irq_tab[8][5] = {
|
| 1275 |
|
|
/*INT INTA INTB INTC INTD */
|
| 1276 |
|
|
{16+12, 16+12, 16+12, 16+12, 16+12}, /* IdSel 17, SCSI */
|
| 1277 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 18, PCEB */
|
| 1278 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 19, ???? */
|
| 1279 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 20, ???? */
|
| 1280 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 21, ???? */
|
| 1281 |
|
|
{ 16+0, 16+0, 16+1, 16+2, 16+3}, /* IdSel 22, slot 0 */
|
| 1282 |
|
|
{ 16+4, 16+4, 16+5, 16+6, 16+7}, /* IdSel 23, slot 1 */
|
| 1283 |
|
|
{ 16+8, 16+8, 16+9, 16+10, 16+11}, /* IdSel 24, slot 2 */
|
| 1284 |
|
|
};
|
| 1285 |
|
|
common_fixup(6, 13, 5, irq_tab, 0);
|
| 1286 |
|
|
}
|
| 1287 |
|
|
|
| 1288 |
|
|
/*
|
| 1289 |
|
|
* Fixup configuration for NORITAKE
|
| 1290 |
|
|
*
|
| 1291 |
|
|
* Summary @ 0x542, summary register #1:
|
| 1292 |
|
|
* Bit Meaning
|
| 1293 |
|
|
* 0 All valid ints from summary regs 2 & 3
|
| 1294 |
|
|
* 1 QLOGIC ISP1020A SCSI
|
| 1295 |
|
|
* 2 Interrupt Line A from slot 0
|
| 1296 |
|
|
* 3 Interrupt Line B from slot 0
|
| 1297 |
|
|
* 4 Interrupt Line A from slot 1
|
| 1298 |
|
|
* 5 Interrupt line B from slot 1
|
| 1299 |
|
|
* 6 Interrupt Line A from slot 2
|
| 1300 |
|
|
* 7 Interrupt Line B from slot 2
|
| 1301 |
|
|
* 8 Interrupt Line A from slot 3
|
| 1302 |
|
|
* 9 Interrupt Line B from slot 3
|
| 1303 |
|
|
*10 Interrupt Line A from slot 4
|
| 1304 |
|
|
*11 Interrupt Line B from slot 4
|
| 1305 |
|
|
*12 Interrupt Line A from slot 5
|
| 1306 |
|
|
*13 Interrupt Line B from slot 5
|
| 1307 |
|
|
*14 Interrupt Line A from slot 6
|
| 1308 |
|
|
*15 Interrupt Line B from slot 6
|
| 1309 |
|
|
*
|
| 1310 |
|
|
* Summary @ 0x544, summary register #2:
|
| 1311 |
|
|
* Bit Meaning
|
| 1312 |
|
|
* 0 OR of all unmasked ints in SR #2
|
| 1313 |
|
|
* 1 OR of secondary bus ints
|
| 1314 |
|
|
* 2 Interrupt Line C from slot 0
|
| 1315 |
|
|
* 3 Interrupt Line D from slot 0
|
| 1316 |
|
|
* 4 Interrupt Line C from slot 1
|
| 1317 |
|
|
* 5 Interrupt line D from slot 1
|
| 1318 |
|
|
* 6 Interrupt Line C from slot 2
|
| 1319 |
|
|
* 7 Interrupt Line D from slot 2
|
| 1320 |
|
|
* 8 Interrupt Line C from slot 3
|
| 1321 |
|
|
* 9 Interrupt Line D from slot 3
|
| 1322 |
|
|
*10 Interrupt Line C from slot 4
|
| 1323 |
|
|
*11 Interrupt Line D from slot 4
|
| 1324 |
|
|
*12 Interrupt Line C from slot 5
|
| 1325 |
|
|
*13 Interrupt Line D from slot 5
|
| 1326 |
|
|
*14 Interrupt Line C from slot 6
|
| 1327 |
|
|
*15 Interrupt Line D from slot 6
|
| 1328 |
|
|
*
|
| 1329 |
|
|
* The device to slot mapping looks like:
|
| 1330 |
|
|
*
|
| 1331 |
|
|
* Slot Device
|
| 1332 |
|
|
* 7 Intel PCI-EISA bridge chip
|
| 1333 |
|
|
* 8 DEC PCI-PCI bridge chip
|
| 1334 |
|
|
* 11 PCI on board slot 0
|
| 1335 |
|
|
* 12 PCI on board slot 1
|
| 1336 |
|
|
* 13 PCI on board slot 2
|
| 1337 |
|
|
*
|
| 1338 |
|
|
*
|
| 1339 |
|
|
* This two layered interrupt approach means that we allocate IRQ 16 and
|
| 1340 |
|
|
* above for PCI interrupts. The IRQ relates to which bit the interrupt
|
| 1341 |
|
|
* comes in on. This makes interrupt processing much easier.
|
| 1342 |
|
|
*/
|
| 1343 |
|
|
static inline void noritake_fixup(void)
|
| 1344 |
|
|
{
|
| 1345 |
|
|
char irq_tab[15][5] = {
|
| 1346 |
|
|
/*INT INTA INTB INTC INTD */
|
| 1347 |
|
|
/* note: IDSELs 16, 17, and 25 are CORELLE only */
|
| 1348 |
|
|
{ 16+1, 16+1, 16+1, 16+1, 16+1}, /* IdSel 16, QLOGIC */
|
| 1349 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 17, S3 Trio64 */
|
| 1350 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 18, PCEB */
|
| 1351 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 19, PPB */
|
| 1352 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 20, ???? */
|
| 1353 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 21, ???? */
|
| 1354 |
|
|
{ 16+2, 16+2, 16+3, 32+2, 32+3}, /* IdSel 22, slot 0 */
|
| 1355 |
|
|
{ 16+4, 16+4, 16+5, 32+4, 32+5}, /* IdSel 23, slot 1 */
|
| 1356 |
|
|
{ 16+6, 16+6, 16+7, 32+6, 32+7}, /* IdSel 24, slot 2 */
|
| 1357 |
|
|
{ 16+8, 16+8, 16+9, 32+8, 32+9}, /* IdSel 25, slot 3 */
|
| 1358 |
|
|
/* the following 5 are actually on PCI bus 1, across the bridge */
|
| 1359 |
|
|
{ 16+1, 16+1, 16+1, 16+1, 16+1}, /* IdSel 16, QLOGIC */
|
| 1360 |
|
|
{ 16+8, 16+8, 16+9, 32+8, 32+9}, /* IdSel 17, slot 3 */
|
| 1361 |
|
|
{16+10, 16+10, 16+11, 32+10, 32+11}, /* IdSel 18, slot 4 */
|
| 1362 |
|
|
{16+12, 16+12, 16+13, 32+12, 32+13}, /* IdSel 19, slot 5 */
|
| 1363 |
|
|
{16+14, 16+14, 16+15, 32+14, 32+15}, /* IdSel 20, slot 6 */
|
| 1364 |
|
|
};
|
| 1365 |
|
|
common_fixup(5, 19, 5, irq_tab, 0);
|
| 1366 |
|
|
}
|
| 1367 |
|
|
|
| 1368 |
|
|
/*
|
| 1369 |
|
|
* Fixup configuration for ALCOR
|
| 1370 |
|
|
*
|
| 1371 |
|
|
* Summary @ GRU_INT_REQ:
|
| 1372 |
|
|
* Bit Meaning
|
| 1373 |
|
|
* 0 Interrupt Line A from slot 2
|
| 1374 |
|
|
* 1 Interrupt Line B from slot 2
|
| 1375 |
|
|
* 2 Interrupt Line C from slot 2
|
| 1376 |
|
|
* 3 Interrupt Line D from slot 2
|
| 1377 |
|
|
* 4 Interrupt Line A from slot 1
|
| 1378 |
|
|
* 5 Interrupt line B from slot 1
|
| 1379 |
|
|
* 6 Interrupt Line C from slot 1
|
| 1380 |
|
|
* 7 Interrupt Line D from slot 1
|
| 1381 |
|
|
* 8 Interrupt Line A from slot 0
|
| 1382 |
|
|
* 9 Interrupt Line B from slot 0
|
| 1383 |
|
|
*10 Interrupt Line C from slot 0
|
| 1384 |
|
|
*11 Interrupt Line D from slot 0
|
| 1385 |
|
|
*12 Interrupt Line A from slot 4
|
| 1386 |
|
|
*13 Interrupt Line B from slot 4
|
| 1387 |
|
|
*14 Interrupt Line C from slot 4
|
| 1388 |
|
|
*15 Interrupt Line D from slot 4
|
| 1389 |
|
|
*16 Interrupt Line D from slot 3
|
| 1390 |
|
|
*17 Interrupt Line D from slot 3
|
| 1391 |
|
|
*18 Interrupt Line D from slot 3
|
| 1392 |
|
|
*19 Interrupt Line D from slot 3
|
| 1393 |
|
|
*20-30 Reserved
|
| 1394 |
|
|
*31 EISA interrupt
|
| 1395 |
|
|
*
|
| 1396 |
|
|
* The device to slot mapping looks like:
|
| 1397 |
|
|
*
|
| 1398 |
|
|
* Slot Device
|
| 1399 |
|
|
* 7 PCI on board slot 0
|
| 1400 |
|
|
* 8 PCI on board slot 3
|
| 1401 |
|
|
* 9 PCI on board slot 4
|
| 1402 |
|
|
* 10 PCEB (PCI-EISA bridge)
|
| 1403 |
|
|
* 11 PCI on board slot 2
|
| 1404 |
|
|
* 12 PCI on board slot 1
|
| 1405 |
|
|
*
|
| 1406 |
|
|
*
|
| 1407 |
|
|
* This two layered interrupt approach means that we allocate IRQ 16 and
|
| 1408 |
|
|
* above for PCI interrupts. The IRQ relates to which bit the interrupt
|
| 1409 |
|
|
* comes in on. This makes interrupt processing much easier.
|
| 1410 |
|
|
*/
|
| 1411 |
|
|
static inline void alcor_fixup(void)
|
| 1412 |
|
|
{
|
| 1413 |
|
|
char irq_tab[7][5] = {
|
| 1414 |
|
|
/*INT INTA INTB INTC INTD */
|
| 1415 |
|
|
/* note: IDSEL 17 is XLT only */
|
| 1416 |
|
|
{16+13, 16+13, 16+13, 16+13, 16+13}, /* IdSel 17, TULIP */
|
| 1417 |
|
|
{ 16+8, 16+8, 16+9, 16+10, 16+11}, /* IdSel 18, slot 0 */
|
| 1418 |
|
|
{16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 19, slot 3 */
|
| 1419 |
|
|
{16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 20, slot 4 */
|
| 1420 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 21, PCEB */
|
| 1421 |
|
|
{ 16+0, 16+0, 16+1, 16+2, 16+3}, /* IdSel 22, slot 2 */
|
| 1422 |
|
|
{ 16+4, 16+4, 16+5, 16+6, 16+7}, /* IdSel 23, slot 1 */
|
| 1423 |
|
|
};
|
| 1424 |
|
|
common_fixup(6, 12, 5, irq_tab, 0);
|
| 1425 |
|
|
}
|
| 1426 |
|
|
|
| 1427 |
|
|
#if 0
|
| 1428 |
|
|
/*
|
| 1429 |
|
|
* Fixup configuration for ALPHA XLT (EV5/EV56)
|
| 1430 |
|
|
*
|
| 1431 |
|
|
* Summary @ GRU_INT_REQ:
|
| 1432 |
|
|
* Bit Meaning
|
| 1433 |
|
|
* 0 Interrupt Line A from slot 2
|
| 1434 |
|
|
* 1 Interrupt Line B from slot 2
|
| 1435 |
|
|
* 2 Interrupt Line C from slot 2
|
| 1436 |
|
|
* 3 Interrupt Line D from slot 2
|
| 1437 |
|
|
* 4 Interrupt Line A from slot 1
|
| 1438 |
|
|
* 5 Interrupt line B from slot 1
|
| 1439 |
|
|
* 6 Interrupt Line C from slot 1
|
| 1440 |
|
|
* 7 Interrupt Line D from slot 1
|
| 1441 |
|
|
* 8 Interrupt Line A from slot 0
|
| 1442 |
|
|
* 9 Interrupt Line B from slot 0
|
| 1443 |
|
|
*10 Interrupt Line C from slot 0
|
| 1444 |
|
|
*11 Interrupt Line D from slot 0
|
| 1445 |
|
|
*12 NCR810 SCSI in slot 9
|
| 1446 |
|
|
*13 DC-21040 (TULIP) in slot 6
|
| 1447 |
|
|
*14-19 Reserved
|
| 1448 |
|
|
*20-23 Jumpers (interrupt)
|
| 1449 |
|
|
*24-27 Module revision
|
| 1450 |
|
|
*28-30 Reserved
|
| 1451 |
|
|
*31 EISA interrupt
|
| 1452 |
|
|
*
|
| 1453 |
|
|
* The device to slot mapping looks like:
|
| 1454 |
|
|
*
|
| 1455 |
|
|
* Slot Device
|
| 1456 |
|
|
* 6 TULIP
|
| 1457 |
|
|
* 7 PCI on board slot 0
|
| 1458 |
|
|
* 8 none
|
| 1459 |
|
|
* 9 SCSI
|
| 1460 |
|
|
* 10 PCI-ISA bridge
|
| 1461 |
|
|
* 11 PCI on board slot 2
|
| 1462 |
|
|
* 12 PCI on board slot 1
|
| 1463 |
|
|
*
|
| 1464 |
|
|
*
|
| 1465 |
|
|
* This two layered interrupt approach means that we allocate IRQ 16 and
|
| 1466 |
|
|
* above for PCI interrupts. The IRQ relates to which bit the interrupt
|
| 1467 |
|
|
* comes in on. This makes interrupt processing much easier.
|
| 1468 |
|
|
*/
|
| 1469 |
|
|
static inline void xlt_fixup(void)
|
| 1470 |
|
|
{
|
| 1471 |
|
|
char irq_tab[7][5] = {
|
| 1472 |
|
|
/*INT INTA INTB INTC INTD */
|
| 1473 |
|
|
{16+13, 16+13, 16+13, 16+13, 16+13}, /* IdSel 17, TULIP */
|
| 1474 |
|
|
{ 16+8, 16+8, 16+9, 16+10, 16+11}, /* IdSel 18, slot 0 */
|
| 1475 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 19, none */
|
| 1476 |
|
|
{16+12, 16+12, 16+12, 16+12, 16+12}, /* IdSel 20, SCSI */
|
| 1477 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 21, SIO */
|
| 1478 |
|
|
{ 16+0, 16+0, 16+1, 16+2, 16+3}, /* IdSel 22, slot 2 */
|
| 1479 |
|
|
{ 16+4, 16+4, 16+5, 16+6, 16+7}, /* IdSel 23, slot 1 */
|
| 1480 |
|
|
};
|
| 1481 |
|
|
common_fixup(6, 12, 5, irq_tab, 0);
|
| 1482 |
|
|
}
|
| 1483 |
|
|
#endif /* 0 */
|
| 1484 |
|
|
|
| 1485 |
|
|
/*
|
| 1486 |
|
|
* Fixup configuration for ALPHA SABLE (2100) - 2100A is different ??
|
| 1487 |
|
|
*
|
| 1488 |
|
|
* Summary Registers (536/53a/53c):
|
| 1489 |
|
|
* Bit Meaning
|
| 1490 |
|
|
*-----------------
|
| 1491 |
|
|
* 0 PCI slot 0
|
| 1492 |
|
|
* 1 NCR810 (builtin)
|
| 1493 |
|
|
* 2 TULIP (builtin)
|
| 1494 |
|
|
* 3 mouse
|
| 1495 |
|
|
* 4 PCI slot 1
|
| 1496 |
|
|
* 5 PCI slot 2
|
| 1497 |
|
|
* 6 keyboard
|
| 1498 |
|
|
* 7 floppy
|
| 1499 |
|
|
* 8 COM2
|
| 1500 |
|
|
* 9 parallel port
|
| 1501 |
|
|
*10 EISA irq 3
|
| 1502 |
|
|
*11 EISA irq 4
|
| 1503 |
|
|
*12 EISA irq 5
|
| 1504 |
|
|
*13 EISA irq 6
|
| 1505 |
|
|
*14 EISA irq 7
|
| 1506 |
|
|
*15 COM1
|
| 1507 |
|
|
*16 EISA irq 9
|
| 1508 |
|
|
*17 EISA irq 10
|
| 1509 |
|
|
*18 EISA irq 11
|
| 1510 |
|
|
*19 EISA irq 12
|
| 1511 |
|
|
*20 EISA irq 13
|
| 1512 |
|
|
*21 EISA irq 14
|
| 1513 |
|
|
*22 NC
|
| 1514 |
|
|
*23 IIC
|
| 1515 |
|
|
*
|
| 1516 |
|
|
* The device to slot mapping looks like:
|
| 1517 |
|
|
*
|
| 1518 |
|
|
* Slot Device
|
| 1519 |
|
|
* 0 TULIP
|
| 1520 |
|
|
* 1 SCSI
|
| 1521 |
|
|
* 2 PCI-EISA bridge
|
| 1522 |
|
|
* 3 none
|
| 1523 |
|
|
* 4 none
|
| 1524 |
|
|
* 5 none
|
| 1525 |
|
|
* 6 PCI on board slot 0
|
| 1526 |
|
|
* 7 PCI on board slot 1
|
| 1527 |
|
|
* 8 PCI on board slot 2
|
| 1528 |
|
|
*
|
| 1529 |
|
|
*
|
| 1530 |
|
|
* This two layered interrupt approach means that we allocate IRQ 16 and
|
| 1531 |
|
|
* above for PCI interrupts. The IRQ relates to which bit the interrupt
|
| 1532 |
|
|
* comes in on. This makes interrupt processing much easier.
|
| 1533 |
|
|
*/
|
| 1534 |
|
|
/* NOTE: the IRQ assignments below are arbitrary, but need to be consistent
|
| 1535 |
|
|
with the values in the sable_irq_to_mask[] and sable_mask_to_irq[] tables
|
| 1536 |
|
|
in irq.c
|
| 1537 |
|
|
*/
|
| 1538 |
|
|
static inline void sable_fixup(void)
|
| 1539 |
|
|
{
|
| 1540 |
|
|
char irq_tab[9][5] = {
|
| 1541 |
|
|
/*INT INTA INTB INTC INTD */
|
| 1542 |
|
|
{ 32+0, 32+0, 32+0, 32+0, 32+0}, /* IdSel 0, TULIP */
|
| 1543 |
|
|
{ 32+1, 32+1, 32+1, 32+1, 32+1}, /* IdSel 1, SCSI */
|
| 1544 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 2, SIO */
|
| 1545 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 3, none */
|
| 1546 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 4, none */
|
| 1547 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 5, none */
|
| 1548 |
|
|
{ 32+2, 32+2, 32+2, 32+2, 32+2}, /* IdSel 6, slot 0 */
|
| 1549 |
|
|
{ 32+3, 32+3, 32+3, 32+3, 32+3}, /* IdSel 7, slot 1 */
|
| 1550 |
|
|
{ 32+4, 32+4, 32+4, 32+4, 32+4}, /* IdSel 8, slot 2 */
|
| 1551 |
|
|
};
|
| 1552 |
|
|
common_fixup(0, 8, 5, irq_tab, 0);
|
| 1553 |
|
|
}
|
| 1554 |
|
|
|
| 1555 |
|
|
/*
|
| 1556 |
|
|
* Fixup configuration for MIATA (EV56+PYXIS)
|
| 1557 |
|
|
*
|
| 1558 |
|
|
* Summary @ PYXIS_INT_REQ:
|
| 1559 |
|
|
* Bit Meaning
|
| 1560 |
|
|
* 0 Fan Fault
|
| 1561 |
|
|
* 1 NMI
|
| 1562 |
|
|
* 2 Halt/Reset switch
|
| 1563 |
|
|
* 3 none
|
| 1564 |
|
|
* 4 CID0 (Riser ID)
|
| 1565 |
|
|
* 5 CID1 (Riser ID)
|
| 1566 |
|
|
* 6 Interval timer
|
| 1567 |
|
|
* 7 PCI-ISA Bridge
|
| 1568 |
|
|
* 8 Ethernet
|
| 1569 |
|
|
* 9 EIDE (deprecated, ISA 14/15 used)
|
| 1570 |
|
|
*10 none
|
| 1571 |
|
|
*11 USB
|
| 1572 |
|
|
*12 Interrupt Line A from slot 4
|
| 1573 |
|
|
*13 Interrupt Line B from slot 4
|
| 1574 |
|
|
*14 Interrupt Line C from slot 4
|
| 1575 |
|
|
*15 Interrupt Line D from slot 4
|
| 1576 |
|
|
*16 Interrupt Line A from slot 5
|
| 1577 |
|
|
*17 Interrupt line B from slot 5
|
| 1578 |
|
|
*18 Interrupt Line C from slot 5
|
| 1579 |
|
|
*19 Interrupt Line D from slot 5
|
| 1580 |
|
|
*20 Interrupt Line A from slot 1
|
| 1581 |
|
|
*21 Interrupt Line B from slot 1
|
| 1582 |
|
|
*22 Interrupt Line C from slot 1
|
| 1583 |
|
|
*23 Interrupt Line D from slot 1
|
| 1584 |
|
|
*24 Interrupt Line A from slot 2
|
| 1585 |
|
|
*25 Interrupt Line B from slot 2
|
| 1586 |
|
|
*26 Interrupt Line C from slot 2
|
| 1587 |
|
|
*27 Interrupt Line D from slot 2
|
| 1588 |
|
|
*27 Interrupt Line A from slot 3
|
| 1589 |
|
|
*29 Interrupt Line B from slot 3
|
| 1590 |
|
|
*30 Interrupt Line C from slot 3
|
| 1591 |
|
|
*31 Interrupt Line D from slot 3
|
| 1592 |
|
|
*
|
| 1593 |
|
|
* The device to slot mapping looks like:
|
| 1594 |
|
|
*
|
| 1595 |
|
|
* Slot Device
|
| 1596 |
|
|
* 3 DC21142 Ethernet
|
| 1597 |
|
|
* 4 EIDE CMD646
|
| 1598 |
|
|
* 5 none
|
| 1599 |
|
|
* 6 USB
|
| 1600 |
|
|
* 7 PCI-ISA bridge
|
| 1601 |
|
|
* 8 PCI-PCI Bridge (SBU Riser)
|
| 1602 |
|
|
* 9 none
|
| 1603 |
|
|
* 10 none
|
| 1604 |
|
|
* 11 PCI on board slot 4 (SBU Riser)
|
| 1605 |
|
|
* 12 PCI on board slot 5 (SBU Riser)
|
| 1606 |
|
|
*
|
| 1607 |
|
|
* These are behind the bridge, so I'm not sure what to do...
|
| 1608 |
|
|
*
|
| 1609 |
|
|
* 13 PCI on board slot 1 (SBU Riser)
|
| 1610 |
|
|
* 14 PCI on board slot 2 (SBU Riser)
|
| 1611 |
|
|
* 15 PCI on board slot 3 (SBU Riser)
|
| 1612 |
|
|
*
|
| 1613 |
|
|
*
|
| 1614 |
|
|
* This two layered interrupt approach means that we allocate IRQ 16 and
|
| 1615 |
|
|
* above for PCI interrupts. The IRQ relates to which bit the interrupt
|
| 1616 |
|
|
* comes in on. This makes interrupt processing much easier.
|
| 1617 |
|
|
*/
|
| 1618 |
|
|
static inline void miata_fixup(void)
|
| 1619 |
|
|
{
|
| 1620 |
|
|
extern int es1888_init(void);
|
| 1621 |
|
|
extern void SMC669_Init(void); /* might be a MiataGL */
|
| 1622 |
|
|
char irq_tab[18][5] = {
|
| 1623 |
|
|
/*INT INTA INTB INTC INTD */
|
| 1624 |
|
|
{16+ 8, 16+ 8, 16+ 8, 16+ 8, 16+ 8}, /* IdSel 14, DC21142/3 */
|
| 1625 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 15, EIDE */
|
| 1626 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 16, none */
|
| 1627 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 17, none */
|
| 1628 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 18, PCI-ISA */
|
| 1629 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 19, PCI-PCI old */
|
| 1630 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 20, none */
|
| 1631 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 21, none */
|
| 1632 |
|
|
{16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 22, slot 4 */
|
| 1633 |
|
|
{16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 23, slot 5 */
|
| 1634 |
|
|
/* the following 7 are actually on PCI bus 1, across the bridge */
|
| 1635 |
|
|
{16+11, 16+11, 16+11, 16+11, 16+11}, /* IdSel 24, QLISP on GL */
|
| 1636 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 25, none */
|
| 1637 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 26, none */
|
| 1638 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 27, none */
|
| 1639 |
|
|
{16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 28, slot 1 */
|
| 1640 |
|
|
{16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 29, slot 2 */
|
| 1641 |
|
|
{16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 30, slot 3 */
|
| 1642 |
|
|
/* this bridge is on the main bus of the later original MIATA */
|
| 1643 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 31, PCI-PCI new */
|
| 1644 |
|
|
};
|
| 1645 |
|
|
common_fixup(3, 20, 5, irq_tab, 0);
|
| 1646 |
|
|
SMC669_Init(); /* might be a MiataGL, so try to find one of these */
|
| 1647 |
|
|
es1888_init();
|
| 1648 |
|
|
}
|
| 1649 |
|
|
|
| 1650 |
|
|
/*
|
| 1651 |
|
|
* Fixup configuration for SX164 (PCA56+PYXIS)
|
| 1652 |
|
|
*
|
| 1653 |
|
|
* Summary @ PYXIS_INT_REQ:
|
| 1654 |
|
|
* Bit Meaning
|
| 1655 |
|
|
* 0 RSVD
|
| 1656 |
|
|
* 1 NMI
|
| 1657 |
|
|
* 2 Halt/Reset switch
|
| 1658 |
|
|
* 3 MBZ
|
| 1659 |
|
|
* 4 RAZ
|
| 1660 |
|
|
* 5 RAZ
|
| 1661 |
|
|
* 6 Interval timer (RTC)
|
| 1662 |
|
|
* 7 PCI-ISA Bridge
|
| 1663 |
|
|
* 8 Interrupt Line A from slot 3
|
| 1664 |
|
|
* 9 Interrupt Line A from slot 2
|
| 1665 |
|
|
*10 Interrupt Line A from slot 1
|
| 1666 |
|
|
*11 Interrupt Line A from slot 0
|
| 1667 |
|
|
*12 Interrupt Line B from slot 3
|
| 1668 |
|
|
*13 Interrupt Line B from slot 2
|
| 1669 |
|
|
*14 Interrupt Line B from slot 1
|
| 1670 |
|
|
*15 Interrupt line B from slot 0
|
| 1671 |
|
|
*16 Interrupt Line C from slot 3
|
| 1672 |
|
|
*17 Interrupt Line C from slot 2
|
| 1673 |
|
|
*18 Interrupt Line C from slot 1
|
| 1674 |
|
|
*19 Interrupt Line C from slot 0
|
| 1675 |
|
|
*20 Interrupt Line D from slot 3
|
| 1676 |
|
|
*21 Interrupt Line D from slot 2
|
| 1677 |
|
|
*22 Interrupt Line D from slot 1
|
| 1678 |
|
|
*23 Interrupt Line D from slot 0
|
| 1679 |
|
|
*
|
| 1680 |
|
|
* IdSel
|
| 1681 |
|
|
* 5 32 bit PCI option slot 2
|
| 1682 |
|
|
* 6 64 bit PCI option slot 0
|
| 1683 |
|
|
* 7 64 bit PCI option slot 1
|
| 1684 |
|
|
* 8 Cypress I/O
|
| 1685 |
|
|
* 9 32 bit PCI option slot 3
|
| 1686 |
|
|
*
|
| 1687 |
|
|
*/
|
| 1688 |
|
|
|
| 1689 |
|
|
static inline void sx164_fixup(void)
|
| 1690 |
|
|
{
|
| 1691 |
|
|
extern void SMC669_Init(void);
|
| 1692 |
|
|
char irq_tab[5][5] = {
|
| 1693 |
|
|
/*INT INTA INTB INTC INTD */
|
| 1694 |
|
|
{ 16+ 9, 16+ 9, 16+13, 16+17, 16+21}, /* IdSel 5 slot 2 J17 */
|
| 1695 |
|
|
{ 16+11, 16+11, 16+15, 16+19, 16+23}, /* IdSel 6 slot 0 J19 */
|
| 1696 |
|
|
{ 16+10, 16+10, 16+14, 16+18, 16+22}, /* IdSel 7 slot 1 J18 */
|
| 1697 |
|
|
{ -1, -1, -1, -1, -1}, /* IdSel 8 SIO */
|
| 1698 |
|
|
{ 16+ 8, 16+ 8, 16+12, 16+16, 16+20} /* IdSel 9 slot 3 J15 */
|
| 1699 |
|
|
};
|
| 1700 |
|
|
|
| 1701 |
|
|
common_fixup(5, 9, 5, irq_tab, 0);
|
| 1702 |
|
|
|
| 1703 |
|
|
SMC669_Init();
|
| 1704 |
|
|
}
|
| 1705 |
|
|
|
| 1706 |
|
|
static inline void ruffian_fixup(void)
|
| 1707 |
|
|
{
|
| 1708 |
|
|
struct pci_dev *dev;
|
| 1709 |
|
|
|
| 1710 |
|
|
/*
|
| 1711 |
|
|
* Go through all devices
|
| 1712 |
|
|
*/
|
| 1713 |
|
|
for (dev = pci_devices; dev; dev = dev->next) {
|
| 1714 |
|
|
if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
|
| 1715 |
|
|
/*
|
| 1716 |
|
|
* if it's a VGA, enable its BIOS ROM at C0000
|
| 1717 |
|
|
*/
|
| 1718 |
|
|
if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
|
| 1719 |
|
|
/* but if its a Cirrus 543x/544x DISABLE it, */
|
| 1720 |
|
|
/* since enabling ROM disables the memory... */
|
| 1721 |
|
|
if ((dev->vendor == PCI_VENDOR_ID_CIRRUS) &&
|
| 1722 |
|
|
(dev->device >= 0x00a0) &&
|
| 1723 |
|
|
(dev->device <= 0x00ac)) {
|
| 1724 |
|
|
pcibios_write_config_dword(
|
| 1725 |
|
|
dev->bus->number,
|
| 1726 |
|
|
dev->devfn,
|
| 1727 |
|
|
PCI_ROM_ADDRESS,
|
| 1728 |
|
|
0x00000000);
|
| 1729 |
|
|
} else {
|
| 1730 |
|
|
pcibios_write_config_dword(
|
| 1731 |
|
|
dev->bus->number,
|
| 1732 |
|
|
dev->devfn,
|
| 1733 |
|
|
PCI_ROM_ADDRESS,
|
| 1734 |
|
|
0x000c0000 | PCI_ROM_ADDRESS_ENABLE);
|
| 1735 |
|
|
}
|
| 1736 |
|
|
}
|
| 1737 |
|
|
/*
|
| 1738 |
|
|
* if it's a SCSI, disable its BIOS ROM
|
| 1739 |
|
|
*/
|
| 1740 |
|
|
if ((dev->class >> 8) == PCI_CLASS_STORAGE_SCSI) {
|
| 1741 |
|
|
pcibios_write_config_dword(dev->bus->number,
|
| 1742 |
|
|
dev->devfn,
|
| 1743 |
|
|
PCI_ROM_ADDRESS,
|
| 1744 |
|
|
0x0000000);
|
| 1745 |
|
|
}
|
| 1746 |
|
|
}
|
| 1747 |
|
|
}
|
| 1748 |
|
|
}
|
| 1749 |
|
|
|
| 1750 |
|
|
/*
|
| 1751 |
|
|
* The Takara has PCI devices 1, 2, and 3 configured to slots 20,
|
| 1752 |
|
|
* 19, and 18 respectively, in the default configuration. They can
|
| 1753 |
|
|
* also be jumpered to slots 8, 7, and 6 respectively, which is fun
|
| 1754 |
|
|
* because the SIO ISA bridge can also be slot 7. However, the SIO
|
| 1755 |
|
|
* doesn't explicitly generate PCI-type interrupts, so we can
|
| 1756 |
|
|
* assign it whatever the hell IRQ we like and it doesn't matter.
|
| 1757 |
|
|
*/
|
| 1758 |
|
|
static inline void takara_fixup(void)
|
| 1759 |
|
|
{
|
| 1760 |
|
|
char irq_tab[15][5] = {
|
| 1761 |
|
|
{ 16+3, 16+3, 16+3, 16+3, 16+3}, /* slot 6 == device 3 */
|
| 1762 |
|
|
{ 16+2, 16+2, 16+2, 16+2, 16+2}, /* slot 7 == device 2 */
|
| 1763 |
|
|
{ 16+1, 16+1, 16+1, 16+1, 16+1}, /* slot 8 == device 1 */
|
| 1764 |
|
|
{ -1, -1, -1, -1, -1}, /* slot 9 == nothing */
|
| 1765 |
|
|
{ -1, -1, -1, -1, -1}, /* slot 10 == nothing */
|
| 1766 |
|
|
{ -1, -1, -1, -1, -1}, /* slot 11 == nothing */
|
| 1767 |
|
|
{ -1, -1, -1, -1, -1}, /* slot 12 == nothing */
|
| 1768 |
|
|
{ -1, -1, -1, -1, -1}, /* slot 13 == nothing */
|
| 1769 |
|
|
{ -1, -1, -1, -1, -1}, /* slot 14 == nothing */
|
| 1770 |
|
|
{ -1, -1, -1, -1, -1}, /* slot 15 == nothing */
|
| 1771 |
|
|
{ -1, -1, -1, -1, -1}, /* slot 16 == nothing */
|
| 1772 |
|
|
{ -1, -1, -1, -1, -1}, /* slot 17 == nothing */
|
| 1773 |
|
|
{ 16+3, 16+3, 16+3, 16+3, 16+3}, /* slot 18 == device 3 */
|
| 1774 |
|
|
{ 16+2, 16+2, 16+2, 16+2, 16+2}, /* slot 19 == device 2 */
|
| 1775 |
|
|
{ 16+1, 16+1, 16+1, 16+1, 16+1}, /* slot 20 == device 1 */
|
| 1776 |
|
|
};
|
| 1777 |
|
|
|
| 1778 |
|
|
common_fixup(6, 20, 5, irq_tab, 0x26e);
|
| 1779 |
|
|
}
|
| 1780 |
|
|
|
| 1781 |
|
|
/*
|
| 1782 |
|
|
* Fixup configuration for all boards that route the PCI interrupts
|
| 1783 |
|
|
* through the SIO PCI/ISA bridge. This includes Noname (AXPpci33),
|
| 1784 |
|
|
* Avanti (AlphaStation) and Kenetics's Platform 2000.
|
| 1785 |
|
|
*/
|
| 1786 |
|
|
static inline void sio_fixup(void)
|
| 1787 |
|
|
{
|
| 1788 |
|
|
struct pci_dev *dev;
|
| 1789 |
|
|
/*
|
| 1790 |
|
|
* The Noname board has 5 PCI slots with each of the 4
|
| 1791 |
|
|
* interrupt pins routed to different pins on the PCI/ISA
|
| 1792 |
|
|
* bridge (PIRQ0-PIRQ3). The table below is based on
|
| 1793 |
|
|
* information available at:
|
| 1794 |
|
|
*
|
| 1795 |
|
|
* http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
|
| 1796 |
|
|
*
|
| 1797 |
|
|
* I have no information on the Avanti interrupt routing, but
|
| 1798 |
|
|
* the routing seems to be identical to the Noname except
|
| 1799 |
|
|
* that the Avanti has an additional slot whose routing I'm
|
| 1800 |
|
|
* unsure of.
|
| 1801 |
|
|
*
|
| 1802 |
|
|
* pirq_tab[0] is a fake entry to deal with old PCI boards
|
| 1803 |
|
|
* that have the interrupt pin number hardwired to 0 (meaning
|
| 1804 |
|
|
* that they use the default INTA line, if they are interrupt
|
| 1805 |
|
|
* driven at all).
|
| 1806 |
|
|
*/
|
| 1807 |
|
|
static const char pirq_tab[][5] = {
|
| 1808 |
|
|
#ifdef CONFIG_ALPHA_P2K
|
| 1809 |
|
|
{ 0, 0, -1, -1, -1}, /* idsel 6 (53c810) */
|
| 1810 |
|
|
{-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
|
| 1811 |
|
|
{ 1, 1, 2, 3, 0}, /* idsel 8 (slot A) */
|
| 1812 |
|
|
{ 2, 2, 3, 0, 1}, /* idsel 9 (slot B) */
|
| 1813 |
|
|
{-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
|
| 1814 |
|
|
{-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
|
| 1815 |
|
|
{ 3, 3, -1, -1, -1}, /* idsel 12 (CMD0646) */
|
| 1816 |
|
|
#else
|
| 1817 |
|
|
{ 3, 3, 3, 3, 3}, /* idsel 6 (53c810) */
|
| 1818 |
|
|
{-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
|
| 1819 |
|
|
{ 2, 2, -1, -1, -1}, /* idsel 8 (Noname hack: slot closest to ISA) */
|
| 1820 |
|
|
{-1, -1, -1, -1, -1}, /* idsel 9 (unused) */
|
| 1821 |
|
|
{-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
|
| 1822 |
|
|
{ 0, 0, 2, 1, 0}, /* idsel 11 KN25_PCI_SLOT0 */
|
| 1823 |
|
|
{ 1, 1, 0, 2, 1}, /* idsel 12 KN25_PCI_SLOT1 */
|
| 1824 |
|
|
{ 2, 2, 1, 0, 2}, /* idsel 13 KN25_PCI_SLOT2 */
|
| 1825 |
|
|
{ 0, 0, 0, 0, 0}, /* idsel 14 AS255 TULIP */
|
| 1826 |
|
|
#endif
|
| 1827 |
|
|
};
|
| 1828 |
|
|
/*
|
| 1829 |
|
|
* route_tab selects irq routing in PCI/ISA bridge so that:
|
| 1830 |
|
|
* PIRQ0 -> irq 15
|
| 1831 |
|
|
* PIRQ1 -> irq 9
|
| 1832 |
|
|
* PIRQ2 -> irq 10
|
| 1833 |
|
|
* PIRQ3 -> irq 11
|
| 1834 |
|
|
*
|
| 1835 |
|
|
* This probably ought to be configurable via MILO. For
|
| 1836 |
|
|
* example, sound boards seem to like using IRQ 9.
|
| 1837 |
|
|
*/
|
| 1838 |
|
|
#ifdef CONFIG_ALPHA_NONAME
|
| 1839 |
|
|
/*
|
| 1840 |
|
|
* For UDB, the only available PCI slot must not map to IRQ 9,
|
| 1841 |
|
|
* since that's the builtin MSS sound chip. That PCI slot
|
| 1842 |
|
|
* will map to PIRQ1 (for INTA at least), so we give it IRQ 15
|
| 1843 |
|
|
* instead.
|
| 1844 |
|
|
*
|
| 1845 |
|
|
* Unfortunately we have to do this for NONAME as well, since
|
| 1846 |
|
|
* they are co-indicated when the platform type "Noname" is
|
| 1847 |
|
|
* selected... :-(
|
| 1848 |
|
|
*/
|
| 1849 |
|
|
#ifdef CONFIG_ALPHA_BOOK1
|
| 1850 |
|
|
/* for the AlphaBook1, NCR810 SCSI is 14, PCMCIA controller is 15 */
|
| 1851 |
|
|
const unsigned int route_tab = 0x0e0f0a0a;
|
| 1852 |
|
|
#else /* CONFIG_ALPHA_BOOK1 */
|
| 1853 |
|
|
const unsigned int route_tab = 0x0b0a0f09;
|
| 1854 |
|
|
#endif /* CONFIG_ALPHA_BOOK1 */
|
| 1855 |
|
|
#else /* CONFIG_ALPHA_NONAME */
|
| 1856 |
|
|
const unsigned int route_tab = 0x0b0a090f;
|
| 1857 |
|
|
#endif /* CONFIG_ALPHA_NONAME */
|
| 1858 |
|
|
unsigned int level_bits;
|
| 1859 |
|
|
unsigned char pin, slot;
|
| 1860 |
|
|
int pirq;
|
| 1861 |
|
|
|
| 1862 |
|
|
pcibios_write_config_dword(0, PCI_DEVFN(7, 0), 0x60, route_tab);
|
| 1863 |
|
|
|
| 1864 |
|
|
/*
|
| 1865 |
|
|
* Go through all devices, fixing up irqs as we see fit:
|
| 1866 |
|
|
*/
|
| 1867 |
|
|
level_bits = 0;
|
| 1868 |
|
|
for (dev = pci_devices; dev; dev = dev->next) {
|
| 1869 |
|
|
if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE)
|
| 1870 |
|
|
#ifdef CONFIG_ALPHA_BOOK1
|
| 1871 |
|
|
&& (dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA)
|
| 1872 |
|
|
#endif /* CONFIG_ALPHA_BOOK1 */
|
| 1873 |
|
|
)
|
| 1874 |
|
|
continue;
|
| 1875 |
|
|
dev->irq = 0;
|
| 1876 |
|
|
if (dev->bus->number != 0) {
|
| 1877 |
|
|
struct pci_dev *curr = dev ;
|
| 1878 |
|
|
/*
|
| 1879 |
|
|
* read the pin and do the PCI-PCI bridge
|
| 1880 |
|
|
* interrupt pin swizzle
|
| 1881 |
|
|
*/
|
| 1882 |
|
|
pcibios_read_config_byte(dev->bus->number, dev->devfn,
|
| 1883 |
|
|
PCI_INTERRUPT_PIN, &pin);
|
| 1884 |
|
|
/* cope with 0 */
|
| 1885 |
|
|
if (pin == 0) pin = 1 ;
|
| 1886 |
|
|
/* follow the chain of bridges, swizzling as we go */
|
| 1887 |
|
|
do {
|
| 1888 |
|
|
/* swizzle */
|
| 1889 |
|
|
pin = bridge_swizzle(pin, PCI_SLOT(curr->devfn)) ;
|
| 1890 |
|
|
/* move up the chain of bridges */
|
| 1891 |
|
|
curr = curr->bus->self ;
|
| 1892 |
|
|
} while (curr->bus->self) ;
|
| 1893 |
|
|
/* The slot is the slot of the last bridge. */
|
| 1894 |
|
|
slot = PCI_SLOT(curr->devfn) ;
|
| 1895 |
|
|
} else {
|
| 1896 |
|
|
/* work out the slot */
|
| 1897 |
|
|
slot = PCI_SLOT(dev->devfn) ;
|
| 1898 |
|
|
/* read the pin */
|
| 1899 |
|
|
pcibios_read_config_byte(dev->bus->number, dev->devfn,
|
| 1900 |
|
|
PCI_INTERRUPT_PIN, &pin);
|
| 1901 |
|
|
}
|
| 1902 |
|
|
|
| 1903 |
|
|
if (slot < 6 || slot >= 6 + sizeof(pirq_tab)/sizeof(pirq_tab[0])) {
|
| 1904 |
|
|
printk("bios32.sio_fixup: "
|
| 1905 |
|
|
"weird, found device %04x:%04x "
|
| 1906 |
|
|
"in non-existent slot %d!!\n",
|
| 1907 |
|
|
dev->vendor, dev->device, slot);
|
| 1908 |
|
|
continue;
|
| 1909 |
|
|
}
|
| 1910 |
|
|
pirq = pirq_tab[slot - 6][pin];
|
| 1911 |
|
|
|
| 1912 |
|
|
DBG_DEVS(("sio_fixup: bus %d slot 0x%x VID 0x%x DID 0x%x\n"
|
| 1913 |
|
|
" int_slot 0x%x pin 0x%x pirq 0x%x\n",
|
| 1914 |
|
|
dev->bus->number, PCI_SLOT(dev->devfn), dev->vendor,
|
| 1915 |
|
|
dev->device, slot, pin, pirq));
|
| 1916 |
|
|
/*
|
| 1917 |
|
|
* if it's a VGA, enable its BIOS ROM at C0000
|
| 1918 |
|
|
*/
|
| 1919 |
|
|
if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
|
| 1920 |
|
|
pcibios_write_config_dword(dev->bus->number, dev->devfn,
|
| 1921 |
|
|
PCI_ROM_ADDRESS,
|
| 1922 |
|
|
0x000c0000 | PCI_ROM_ADDRESS_ENABLE);
|
| 1923 |
|
|
}
|
| 1924 |
|
|
if ((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
|
| 1925 |
|
|
continue; /* for now, displays get no IRQ */
|
| 1926 |
|
|
}
|
| 1927 |
|
|
|
| 1928 |
|
|
if (pirq < 0) {
|
| 1929 |
|
|
printk("bios32.sio_fixup: "
|
| 1930 |
|
|
"weird, device %04x:%04x coming in on slot %d has no irq line!!\n",
|
| 1931 |
|
|
dev->vendor, dev->device, slot);
|
| 1932 |
|
|
continue;
|
| 1933 |
|
|
}
|
| 1934 |
|
|
|
| 1935 |
|
|
dev->irq = (route_tab >> (8 * pirq)) & 0xff;
|
| 1936 |
|
|
|
| 1937 |
|
|
#ifndef CONFIG_ALPHA_BOOK1
|
| 1938 |
|
|
/* do not set *ANY* level triggers for AlphaBook1 */
|
| 1939 |
|
|
/* must set the PCI IRQs to level triggered */
|
| 1940 |
|
|
level_bits |= (1 << dev->irq);
|
| 1941 |
|
|
#endif /* !CONFIG_ALPHA_BOOK1 */
|
| 1942 |
|
|
|
| 1943 |
|
|
#if PCI_MODIFY
|
| 1944 |
|
|
/* tell the device: */
|
| 1945 |
|
|
pcibios_write_config_byte(dev->bus->number, dev->devfn,
|
| 1946 |
|
|
PCI_INTERRUPT_LINE, dev->irq);
|
| 1947 |
|
|
#endif
|
| 1948 |
|
|
|
| 1949 |
|
|
#ifdef CONFIG_ALPHA_BOOK1
|
| 1950 |
|
|
/*
|
| 1951 |
|
|
* on the AlphaBook1, the PCMCIA chip (Cirrus 6729)
|
| 1952 |
|
|
* is sensitive to PCI bus bursts, so we must DISABLE
|
| 1953 |
|
|
* burst mode for the NCR 8xx SCSI... :-(
|
| 1954 |
|
|
*
|
| 1955 |
|
|
* Note that the NCR810 SCSI driver must preserve the
|
| 1956 |
|
|
* setting of the bit in order for this to work. At the
|
| 1957 |
|
|
* moment (2.0.29), ncr53c8xx.c does NOT do this, but
|
| 1958 |
|
|
* 53c7,8xx.c DOES...
|
| 1959 |
|
|
*/
|
| 1960 |
|
|
if ((dev->vendor == PCI_VENDOR_ID_NCR) &&
|
| 1961 |
|
|
((dev->device == PCI_DEVICE_ID_NCR_53C810) ||
|
| 1962 |
|
|
(dev->device == PCI_DEVICE_ID_NCR_53C815) ||
|
| 1963 |
|
|
(dev->device == PCI_DEVICE_ID_NCR_53C820) ||
|
| 1964 |
|
|
(dev->device == PCI_DEVICE_ID_NCR_53C825)
|
| 1965 |
|
|
)) {
|
| 1966 |
|
|
unsigned int io_port;
|
| 1967 |
|
|
unsigned char ctest4;
|
| 1968 |
|
|
|
| 1969 |
|
|
pcibios_read_config_dword(dev->bus->number, dev->devfn,
|
| 1970 |
|
|
PCI_BASE_ADDRESS_0, &io_port);
|
| 1971 |
|
|
io_port &= PCI_BASE_ADDRESS_IO_MASK;
|
| 1972 |
|
|
ctest4 = inb(io_port+0x21);
|
| 1973 |
|
|
if (!(ctest4 & 0x80)) {
|
| 1974 |
|
|
printk("AlphaBook1 NCR init: setting burst disable\n");
|
| 1975 |
|
|
outb(ctest4 | 0x80, io_port+0x21);
|
| 1976 |
|
|
}
|
| 1977 |
|
|
}
|
| 1978 |
|
|
#endif /* CONFIG_ALPHA_BOOK1 */
|
| 1979 |
|
|
|
| 1980 |
|
|
} /* end for devs */
|
| 1981 |
|
|
|
| 1982 |
|
|
/*
|
| 1983 |
|
|
* Now, make all PCI interrupts level sensitive. Notice:
|
| 1984 |
|
|
* these registers must be accessed byte-wise. inw()/outw()
|
| 1985 |
|
|
* don't work.
|
| 1986 |
|
|
*
|
| 1987 |
|
|
* Make sure to turn off any level bits set for IRQs 9,10,11,15,
|
| 1988 |
|
|
* so that the only bits getting set are for devices actually found.
|
| 1989 |
|
|
* Note that we do preserve the remainder of the bits, which we hope
|
| 1990 |
|
|
* will be set correctly by ARC/SRM.
|
| 1991 |
|
|
*
|
| 1992 |
|
|
* Note: we at least preserve any level-set bits on AlphaBook1
|
| 1993 |
|
|
*/
|
| 1994 |
|
|
level_bits |= ((inb(0x4d0) | (inb(0x4d1) << 8)) & 0x71ff);
|
| 1995 |
|
|
outb((level_bits >> 0) & 0xff, 0x4d0);
|
| 1996 |
|
|
outb((level_bits >> 8) & 0xff, 0x4d1);
|
| 1997 |
|
|
|
| 1998 |
|
|
#ifdef CONFIG_ALPHA_BOOK1
|
| 1999 |
|
|
{
|
| 2000 |
|
|
unsigned char orig, config;
|
| 2001 |
|
|
/* on the AlphaBook1, make sure that register PR1 indicates 1Mb mem */
|
| 2002 |
|
|
outb(0x0f, 0x3ce); orig = inb(0x3cf); /* read PR5 */
|
| 2003 |
|
|
outb(0x0f, 0x3ce); outb(0x05, 0x3cf); /* unlock PR0-4 */
|
| 2004 |
|
|
outb(0x0b, 0x3ce); config = inb(0x3cf); /* read PR1 */
|
| 2005 |
|
|
if ((config & 0xc0) != 0xc0) {
|
| 2006 |
|
|
printk("AlphaBook1 VGA init: setting 1Mb memory\n");
|
| 2007 |
|
|
config |= 0xc0;
|
| 2008 |
|
|
outb(0x0b, 0x3ce); outb(config, 0x3cf); /* write PR1 */
|
| 2009 |
|
|
}
|
| 2010 |
|
|
outb(0x0f, 0x3ce); outb(orig, 0x3cf); /* (re)lock PR0-4 */
|
| 2011 |
|
|
}
|
| 2012 |
|
|
#endif /* CONFIG_ALPHA_BOOK1 */
|
| 2013 |
|
|
|
| 2014 |
|
|
#ifndef CONFIG_ALPHA_BOOK1
|
| 2015 |
|
|
/* do not do IDE init for AlphaBook1 */
|
| 2016 |
|
|
enable_ide(0x26e);
|
| 2017 |
|
|
#endif /* !CONFIG_ALPHA_BOOK1 */
|
| 2018 |
|
|
}
|
| 2019 |
|
|
|
| 2020 |
|
|
|
| 2021 |
|
|
#ifdef CONFIG_TGA_CONSOLE
|
| 2022 |
|
|
extern void tga_console_find(void);
|
| 2023 |
|
|
#endif /* CONFIG_TGA_CONSOLE */
|
| 2024 |
|
|
|
| 2025 |
|
|
unsigned long pcibios_fixup(unsigned long mem_start, unsigned long mem_end)
|
| 2026 |
|
|
{
|
| 2027 |
|
|
#if PCI_MODIFY && !defined(CONFIG_ALPHA_RUFFIAN)
|
| 2028 |
|
|
/*
|
| 2029 |
|
|
* Scan the tree, allocating PCI memory and I/O space.
|
| 2030 |
|
|
*/
|
| 2031 |
|
|
layout_bus(&pci_root);
|
| 2032 |
|
|
#endif
|
| 2033 |
|
|
|
| 2034 |
|
|
/*
|
| 2035 |
|
|
* Now is the time to do all those dirty little deeds...
|
| 2036 |
|
|
*/
|
| 2037 |
|
|
#if defined(CONFIG_ALPHA_NONAME) || defined(CONFIG_ALPHA_AVANTI) || defined(CONFIG_ALPHA_P2K)
|
| 2038 |
|
|
sio_fixup();
|
| 2039 |
|
|
#elif defined(CONFIG_ALPHA_CABRIOLET) || defined(CONFIG_ALPHA_EB164)
|
| 2040 |
|
|
cabriolet_fixup();
|
| 2041 |
|
|
#elif defined(CONFIG_ALPHA_PC164) || defined(CONFIG_ALPHA_LX164)
|
| 2042 |
|
|
alphapc164_fixup();
|
| 2043 |
|
|
#elif defined(CONFIG_ALPHA_EB66P)
|
| 2044 |
|
|
eb66p_fixup();
|
| 2045 |
|
|
#elif defined(CONFIG_ALPHA_EB66)
|
| 2046 |
|
|
eb66_and_eb64p_fixup();
|
| 2047 |
|
|
#elif defined(CONFIG_ALPHA_EB64P)
|
| 2048 |
|
|
eb66_and_eb64p_fixup();
|
| 2049 |
|
|
#elif defined(CONFIG_ALPHA_MIKASA)
|
| 2050 |
|
|
mikasa_fixup();
|
| 2051 |
|
|
#elif defined(CONFIG_ALPHA_ALCOR) || defined(CONFIG_ALPHA_XLT)
|
| 2052 |
|
|
alcor_fixup();
|
| 2053 |
|
|
#elif defined(CONFIG_ALPHA_SABLE)
|
| 2054 |
|
|
sable_fixup();
|
| 2055 |
|
|
#elif defined(CONFIG_ALPHA_MIATA)
|
| 2056 |
|
|
miata_fixup();
|
| 2057 |
|
|
#elif defined(CONFIG_ALPHA_NORITAKE)
|
| 2058 |
|
|
noritake_fixup();
|
| 2059 |
|
|
#elif defined(CONFIG_ALPHA_SX164)
|
| 2060 |
|
|
sx164_fixup();
|
| 2061 |
|
|
#elif defined(CONFIG_ALPHA_TAKARA)
|
| 2062 |
|
|
takara_fixup();
|
| 2063 |
|
|
#elif defined(CONFIG_ALPHA_RUFFIAN)
|
| 2064 |
|
|
ruffian_fixup();
|
| 2065 |
|
|
#else
|
| 2066 |
|
|
# error You must tell me what kind of platform you want.
|
| 2067 |
|
|
#endif
|
| 2068 |
|
|
|
| 2069 |
|
|
#ifdef CONFIG_TGA_CONSOLE
|
| 2070 |
|
|
tga_console_find();
|
| 2071 |
|
|
#endif /* CONFIG_TGA_CONSOLE */
|
| 2072 |
|
|
|
| 2073 |
|
|
return mem_start;
|
| 2074 |
|
|
}
|
| 2075 |
|
|
|
| 2076 |
|
|
|
| 2077 |
|
|
const char *pcibios_strerror (int error)
|
| 2078 |
|
|
{
|
| 2079 |
|
|
static char buf[80];
|
| 2080 |
|
|
|
| 2081 |
|
|
switch (error) {
|
| 2082 |
|
|
case PCIBIOS_SUCCESSFUL:
|
| 2083 |
|
|
return "SUCCESSFUL";
|
| 2084 |
|
|
|
| 2085 |
|
|
case PCIBIOS_FUNC_NOT_SUPPORTED:
|
| 2086 |
|
|
return "FUNC_NOT_SUPPORTED";
|
| 2087 |
|
|
|
| 2088 |
|
|
case PCIBIOS_BAD_VENDOR_ID:
|
| 2089 |
|
|
return "SUCCESSFUL";
|
| 2090 |
|
|
|
| 2091 |
|
|
case PCIBIOS_DEVICE_NOT_FOUND:
|
| 2092 |
|
|
return "DEVICE_NOT_FOUND";
|
| 2093 |
|
|
|
| 2094 |
|
|
case PCIBIOS_BAD_REGISTER_NUMBER:
|
| 2095 |
|
|
return "BAD_REGISTER_NUMBER";
|
| 2096 |
|
|
|
| 2097 |
|
|
default:
|
| 2098 |
|
|
sprintf (buf, "UNKNOWN RETURN 0x%x", error);
|
| 2099 |
|
|
return buf;
|
| 2100 |
|
|
}
|
| 2101 |
|
|
}
|
| 2102 |
|
|
|
| 2103 |
|
|
asmlinkage int sys_pciconfig_read(
|
| 2104 |
|
|
unsigned long bus,
|
| 2105 |
|
|
unsigned long dfn,
|
| 2106 |
|
|
unsigned long off,
|
| 2107 |
|
|
unsigned long len,
|
| 2108 |
|
|
unsigned char *buf)
|
| 2109 |
|
|
{
|
| 2110 |
|
|
unsigned char ubyte;
|
| 2111 |
|
|
unsigned short ushort;
|
| 2112 |
|
|
unsigned int uint;
|
| 2113 |
|
|
long err = 0;
|
| 2114 |
|
|
|
| 2115 |
|
|
switch (len) {
|
| 2116 |
|
|
case 1:
|
| 2117 |
|
|
err = pcibios_read_config_byte(bus, dfn, off, &ubyte);
|
| 2118 |
|
|
if (err != PCIBIOS_SUCCESSFUL)
|
| 2119 |
|
|
ubyte = 0xff;
|
| 2120 |
|
|
put_user(ubyte, buf);
|
| 2121 |
|
|
break;
|
| 2122 |
|
|
case 2:
|
| 2123 |
|
|
err = pcibios_read_config_word(bus, dfn, off, &ushort);
|
| 2124 |
|
|
if (err != PCIBIOS_SUCCESSFUL)
|
| 2125 |
|
|
ushort = 0xffff;
|
| 2126 |
|
|
put_user(ushort, (unsigned short *)buf);
|
| 2127 |
|
|
break;
|
| 2128 |
|
|
case 4:
|
| 2129 |
|
|
err = pcibios_read_config_dword(bus, dfn, off, &uint);
|
| 2130 |
|
|
if (err != PCIBIOS_SUCCESSFUL)
|
| 2131 |
|
|
uint = 0xffffffff;
|
| 2132 |
|
|
put_user(uint, (unsigned int *)buf);
|
| 2133 |
|
|
break;
|
| 2134 |
|
|
default:
|
| 2135 |
|
|
err = -EINVAL;
|
| 2136 |
|
|
break;
|
| 2137 |
|
|
}
|
| 2138 |
|
|
return err;
|
| 2139 |
|
|
}
|
| 2140 |
|
|
asmlinkage int sys_pciconfig_write(
|
| 2141 |
|
|
unsigned long bus,
|
| 2142 |
|
|
unsigned long dfn,
|
| 2143 |
|
|
unsigned long off,
|
| 2144 |
|
|
unsigned long len,
|
| 2145 |
|
|
unsigned char *buf)
|
| 2146 |
|
|
{
|
| 2147 |
|
|
unsigned char ubyte;
|
| 2148 |
|
|
unsigned short ushort;
|
| 2149 |
|
|
unsigned int uint;
|
| 2150 |
|
|
long err = 0;
|
| 2151 |
|
|
|
| 2152 |
|
|
switch (len) {
|
| 2153 |
|
|
case 1:
|
| 2154 |
|
|
ubyte = get_user(buf);
|
| 2155 |
|
|
err = pcibios_write_config_byte(bus, dfn, off, ubyte);
|
| 2156 |
|
|
if (err != PCIBIOS_SUCCESSFUL) {
|
| 2157 |
|
|
err = -EFAULT;
|
| 2158 |
|
|
}
|
| 2159 |
|
|
break;
|
| 2160 |
|
|
case 2:
|
| 2161 |
|
|
ushort = get_user((unsigned short *)buf);
|
| 2162 |
|
|
err = pcibios_write_config_word(bus, dfn, off, ushort);
|
| 2163 |
|
|
if (err != PCIBIOS_SUCCESSFUL) {
|
| 2164 |
|
|
err = -EFAULT;
|
| 2165 |
|
|
}
|
| 2166 |
|
|
break;
|
| 2167 |
|
|
case 4:
|
| 2168 |
|
|
uint = get_user((unsigned int *)buf);
|
| 2169 |
|
|
err = pcibios_write_config_dword(bus, dfn, off, uint);
|
| 2170 |
|
|
if (err != PCIBIOS_SUCCESSFUL) {
|
| 2171 |
|
|
err = -EFAULT;
|
| 2172 |
|
|
}
|
| 2173 |
|
|
break;
|
| 2174 |
|
|
default:
|
| 2175 |
|
|
err = -EINVAL;
|
| 2176 |
|
|
break;
|
| 2177 |
|
|
}
|
| 2178 |
|
|
return err;
|
| 2179 |
|
|
}
|
| 2180 |
|
|
|
| 2181 |
|
|
#if (defined(CONFIG_ALPHA_PC164) || \
|
| 2182 |
|
|
defined(CONFIG_ALPHA_LX164) || \
|
| 2183 |
|
|
defined(CONFIG_ALPHA_SX164) || \
|
| 2184 |
|
|
defined(CONFIG_ALPHA_EB164) || \
|
| 2185 |
|
|
defined(CONFIG_ALPHA_EB66P) || \
|
| 2186 |
|
|
defined(CONFIG_ALPHA_CABRIOLET)) && defined(CONFIG_ALPHA_SRM)
|
| 2187 |
|
|
|
| 2188 |
|
|
/*
|
| 2189 |
|
|
on the above machines, under SRM console, we must use the CSERVE PALcode
|
| 2190 |
|
|
routine to manage the interrupt mask for us, otherwise, the kernel/HW get
|
| 2191 |
|
|
out of sync with what the PALcode thinks it needs to deliver/ignore
|
| 2192 |
|
|
*/
|
| 2193 |
|
|
void
|
| 2194 |
|
|
cserve_update_hw(unsigned long irq, unsigned long mask)
|
| 2195 |
|
|
{
|
| 2196 |
|
|
extern void cserve_ena(unsigned long);
|
| 2197 |
|
|
extern void cserve_dis(unsigned long);
|
| 2198 |
|
|
|
| 2199 |
|
|
if (mask & (1UL << irq))
|
| 2200 |
|
|
/* disable */
|
| 2201 |
|
|
cserve_dis(irq - 16);
|
| 2202 |
|
|
else
|
| 2203 |
|
|
/* enable */
|
| 2204 |
|
|
cserve_ena(irq - 16);
|
| 2205 |
|
|
return;
|
| 2206 |
|
|
}
|
| 2207 |
|
|
#endif /* (PC164 || LX164 || SX164 || EB164 || CABRIO) && SRM */
|
| 2208 |
|
|
|
| 2209 |
|
|
#ifdef CONFIG_ALPHA_MIATA
|
| 2210 |
|
|
|
| 2211 |
|
|
/* init the built-in ES1888 sound chip (SB16 compatible) */
|
| 2212 |
|
|
int es1888_init(void)
|
| 2213 |
|
|
{
|
| 2214 |
|
|
/* sequence of IO reads to init the audio controller */
|
| 2215 |
|
|
inb(0x0229);
|
| 2216 |
|
|
inb(0x0229);
|
| 2217 |
|
|
inb(0x0229);
|
| 2218 |
|
|
inb(0x022b);
|
| 2219 |
|
|
inb(0x0229);
|
| 2220 |
|
|
inb(0x022b);
|
| 2221 |
|
|
inb(0x0229);
|
| 2222 |
|
|
inb(0x0229);
|
| 2223 |
|
|
inb(0x022b);
|
| 2224 |
|
|
inb(0x0229);
|
| 2225 |
|
|
inb(0x0220); /* this sets the base address to 0x220 */
|
| 2226 |
|
|
|
| 2227 |
|
|
/* sequence to set DMA channels */
|
| 2228 |
|
|
outb(0x01, 0x0226); /* reset */
|
| 2229 |
|
|
inb(0x0226); /* pause */
|
| 2230 |
|
|
outb(0x00, 0x0226); /* release reset */
|
| 2231 |
|
|
while (!(inb(0x022e) & 0x80)) /* wait for bit 7 to assert*/
|
| 2232 |
|
|
continue;
|
| 2233 |
|
|
inb(0x022a); /* pause */
|
| 2234 |
|
|
outb(0xc6, 0x022c); /* enable extended mode */
|
| 2235 |
|
|
while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */
|
| 2236 |
|
|
continue;
|
| 2237 |
|
|
outb(0xb1, 0x022c); /* setup for write to Interrupt CR */
|
| 2238 |
|
|
while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */
|
| 2239 |
|
|
continue;
|
| 2240 |
|
|
outb(0x14, 0x022c); /* set IRQ 5 */
|
| 2241 |
|
|
while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */
|
| 2242 |
|
|
continue;
|
| 2243 |
|
|
outb(0xb2, 0x022c); /* setup for write to DMA CR */
|
| 2244 |
|
|
while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */
|
| 2245 |
|
|
continue;
|
| 2246 |
|
|
outb(0x18, 0x022c); /* set DMA channel 1 */
|
| 2247 |
|
|
|
| 2248 |
|
|
return 0;
|
| 2249 |
|
|
}
|
| 2250 |
|
|
|
| 2251 |
|
|
#endif /* CONFIG_ALPHA_MIATA */
|
| 2252 |
|
|
|
| 2253 |
|
|
#ifdef CONFIG_ALPHA_SRM_SETUP
|
| 2254 |
|
|
void reset_for_srm(void)
|
| 2255 |
|
|
{
|
| 2256 |
|
|
extern void scrreset(void);
|
| 2257 |
|
|
struct pci_dev *dev;
|
| 2258 |
|
|
int i;
|
| 2259 |
|
|
|
| 2260 |
|
|
/* reset any IRQs that we changed */
|
| 2261 |
|
|
for (i = 0; i < irq_reset_count; i++) {
|
| 2262 |
|
|
dev = irq_dev_to_reset[i];
|
| 2263 |
|
|
|
| 2264 |
|
|
pcibios_write_config_byte(dev->bus->number, dev->devfn,
|
| 2265 |
|
|
PCI_INTERRUPT_LINE, irq_to_reset[i]);
|
| 2266 |
|
|
#if 1
|
| 2267 |
|
|
printk("reset_for_srm: bus %d slot 0x%x "
|
| 2268 |
|
|
"SRM IRQ 0x%x changed back from 0x%x\n",
|
| 2269 |
|
|
dev->bus->number, PCI_SLOT(dev->devfn),
|
| 2270 |
|
|
irq_to_reset[i], dev->irq);
|
| 2271 |
|
|
#endif
|
| 2272 |
|
|
}
|
| 2273 |
|
|
|
| 2274 |
|
|
/* reset any IO addresses that we changed */
|
| 2275 |
|
|
for (i = 0; i < io_reset_count; i++) {
|
| 2276 |
|
|
dev = io_dev_to_reset[i];
|
| 2277 |
|
|
|
| 2278 |
|
|
pcibios_write_config_byte(dev->bus->number, dev->devfn,
|
| 2279 |
|
|
io_reg_to_reset[i], io_to_reset[i]);
|
| 2280 |
|
|
#if 1
|
| 2281 |
|
|
printk("reset_for_srm: bus %d slot 0x%x "
|
| 2282 |
|
|
"SRM IO restored to 0x%x\n",
|
| 2283 |
|
|
dev->bus->number, PCI_SLOT(dev->devfn),
|
| 2284 |
|
|
io_to_reset[i]);
|
| 2285 |
|
|
#endif
|
| 2286 |
|
|
}
|
| 2287 |
|
|
|
| 2288 |
|
|
/* reset the visible screen to the top of display memory */
|
| 2289 |
|
|
scrreset();
|
| 2290 |
|
|
}
|
| 2291 |
|
|
#endif /* CONFIG_ALPHA_SRM_SETUP */
|
| 2292 |
|
|
|
| 2293 |
|
|
#endif /* CONFIG_PCI */
|
