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jcastillo |
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| fpsp.h 3.3 3.3
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| Copyright (C) Motorola, Inc. 1990
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| All Rights Reserved
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| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
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| The copyright notice above does not evidence any
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| actual or intended publication of such source code.
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| fpsp.h --- stack frame offsets during FPSP exception handling
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| These equates are used to access the exception frame, the fsave
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| frame and any local variables needed by the FPSP package.
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| All FPSP handlers begin by executing:
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| link a6,#-LOCAL_SIZE
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| fsave -(a7)
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| movem.l d0-d1/a0-a1,USER_DA(a6)
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| fmovem.x fp0-fp3,USER_FP0(a6)
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| fmove.l fpsr/fpcr/fpiar,USER_FPSR(a6)
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| After initialization, the stack looks like this:
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| A7 ---> +-------------------------------+
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| | FPU fsave area |
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| +-------------------------------+
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| | FPSP Local Variables |
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| | including |
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| | saved registers |
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| +-------------------------------+
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| A6 ---> | Saved A6 |
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| +-------------------------------+
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| | Exception Frame |
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| Positive offsets from A6 refer to the exception frame. Negative
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| offsets refer to the Local Variable area and the fsave area.
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| The fsave frame is also accessible from the top via A7.
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| On exit, the handlers execute:
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| movem.l USER_DA(a6),d0-d1/a0-a1
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| fmovem.x USER_FP0(a6),fp0-fp3
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| fmove.l USER_FPSR(a6),fpsr/fpcr/fpiar
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| frestore (a7)+
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| unlk a6
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| and then either "bra fpsp_done" if the exception was completely
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| handled by the package, or "bra real_xxxx" which is an external
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| label to a routine that will process a real exception of the
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| type that was generated. Some handlers may omit the "frestore"
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| if the FPU state after the exception is idle.
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| Sometimes the exception handler will transform the fsave area
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| because it needs to report an exception back to the user. This
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| can happen if the package is entered for an unimplemented float
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| instruction that generates (say) an underflow. Alternatively,
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| a second fsave frame can be pushed onto the stack and the
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| handler exit code will reload the new frame and discard the old.
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| The registers d0, d1, a0, a1 and fp0-fp3 are always saved and
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| restored from the "local variable" area and can be used as
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| temporaries. If a routine needs to change any
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| of these registers, it should modify the saved copy and let
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| the handler exit code restore the value.
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|----------------------------------------------------------------------
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| Local Variables on the stack
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.set LOCAL_SIZE,192 | bytes needed for local variables
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.set LV,-LOCAL_SIZE | convenient base value
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.set USER_DA,LV+0 | save space for D0-D1,A0-A1
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.set USER_D0,LV+0 | saved user D0
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.set USER_D1,LV+4 | saved user D1
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.set USER_A0,LV+8 | saved user A0
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.set USER_A1,LV+12 | saved user A1
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.set USER_FP0,LV+16 | saved user FP0
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.set USER_FP1,LV+28 | saved user FP1
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.set USER_FP2,LV+40 | saved user FP2
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.set USER_FP3,LV+52 | saved user FP3
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.set USER_FPCR,LV+64 | saved user FPCR
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.set FPCR_ENABLE,USER_FPCR+2 | FPCR exception enable
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.set FPCR_MODE,USER_FPCR+3 | FPCR rounding mode control
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.set USER_FPSR,LV+68 | saved user FPSR
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.set FPSR_CC,USER_FPSR+0 | FPSR condition code
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.set FPSR_QBYTE,USER_FPSR+1 | FPSR quotient
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.set FPSR_EXCEPT,USER_FPSR+2 | FPSR exception
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.set FPSR_AEXCEPT,USER_FPSR+3 | FPSR accrued exception
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.set USER_FPIAR,LV+72 | saved user FPIAR
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.set FP_SCR1,LV+76 | room for a temporary float value
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.set FP_SCR2,LV+92 | room for a temporary float value
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.set L_SCR1,LV+108 | room for a temporary long value
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.set L_SCR2,LV+112 | room for a temporary long value
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.set STORE_FLG,LV+116
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.set BINDEC_FLG,LV+117 | used in bindec
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.set DNRM_FLG,LV+118 | used in res_func
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.set RES_FLG,LV+119 | used in res_func
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.set DY_MO_FLG,LV+120 | dyadic/monadic flag
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.set UFLG_TMP,LV+121 | temporary for uflag errata
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.set CU_ONLY,LV+122 | cu-only flag
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.set VER_TMP,LV+123 | temp holding for version number
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.set L_SCR3,LV+124 | room for a temporary long value
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.set FP_SCR3,LV+128 | room for a temporary float value
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.set FP_SCR4,LV+144 | room for a temporary float value
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.set FP_SCR5,LV+160 | room for a temporary float value
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.set FP_SCR6,LV+176
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|NEXT equ LV+192 ;need to increase LOCAL_SIZE
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|--------------------------------------------------------------------------
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| fsave offsets and bit definitions
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| Offsets are defined from the end of an fsave because the last 10
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| words of a busy frame are the same as the unimplemented frame.
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.set CU_SAVEPC,LV-92 | micro-pc for CU (1 byte)
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.set FPR_DIRTY_BITS,LV-91 | fpr dirty bits
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.set WBTEMP,LV-76 | write back temp (12 bytes)
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.set WBTEMP_EX,WBTEMP | wbtemp sign and exponent (2 bytes)
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.set WBTEMP_HI,WBTEMP+4 | wbtemp mantissa [63:32] (4 bytes)
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.set WBTEMP_LO,WBTEMP+8 | wbtemp mantissa [31:00] (4 bytes)
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.set WBTEMP_SGN,WBTEMP+2 | used to store sign
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.set FPSR_SHADOW,LV-64 | fpsr shadow reg
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.set FPIARCU,LV-60 | Instr. addr. reg. for CU (4 bytes)
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.set CMDREG2B,LV-52 | cmd reg for machine 2
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.set CMDREG3B,LV-48 | cmd reg for E3 exceptions (2 bytes)
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.set NMNEXC,LV-44 | NMNEXC (unsup,snan bits only)
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.set nmn_unsup_bit,1 |
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.set nmn_snan_bit,0 |
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.set NMCEXC,LV-43 | NMNEXC & NMCEXC
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.set nmn_operr_bit,7
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.set nmn_ovfl_bit,6
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.set nmn_unfl_bit,5
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.set nmc_unsup_bit,4
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.set nmc_snan_bit,3
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.set nmc_operr_bit,2
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.set nmc_ovfl_bit,1
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.set nmc_unfl_bit,0
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.set STAG,LV-40 | source tag (1 byte)
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.set WBTEMP_GRS,LV-40 | alias wbtemp guard, round, sticky
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.set guard_bit,1 | guard bit is bit number 1
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.set round_bit,0 | round bit is bit number 0
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.set stag_mask,0xE0 | upper 3 bits are source tag type
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.set denorm_bit,7 | bit determines if denorm or unnorm
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.set etemp15_bit,4 | etemp exponent bit #15
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.set wbtemp66_bit,2 | wbtemp mantissa bit #66
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.set wbtemp1_bit,1 | wbtemp mantissa bit #1
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.set wbtemp0_bit,0 | wbtemp mantissa bit #0
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.set STICKY,LV-39 | holds sticky bit
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.set sticky_bit,7
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.set CMDREG1B,LV-36 | cmd reg for E1 exceptions (2 bytes)
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.set kfact_bit,12 | distinguishes static/dynamic k-factor
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| ;on packed move outs. NOTE: this
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| ;equate only works when CMDREG1B is in
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| ;a register.
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.set CMDWORD,LV-35 | command word in cmd1b
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.set direction_bit,5 | bit 0 in opclass
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.set size_bit2,12 | bit 2 in size field
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.set DTAG,LV-32 | dest tag (1 byte)
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.set dtag_mask,0xE0 | upper 3 bits are dest type tag
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.set fptemp15_bit,4 | fptemp exponent bit #15
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.set WB_BYTE,LV-31 | holds WBTE15 bit (1 byte)
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.set wbtemp15_bit,4 | wbtemp exponent bit #15
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.set E_BYTE,LV-28 | holds E1 and E3 bits (1 byte)
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.set E1,2 | which bit is E1 flag
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.set E3,1 | which bit is E3 flag
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.set SFLAG,0 | which bit is S flag
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.set T_BYTE,LV-27 | holds T and U bits (1 byte)
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.set XFLAG,7 | which bit is X flag
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.set UFLAG,5 | which bit is U flag
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.set TFLAG,4 | which bit is T flag
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.set FPTEMP,LV-24 | fptemp (12 bytes)
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.set FPTEMP_EX,FPTEMP | fptemp sign and exponent (2 bytes)
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.set FPTEMP_HI,FPTEMP+4 | fptemp mantissa [63:32] (4 bytes)
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.set FPTEMP_LO,FPTEMP+8 | fptemp mantissa [31:00] (4 bytes)
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.set FPTEMP_SGN,FPTEMP+2 | used to store sign
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.set ETEMP,LV-12 | etemp (12 bytes)
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.set ETEMP_EX,ETEMP | etemp sign and exponent (2 bytes)
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.set ETEMP_HI,ETEMP+4 | etemp mantissa [63:32] (4 bytes)
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.set ETEMP_LO,ETEMP+8 | etemp mantissa [31:00] (4 bytes)
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.set ETEMP_SGN,ETEMP+2 | used to store sign
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.set EXC_SR,4 | exception frame status register
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.set EXC_PC,6 | exception frame program counter
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.set EXC_VEC,10 | exception frame vector (format+vector#)
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.set EXC_EA,12 | exception frame effective address
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|--------------------------------------------------------------------------
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| FPSR/FPCR bits
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.set neg_bit,3 | negative result
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.set z_bit,2 | zero result
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.set inf_bit,1 | infinity result
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.set nan_bit,0 | not-a-number result
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.set q_sn_bit,7 | sign bit of quotient byte
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.set bsun_bit,7 | branch on unordered
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.set snan_bit,6 | signalling nan
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.set operr_bit,5 | operand error
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.set ovfl_bit,4 | overflow
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.set unfl_bit,3 | underflow
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.set dz_bit,2 | divide by zero
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.set inex2_bit,1 | inexact result 2
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.set inex1_bit,0 | inexact result 1
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| 239 |
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.set aiop_bit,7 | accrued illegal operation
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| 240 |
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.set aovfl_bit,6 | accrued overflow
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| 241 |
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.set aunfl_bit,5 | accrued underflow
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| 242 |
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.set adz_bit,4 | accrued divide by zero
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| 243 |
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.set ainex_bit,3 | accrued inexact
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| 244 |
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| 245 |
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| FPSR individual bit masks
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| 247 |
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.set neg_mask,0x08000000
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| 248 |
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.set z_mask,0x04000000
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| 249 |
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.set inf_mask,0x02000000
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| 250 |
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.set nan_mask,0x01000000
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| 251 |
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| 252 |
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.set bsun_mask,0x00008000 |
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| 253 |
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.set snan_mask,0x00004000
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| 254 |
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.set operr_mask,0x00002000
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| 255 |
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.set ovfl_mask,0x00001000
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| 256 |
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.set unfl_mask,0x00000800
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| 257 |
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.set dz_mask,0x00000400
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| 258 |
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.set inex2_mask,0x00000200
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| 259 |
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.set inex1_mask,0x00000100
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| 260 |
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| 261 |
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.set aiop_mask,0x00000080 | accrued illegal operation
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| 262 |
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.set aovfl_mask,0x00000040 | accrued overflow
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| 263 |
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.set aunfl_mask,0x00000020 | accrued underflow
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| 264 |
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.set adz_mask,0x00000010 | accrued divide by zero
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| 265 |
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.set ainex_mask,0x00000008 | accrued inexact
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| 266 |
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| 267 |
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| FPSR combinations used in the FPSP
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| 268 |
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| 269 |
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.set dzinf_mask,inf_mask+dz_mask+adz_mask
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| 270 |
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.set opnan_mask,nan_mask+operr_mask+aiop_mask
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| 271 |
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.set nzi_mask,0x01ffffff | clears N, Z, and I
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| 272 |
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.set unfinx_mask,unfl_mask+inex2_mask+aunfl_mask+ainex_mask
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| 273 |
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.set unf2inx_mask,unfl_mask+inex2_mask+ainex_mask
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| 274 |
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.set ovfinx_mask,ovfl_mask+inex2_mask+aovfl_mask+ainex_mask
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| 275 |
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.set inx1a_mask,inex1_mask+ainex_mask
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| 276 |
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.set inx2a_mask,inex2_mask+ainex_mask
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| 277 |
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.set snaniop_mask,nan_mask+snan_mask+aiop_mask
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| 278 |
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.set naniop_mask,nan_mask+aiop_mask
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| 279 |
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.set neginf_mask,neg_mask+inf_mask
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| 280 |
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.set infaiop_mask,inf_mask+aiop_mask
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| 281 |
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.set negz_mask,neg_mask+z_mask
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| 282 |
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.set opaop_mask,operr_mask+aiop_mask
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| 283 |
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.set unfl_inx_mask,unfl_mask+aunfl_mask+ainex_mask
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| 284 |
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.set ovfl_inx_mask,ovfl_mask+aovfl_mask+ainex_mask
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| 285 |
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| 286 |
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|--------------------------------------------------------------------------
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| 287 |
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| 288 |
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| FPCR rounding modes
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| 289 |
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| 290 |
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.set x_mode,0x00 | round to extended
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| 291 |
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.set s_mode,0x40 | round to single
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| 292 |
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.set d_mode,0x80 | round to double
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| 293 |
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| 294 |
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.set rn_mode,0x00 | round nearest
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| 295 |
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.set rz_mode,0x10 | round to zero
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| 296 |
|
|
.set rm_mode,0x20 | round to minus infinity
|
| 297 |
|
|
.set rp_mode,0x30 | round to plus infinity
|
| 298 |
|
|
|
|
| 299 |
|
|
|--------------------------------------------------------------------------
|
| 300 |
|
|
|
|
| 301 |
|
|
| Miscellaneous equates
|
| 302 |
|
|
|
|
| 303 |
|
|
.set signan_bit,6 | signalling nan bit in mantissa
|
| 304 |
|
|
.set sign_bit,7
|
| 305 |
|
|
|
|
| 306 |
|
|
.set rnd_stky_bit,29 | round/sticky bit of mantissa
|
| 307 |
|
|
| this can only be used if in a data register
|
| 308 |
|
|
.set sx_mask,0x01800000 | set s and x bits in word $48
|
| 309 |
|
|
|
|
| 310 |
|
|
.set LOCAL_EX,0
|
| 311 |
|
|
.set LOCAL_SGN,2
|
| 312 |
|
|
.set LOCAL_HI,4
|
| 313 |
|
|
.set LOCAL_LO,8
|
| 314 |
|
|
.set LOCAL_GRS,12 | valid ONLY for FP_SCR1, FP_SCR2
|
| 315 |
|
|
|
|
| 316 |
|
|
|
|
| 317 |
|
|
.set norm_tag,0x00 | tag bits in {7:5} position
|
| 318 |
|
|
.set zero_tag,0x20
|
| 319 |
|
|
.set inf_tag,0x40
|
| 320 |
|
|
.set nan_tag,0x60
|
| 321 |
|
|
.set dnrm_tag,0x80
|
| 322 |
|
|
|
|
| 323 |
|
|
| fsave sizes and formats
|
| 324 |
|
|
|
|
| 325 |
|
|
.set VER_4,0x40 | fpsp compatible version numbers
|
| 326 |
|
|
| are in the $40s {$40-$4f}
|
| 327 |
|
|
.set VER_40,0x40 | original version number
|
| 328 |
|
|
.set VER_41,0x41 | revision version number
|
| 329 |
|
|
|
|
| 330 |
|
|
.set BUSY_SIZE,100 | size of busy frame
|
| 331 |
|
|
.set BUSY_FRAME,LV-BUSY_SIZE | start of busy frame
|
| 332 |
|
|
|
|
| 333 |
|
|
.set UNIMP_40_SIZE,44 | size of orig unimp frame
|
| 334 |
|
|
.set UNIMP_41_SIZE,52 | size of rev unimp frame
|
| 335 |
|
|
|
|
| 336 |
|
|
.set IDLE_SIZE,4 | size of idle frame
|
| 337 |
|
|
.set IDLE_FRAME,LV-IDLE_SIZE | start of idle frame
|
| 338 |
|
|
|
|
| 339 |
|
|
| exception vectors
|
| 340 |
|
|
|
|
| 341 |
|
|
.set TRACE_VEC,0x2024 | trace trap
|
| 342 |
|
|
.set FLINE_VEC,0x002C | real F-line
|
| 343 |
|
|
.set UNIMP_VEC,0x202C | unimplemented
|
| 344 |
|
|
.set INEX_VEC,0x00C4
|
| 345 |
|
|
|
|
| 346 |
|
|
.set dbl_thresh,0x3C01
|
| 347 |
|
|
.set sgl_thresh,0x3F81
|
| 348 |
|
|
|
|
