OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [arch/] [m68k/] [ifpsp060/] [fskeleton.S] - Blame information for rev 1777

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1623 jcastillo
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2
|MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
3
|M68000 Hi-Performance Microprocessor Division
4
|M68060 Software Package
5
|Production Release P1.00 -- October 10, 1994
6
|
7
|M68060 Software Package Copyright © 1993, 1994 Motorola Inc.  All rights reserved.
8
|
9
|THE SOFTWARE is provided on an "AS IS" basis and without warranty.
10
|To the maximum extent permitted by applicable law,
11
|MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
12
|INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
13
|and any warranty against infringement with regard to the SOFTWARE
14
|(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
15
|
16
|To the maximum extent permitted by applicable law,
17
|IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
18
|(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
19
|BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
20
|ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
21
|Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
22
|
23
|You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
24
|so long as this entire notice is retained without alteration in any modified and/or
25
|redistributed versions, and that such modified versions are clearly identified as such.
26
|No licenses are granted by implication, estoppel or otherwise under any patents
27
|or trademarks of Motorola, Inc.
28
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
29
| fskeleton.s
30
|
31
| This file contains:
32
|       (1) example "Call-out"s
33
|       (2) example package entry code
34
|       (3) example "Call-out" table
35
|
36
 
37
 
38
|################################
39
| (1) EXAMPLE CALL-OUTS         #
40
|                               #
41
| _060_fpsp_done()              #
42
| _060_real_ovfl()              #
43
| _060_real_unfl()              #
44
| _060_real_operr()             #
45
| _060_real_snan()              #
46
| _060_real_dz()                #
47
| _060_real_inex()              #
48
| _060_real_bsun()              #
49
| _060_real_fline()             #
50
| _060_real_fpu_disabled()      #
51
| _060_real_trap()              #
52
|################################
53
 
54
|
55
| _060_fpsp_done():
56
|
57
| This is the main exit point for the 68060 Floating-Point
58
| Software Package. For a normal exit, all 060FPSP routines call this
59
| routine. The operating system can do system dependent clean-up or
60
| simply execute an "rte" as with the sample code below.
61
|
62
        .global         _060_fpsp_done
63
_060_fpsp_done:
64
        rte
65
 
66
|
67
| _060_real_ovfl():
68
|
69
| This is the exit point for the 060FPSP when an enabled overflow exception
70
| is present. The routine below should point to the operating system handler
71
| for enabled overflow conditions. The exception stack frame is an overflow
72
| stack frame. The FP state frame holds the EXCEPTIONAL OPERAND.
73
|
74
| The sample routine below simply clears the exception status bit and
75
| does an "rte".
76
|
77
        .global         _060_real_ovfl
78
_060_real_ovfl:
79
        fsave           -(%sp)
80
        move.w          #0x6000,0x2(%sp)
81
        frestore        (%sp)+
82
        rte
83
 
84
|
85
| _060_real_unfl():
86
|
87
| This is the exit point for the 060FPSP when an enabled underflow exception
88
| is present. The routine below should point to the operating system handler
89
| for enabled underflow conditions. The exception stack frame is an underflow
90
| stack frame. The FP state frame holds the EXCEPTIONAL OPERAND.
91
|
92
| The sample routine below simply clears the exception status bit and
93
| does an "rte".
94
|
95
        .global         _060_real_unfl
96
_060_real_unfl:
97
        fsave           -(%sp)
98
        move.w          #0x6000,0x2(%sp)
99
        frestore        (%sp)+
100
        rte
101
 
102
|
103
| _060_real_operr():
104
|
105
| This is the exit point for the 060FPSP when an enabled operand error exception
106
| is present. The routine below should point to the operating system handler
107
| for enabled operand error exceptions. The exception stack frame is an operand error
108
| stack frame. The FP state frame holds the source operand of the faulting
109
| instruction.
110
|
111
| The sample routine below simply clears the exception status bit and
112
| does an "rte".
113
|
114
        .global         _060_real_operr
115
_060_real_operr:
116
        fsave           -(%sp)
117
        move.w          #0x6000,0x2(%sp)
118
        frestore        (%sp)+
119
        rte
120
 
121
|
122
| _060_real_snan():
123
|
124
| This is the exit point for the 060FPSP when an enabled signalling NaN exception
125
| is present. The routine below should point to the operating system handler
126
| for enabled signalling NaN exceptions. The exception stack frame is a signalling NaN
127
| stack frame. The FP state frame holds the source operand of the faulting
128
| instruction.
129
|
130
| The sample routine below simply clears the exception status bit and
131
| does an "rte".
132
|
133
        .global         _060_real_snan
134
_060_real_snan:
135
        fsave           -(%sp)
136
        move.w          #0x6000,0x2(%sp)
137
        frestore        (%sp)+
138
        rte
139
 
140
|
141
| _060_real_dz():
142
|
143
| This is the exit point for the 060FPSP when an enabled divide-by-zero exception
144
| is present. The routine below should point to the operating system handler
145
| for enabled divide-by-zero exceptions. The exception stack frame is a divide-by-zero
146
| stack frame. The FP state frame holds the source operand of the faulting
147
| instruction.
148
|
149
| The sample routine below simply clears the exception status bit and
150
| does an "rte".
151
|
152
        .global         _060_real_dz
153
_060_real_dz:
154
        fsave           -(%sp)
155
        move.w          #0x6000,0x2(%sp)
156
        frestore        (%sp)+
157
        rte
158
 
159
|
160
| _060_real_inex():
161
|
162
| This is the exit point for the 060FPSP when an enabled inexact exception
163
| is present. The routine below should point to the operating system handler
164
| for enabled inexact exceptions. The exception stack frame is an inexact
165
| stack frame. The FP state frame holds the source operand of the faulting
166
| instruction.
167
|
168
| The sample routine below simply clears the exception status bit and
169
| does an "rte".
170
|
171
        .global         _060_real_inex
172
_060_real_inex:
173
        fsave           -(%sp)
174
        move.w          #0x6000,0x2(%sp)
175
        frestore        (%sp)+
176
        rte
177
 
178
|
179
| _060_real_bsun():
180
|
181
| This is the exit point for the 060FPSP when an enabled bsun exception
182
| is present. The routine below should point to the operating system handler
183
| for enabled bsun exceptions. The exception stack frame is a bsun
184
| stack frame.
185
|
186
| The sample routine below clears the exception status bit, clears the NaN
187
| bit in the FPSR, and does an "rte". The instruction that caused the
188
| bsun will now be re-executed but with the NaN FPSR bit cleared.
189
|
190
        .global         _060_real_bsun
191
_060_real_bsun:
192
        fsave           -(%sp)
193
 
194
        fmove.l         %fpsr,-(%sp)
195
        andi.b          #0xfe,(%sp)
196
        fmove.l         (%sp)+,%fpsr
197
 
198
        add.l           #0xc,%sp
199
        rte
200
 
201
|
202
| _060_real_fline():
203
|
204
| This is the exit point for the 060FPSP when an F-Line Illegal exception is
205
| encountered. Three different types of exceptions can enter the F-Line exception
206
| vector number 11: FP Unimplemented Instructions, FP implemented instructions when
207
| the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module
208
| _fpsp_fline() distinguishes between the three and acts appropriately. F-Line
209
| Illegals branch here.
210
|
211
        .global         _060_real_fline
212
_060_real_fline:
213
        bras            _060_real_fline
214
 
215
|
216
| _060_real_fpu_disabled():
217
|
218
| This is the exit point for the 060FPSP when an FPU disabled exception is
219
| encountered. Three different types of exceptions can enter the F-Line exception
220
| vector number 11: FP Unimplemented Instructions, FP implemented instructions when
221
| the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module
222
| _fpsp_fline() distinguishes between the three and acts appropriately. FPU disabled
223
| exceptions branch here.
224
|
225
| The sample code below enables the FPU, sets the PC field in the exception stack
226
| frame to the PC of the instruction causing the exception, and does an "rte".
227
| The execution of the instruction then proceeds with an enabled floating-point
228
| unit.
229
|
230
        .global         _060_real_fpu_disabled
231
_060_real_fpu_disabled:
232
        move.l          %d0,-(%sp)              | enabled the fpu
233
        .long   0x4E7A0808
234
        |movec          pcr,d0
235
        bclr            #0x1,%d0
236
        .long   0x4E7B0808
237
        |movec          %d0,pcr
238
        move.l          (%sp)+,%d0
239
 
240
        move.l          0xc(%sp),0x2(%sp)       | set "Current PC"
241
        rte
242
 
243
|
244
| _060_real_trap():
245
|
246
| This is the exit point for the 060FPSP when an emulated "ftrapcc" instruction
247
| discovers that the trap condition is true and it should branch to the operating
248
| system handler for the trap exception vector number 7.
249
|
250
| The sample code below simply executes an "rte".
251
|
252
        .global         _060_real_trap
253
_060_real_trap:
254
        rte
255
 
256
|############################################################################
257
 
258
|#################################
259
| (2) EXAMPLE PACKAGE ENTRY CODE #
260
|#################################
261
 
262
        .global         _060_fpsp_snan
263
_060_fpsp_snan:
264
        bra.l           _FP_CALL_TOP+0x80+0x00
265
 
266
        .global         _060_fpsp_operr
267
_060_fpsp_operr:
268
        bra.l           _FP_CALL_TOP+0x80+0x08
269
 
270
        .global         _060_fpsp_ovfl
271
_060_fpsp_ovfl:
272
        bra.l           _FP_CALL_TOP+0x80+0x10
273
 
274
        .global         _060_fpsp_unfl
275
_060_fpsp_unfl:
276
        bra.l           _FP_CALL_TOP+0x80+0x18
277
 
278
        .global         _060_fpsp_dz
279
_060_fpsp_dz:
280
        bra.l           _FP_CALL_TOP+0x80+0x20
281
 
282
        .global         _060_fpsp_inex
283
_060_fpsp_inex:
284
        bra.l           _FP_CALL_TOP+0x80+0x28
285
 
286
        .global         _060_fpsp_fline
287
_060_fpsp_fline:
288
        bra.l           _FP_CALL_TOP+0x80+0x30
289
 
290
        .global         _060_fpsp_unsupp
291
_060_fpsp_unsupp:
292
        bra.l           _FP_CALL_TOP+0x80+0x38
293
 
294
        .global         _060_fpsp_effadd
295
_060_fpsp_effadd:
296
        bra.l           _FP_CALL_TOP+0x80+0x40
297
 
298
|############################################################################
299
 
300
|###############################
301
| (3) EXAMPLE CALL-OUT SECTION #
302
|###############################
303
 
304
| The size of this section MUST be 128 bytes!!!
305
 
306
        .global _FP_CALL_TOP
307
_FP_CALL_TOP:
308
        .long   _060_real_bsun          - _FP_CALL_TOP
309
        .long   _060_real_snan          - _FP_CALL_TOP
310
        .long   _060_real_operr         - _FP_CALL_TOP
311
        .long   _060_real_ovfl          - _FP_CALL_TOP
312
        .long   _060_real_unfl          - _FP_CALL_TOP
313
        .long   _060_real_dz            - _FP_CALL_TOP
314
        .long   _060_real_inex          - _FP_CALL_TOP
315
        .long   _060_real_fline         - _FP_CALL_TOP
316
        .long   _060_real_fpu_disabled  - _FP_CALL_TOP
317
        .long   _060_real_trap          - _FP_CALL_TOP
318
        .long   _060_real_trace         - _FP_CALL_TOP
319
        .long   _060_real_access        - _FP_CALL_TOP
320
        .long   _060_fpsp_done          - _FP_CALL_TOP
321
 
322
        .long   0x00000000, 0x00000000, 0x00000000
323
 
324
        .long   _060_imem_read          - _FP_CALL_TOP
325
        .long   _060_dmem_read          - _FP_CALL_TOP
326
        .long   _060_dmem_write         - _FP_CALL_TOP
327
        .long   _060_imem_read_word     - _FP_CALL_TOP
328
        .long   _060_imem_read_long     - _FP_CALL_TOP
329
        .long   _060_dmem_read_byte     - _FP_CALL_TOP
330
        .long   _060_dmem_read_word     - _FP_CALL_TOP
331
        .long   _060_dmem_read_long     - _FP_CALL_TOP
332
        .long   _060_dmem_write_byte    - _FP_CALL_TOP
333
        .long   _060_dmem_write_word    - _FP_CALL_TOP
334
        .long   _060_dmem_write_long    - _FP_CALL_TOP
335
 
336
        .long   0x00000000
337
 
338
        .long   0x00000000, 0x00000000, 0x00000000, 0x00000000
339
 
340
|############################################################################
341
 
342
| 060 FPSP KERNEL PACKAGE NEEDS TO GO HERE!!!
343
 
344
        .include "fpsp.sa"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.