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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [arch/] [or32/] [kernel/] [misc.S] - Blame information for rev 1777

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Line No. Rev Author Line
1 1624 jcastillo 
#include
2 
#include
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4 
        .text
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/*
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 * Enable interrupts
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 *      sti()
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 */
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        .global _sti
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_sti:
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        l.mfspr r3,r0,SPR_SR
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        l.ori r3,r3,(SPR_SR_IEE | SPR_SR_TEE)
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        l.mtspr r0,r3,SPR_SR
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        l.jr    r9
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        l.nop
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/*
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 * Disable interrupts
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 *      cli()
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 */
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        .global _cli
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_cli:
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        l.addi r4,r0,-1
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        l.xori r4,r4,(SPR_SR_IEE | SPR_SR_TEE)
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        l.mfspr r3,r0,SPR_SR
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        l.and r3,r3,r4
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        l.mtspr r0,r3,SPR_SR
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        l.jr    r9
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        l.nop
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/*
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 * Get 'flags' (aka status register)
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 *      __save_flags(long *ptr)
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 */
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        .global ___save_flags
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___save_flags:
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        l.mfspr r4,r0,SPR_SR
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        l.sw    0(r3),r4
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        l.jr    r9
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        l.nop
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/*
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 * Restore 'flags'
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 *      __restore_flags(long val)
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 */
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        .global ___restore_flags
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___restore_flags:
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        l.mtspr r0,r3,SPR_SR
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        l.jr    r9
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        l.nop
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/*
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 * SPR write
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 *      mtspr(long add, long val)
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 */
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        .global _mtspr
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_mtspr:
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        l.mtspr r3,r4,0
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        l.jr    r9
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        l.nop
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/*
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 * SPR read
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 *      mtspr(long add)
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 */
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        .global _mfspr
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_mfspr:
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        l.mfspr r11,r3,0
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        l.jr    r9
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        l.nop
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/*
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 * Instruction cache enable
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 *      ic_enable()
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 */
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        .global _ic_enable
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_ic_enable:
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  /* Disable IC */
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  l.mfspr r13,r0,SPR_SR
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  l.addi  r11,r0,-1
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  l.xori  r11,r11,SPR_SR_ICE
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  l.and   r11,r13,r11
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  l.mtspr r0,r11,SPR_SR
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85 
  /* Invalidate IC */
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  l.addi  r13,r0,0
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  l.addi  r11,r0,IC_SIZE
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1:
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  l.mtspr r0,r13,SPR_ICBIR
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  l.sfne  r13,r11
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  l.bf    1b
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  l.addi  r13,r13,IC_LINE
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  /* Enable IC */
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  l.mfspr r13,r0,SPR_SR
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  l.ori   r13,r13,SPR_SR_ICE
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  l.mtspr r0,r13,SPR_SR
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  l.nop
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  l.nop
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  l.nop
101 
  l.nop
102 
  l.nop
103 
 
104 
  l.jr    r9
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  l.nop
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107 
/*
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 * Instruction cache disable
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 *      ic_disable()
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 */
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        .global _ic_disable
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_ic_disable:
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  /* Disable IC */
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  l.mfspr r13,r0,SPR_SR
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  l.addi  r11,r0,-1
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  l.xori  r11,r11,SPR_SR_ICE
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  l.and   r11,r13,r11
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  l.mtspr r0,r11,SPR_SR
119 
 
120 
  l.jr    r9
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  l.nop
122 
 
123 
/*
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 * Instruction cache invalidate
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 *      ic_flush()
126 
 */
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        .global _ic_invalidate
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_ic_invalidate:
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  /* Disable IC */
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  l.mfspr r13,r0,SPR_SR
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  l.addi  r11,r0,-1
132 
  l.xori  r11,r11,SPR_SR_ICE
133 
  l.and   r11,r13,r11
134 
  l.mtspr r0,r11,SPR_SR
135 
 
136 
  /* Invalidate IC */
137 
  l.addi  r13,r0,0
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  l.addi  r11,r0,IC_SIZE
139 
1:
140 
  l.mtspr r0,r13,SPR_ICBIR
141 
  l.sfne  r13,r11
142 
  l.bf    1b
143 
  l.addi  r13,r13,IC_LINE
144 
 
145 
  /* Enable IC */
146 
  l.mfspr r13,r0,SPR_SR
147 
  l.ori   r13,r13,SPR_SR_ICE
148 
  l.mtspr r0,r13,SPR_SR
149 
  l.nop
150 
  l.nop
151 
  l.nop
152 
  l.nop
153 
  l.nop
154 
 
155 
  l.jr    r9
156 
  l.nop
157 
 
158 
/*
159 
 * Data cache enable
160 
 *      dc_enable()
161 
 */
162 
        .global _dc_enable
163 
_dc_enable:
164 
  /* Disable DC */
165 
  l.mfspr r13,r0,SPR_SR
166 
  l.addi  r11,r0,-1
167 
  l.xori  r11,r11,SPR_SR_DCE
168 
  l.and   r11,r13,r11
169 
  l.mtspr r0,r11,SPR_SR
170 
 
171 
  /* Flush DC */
172 
  l.addi  r13,r0,0
173 
  l.addi  r11,r0,DC_SIZE
174 
1:
175 
  l.mtspr r0,r13,SPR_DCBIR
176 
  l.sfne  r13,r11
177 
  l.bf    1b
178 
  l.addi  r13,r13,DC_LINE
179 
 
180 
  /* Enable DC */
181 
  l.mfspr r13,r0,SPR_SR
182 
  l.ori   r13,r13,SPR_SR_DCE
183 
  l.mtspr r0,r13,SPR_SR
184 
 
185 
  l.jr    r9
186 
  l.nop
187 
 
188 
/*
189 
 * Data cache disable
190 
 *      dc_disable()
191 
 */
192 
        .global _dc_disable
193 
_dc_disable:
194 
  /* Disable DC */
195 
  l.mfspr r13,r0,SPR_SR
196 
  l.addi  r11,r0,-1
197 
  l.xori  r11,r11,SPR_SR_DCE
198 
  l.and   r11,r13,r11
199 
  l.mtspr r0,r11,SPR_SR
200 
 
201 
  l.jr    r9
202 
  l.nop
203 
 
204 
/*
205 
 * Invalidate data cache line
206 
 *      dc_line_invalidate(long ph_add)
207 
 */
208 
        .global _dc_line_invalidate
209 
_dc_line_invalidate:
210 
  l.mfspr r4,r0,SPR_SR
211 
  l.addi  r5,r0,-1
212 
  l.xori  r5,r5,SPR_SR_DCE
213 
  l.and   r5,r4,r5
214 
  l.mtspr r0,r5,SPR_SR
215 
  l.mtspr r0,r3,SPR_DCBIR
216 
  l.mtspr r0,r4,SPR_SR
217 
  l.jr    r9
218 
  l.nop
219 
 
220 
/*
221 
 * Data MMU enable
222 
 *      dmmu_enable()
223 
 */
224 
        .global _dmmu_enable
225 
_dmmu_enable:
226 
  /* Invalidate all sets */
227 
  l.addi  r11,r0,DMMU_SET_NB
228 
  l.addi  r13,r0,0
229 
1:
230 
  l.mtspr r13,r0,SPR_DTLBMR_BASE(0)
231 
  l.addi  r11,r11,-1
232 
  l.sfeqi r11,0
233 
  l.bnf   1b
234 
  l.addi  r13,r13,1
235 
  l.mfspr r11,r0,SPR_SR
236 
  l.ori   r11,r11,SPR_SR_DME
237 
  l.mtspr r0,r11,SPR_SR
238 
  l.jr    r9
239 
  l.nop
240 
 
241 
/*
242 
 * Instruction MMU enable
243 
 *      immu_enable()
244 
 */
245 
        .global _immu_enable
246 
_immu_enable:
247 
  /* Invalidate all sets */
248 
  l.addi  r11,r0,IMMU_SET_NB
249 
  l.addi  r13,r0,0
250 
1:
251 
  l.mtspr r13,r0,SPR_ITLBMR_BASE(0)
252 
  l.addi  r11,r11,-1
253 
  l.sfeqi r11,0
254 
  l.bnf   1b
255 
  l.addi  r13,r13,1
256 
  l.mfspr r11,r0,SPR_SR
257 
  l.ori   r11,r11,SPR_SR_IME
258 
  l.mtspr r0,r11,SPR_SR
259 
  l.nop
260 
  l.nop
261 
  l.nop
262 
  l.nop
263 
  l.jr    r9
264 
  l.nop
265 
 
266 
 /*
267 
 * Print utility
268 
 *      __print(const char *fmt, ...)
269 
 */
270 
        .global __print
271 
__print:
272 
        l.lwz   r3,0(r1)
273 
        l.addi  r4,r1,4
274 
#       l.sys   202
275 
  l.nop 3
276 
        l.jr    r9
277 
        l.nop
278 
 

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