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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [drivers/] [isdn/] [hisax/] [isac.c] - Blame information for rev 1777

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/* $Id: isac.c,v 1.1 2005-12-20 10:17:01 jcastillo Exp $
 
 * isac.c   ISAC specific routines
 *
 * Author       Karsten Keil (keil@isdn4linux.de)
 *
 *              This file is (c) under GNU PUBLIC LICENSE
 *              For changes and modifications please read
 *              ../../../Documentation/isdn/HiSax.cert
 *
 * $Log: not supported by cvs2svn $
 * Revision 1.1.1.1  2001/09/10 07:44:18  simons
 * Initial import
 *
 * Revision 1.1.1.1  2001/07/02 17:58:32  simons
 * Initial revision
 *
 * Revision 1.7.2.9  1998/11/03 00:06:41  keil
 * certification related changes
 * fixed logging for smaller stack use
 *
 * Revision 1.7.2.8  1998/09/27 13:06:18  keil
 * Apply most changes from 2.1.X (HiSax 3.1)
 *
 * Revision 1.7.2.7  1998/05/27 18:05:38  keil
 * HiSax 3.0
 *
 * Revision 1.7.2.6  1998/04/08 21:57:31  keil
 * New init code to fix problems during init if S0 is allready activ
 *
 * Revision 1.7.2.5  1998/03/07 23:15:24  tsbogend
 * made HiSax working on Linux/Alpha
 *
 * Revision 1.7.2.4  1998/02/09 11:24:06  keil
 * New leased line support (Read README.HiSax!)
 *
 * Revision 1.7.2.3  1998/01/11 22:58:55  keil
 * new setstack interface
 *
 * Revision 1.7.2.2  1997/11/15 18:54:23  keil
 * cosmetics
 *
 * Revision 1.7.2.1  1997/10/17 22:10:49  keil
 * new files on 2.0
 *
 * Revision 1.6  1997/08/15 17:47:08  keil
 * avoid oops because a uninitialised timer
 *
 * Revision 1.5  1997/08/07 17:48:49  keil
 * fix wrong parenthesis
 *
 * Revision 1.4  1997/07/30 17:11:59  keil
 * fixed Timer3
 *
 * Revision 1.3  1997/07/27 21:37:40  keil
 * T3 implemented; supervisor l1timer; B-channel TEST_LOOP
 *
 * Revision 1.2  1997/06/26 11:16:15  keil
 * first version
 *
 *
 */
 
#define __NO_VERSION__
#include "hisax.h"
#include "isac.h"
#include "isdnl1.h"
#include <linux/interrupt.h>
 
#define DBUSY_TIMER_VALUE 80
#define ARCOFI_USE 1
 
static char *ISACVer[] HISAX_INITDATA =
{"2086/2186 V1.1", "2085 B1", "2085 B2",
 "2085 V2.3"};
 
void
ISACVersion(struct IsdnCardState *cs, char *s)
{
        int val;
 
        val = cs->readisac(cs, ISAC_RBCH);
        printk(KERN_INFO "%s ISAC version (%x): %s\n", s, val, ISACVer[(val >> 5) & 3]);
}
 
static void
ph_command(struct IsdnCardState *cs, unsigned int command)
{
        if (cs->debug & L1_DEB_ISAC)
                debugl1(cs, "ph_command %x", command);
        cs->writeisac(cs, ISAC_CIX0, (command << 2) | 3);
}
 
 
static void
isac_new_ph(struct IsdnCardState *cs)
{
        switch (cs->ph_state) {
                case (ISAC_IND_RS):
                case (ISAC_IND_EI):
                        ph_command(cs, ISAC_CMD_DUI);
                        l1_msg(cs, HW_RESET | INDICATION, NULL);
                        break;
                case (ISAC_IND_DID):
                        l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);
                        break;
                case (ISAC_IND_DR):
                        l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
                        break;
                case (ISAC_IND_PU):
                        l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
                        break;
                case (ISAC_IND_RSY):
                        l1_msg(cs, HW_RSYNC | INDICATION, NULL);
                        break;
                case (ISAC_IND_ARD):
                        l1_msg(cs, HW_INFO2 | INDICATION, NULL);
                        break;
                case (ISAC_IND_AI8):
                        l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
                        break;
                case (ISAC_IND_AI10):
                        l1_msg(cs, HW_INFO4_P10 | INDICATION, NULL);
                        break;
                default:
                        break;
        }
}
 
static void
isac_bh(struct IsdnCardState *cs)
{
        struct PStack *stptr;
 
        if (!cs)
                return;
        if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
                if (cs->debug)
                        debugl1(cs, "D-Channel Busy cleared");
                stptr = cs->stlist;
                while (stptr != NULL) {
                        stptr->l1.l1l2(stptr, PH_PAUSE | CONFIRM, NULL);
                        stptr = stptr->next;
                }
        }
        if (test_and_clear_bit(D_L1STATECHANGE, &cs->event))
                isac_new_ph(cs);
        if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
                DChannel_proc_rcv(cs);
        if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
                DChannel_proc_xmt(cs);
        if (test_and_clear_bit(D_RX_MON0, &cs->event))
                test_and_set_bit(HW_MON0_RX_END, &cs->HW_Flags);
        if (test_and_clear_bit(D_RX_MON1, &cs->event))
                test_and_set_bit(HW_MON1_RX_END, &cs->HW_Flags);
        if (test_and_clear_bit(D_TX_MON0, &cs->event))
                test_and_set_bit(HW_MON0_TX_END, &cs->HW_Flags);
        if (test_and_clear_bit(D_TX_MON1, &cs->event))
                test_and_set_bit(HW_MON1_TX_END, &cs->HW_Flags);
}
 
void
isac_empty_fifo(struct IsdnCardState *cs, int count)
{
        u_char *ptr;
        long flags;
 
        if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
                debugl1(cs, "isac_empty_fifo");
 
        if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
                if (cs->debug & L1_DEB_WARN)
                        debugl1(cs, "isac_empty_fifo overrun %d",
                                cs->rcvidx + count);
                cs->writeisac(cs, ISAC_CMDR, 0x80);
                cs->rcvidx = 0;
                return;
        }
        ptr = cs->rcvbuf + cs->rcvidx;
        cs->rcvidx += count;
        save_flags(flags);
        cli();
        cs->readisacfifo(cs, ptr, count);
        cs->writeisac(cs, ISAC_CMDR, 0x80);
        restore_flags(flags);
        if (cs->debug & L1_DEB_ISAC_FIFO) {
                char *t = cs->dlog;
 
                t += sprintf(t, "isac_empty_fifo cnt %d", count);
                QuickHex(t, ptr, count);
                debugl1(cs, cs->dlog);
        }
}
 
static void
isac_fill_fifo(struct IsdnCardState *cs)
{
        int count, more;
        u_char *ptr;
        long flags;
 
        if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
                debugl1(cs, "isac_fill_fifo");
 
        if (!cs->tx_skb)
                return;
 
        count = cs->tx_skb->len;
        if (count <= 0)
                return;
 
        more = 0;
        if (count > 32) {
                more = !0;
                count = 32;
        }
        save_flags(flags);
        cli();
        ptr = cs->tx_skb->data;
        skb_pull(cs->tx_skb, count);
        cs->tx_cnt += count;
        cs->writeisacfifo(cs, ptr, count);
        cs->writeisac(cs, ISAC_CMDR, more ? 0x8 : 0xa);
        restore_flags(flags);
        if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
                debugl1(cs, "isac_fill_fifo dbusytimer running");
                del_timer(&cs->dbusytimer);
        }
        init_timer(&cs->dbusytimer);
        cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
        add_timer(&cs->dbusytimer);
        if (cs->debug & L1_DEB_ISAC_FIFO) {
                char *t = cs->dlog;
 
                t += sprintf(t, "isac_fill_fifo cnt %d", count);
                QuickHex(t, ptr, count);
                debugl1(cs, cs->dlog);
        }
}
 
void
isac_sched_event(struct IsdnCardState *cs, int event)
{
        test_and_set_bit(event, &cs->event);
        queue_task(&cs->tqueue, &tq_immediate);
        mark_bh(IMMEDIATE_BH);
}
 
void
isac_interrupt(struct IsdnCardState *cs, u_char val)
{
        u_char exval, v1;
        struct sk_buff *skb;
        unsigned int count;
        long flags;
 
        if (cs->debug & L1_DEB_ISAC)
                debugl1(cs, "ISAC interrupt %x", val);
        if (val & 0x80) {       /* RME */
                exval = cs->readisac(cs, ISAC_RSTA);
                if ((exval & 0x70) != 0x20) {
                        if (exval & 0x40)
                                if (cs->debug & L1_DEB_WARN)
                                        debugl1(cs, "ISAC RDO");
                        if (!(exval & 0x20))
                                if (cs->debug & L1_DEB_WARN)
                                        debugl1(cs, "ISAC CRC error");
                        cs->writeisac(cs, ISAC_CMDR, 0x80);
                } else {
                        count = cs->readisac(cs, ISAC_RBCL) & 0x1f;
                        if (count == 0)
                                count = 32;
                        isac_empty_fifo(cs, count);
                        save_flags(flags);
                        cli();
                        if ((count = cs->rcvidx) > 0) {
                                cs->rcvidx = 0;
                                if (!(skb = alloc_skb(count, GFP_ATOMIC)))
                                        printk(KERN_WARNING "HiSax: D receive out of memory\n");
                                else {
                                        SET_SKB_FREE(skb);
                                        memcpy(skb_put(skb, count), cs->rcvbuf, count);
                                        skb_queue_tail(&cs->rq, skb);
                                }
                        }
                        restore_flags(flags);
                }
                cs->rcvidx = 0;
                isac_sched_event(cs, D_RCVBUFREADY);
        }
        if (val & 0x40) {       /* RPF */
                isac_empty_fifo(cs, 32);
        }
        if (val & 0x20) {       /* RSC */
                /* never */
                if (cs->debug & L1_DEB_WARN)
                        debugl1(cs, "ISAC RSC interrupt");
        }
        if (val & 0x10) {       /* XPR */
                if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
                        del_timer(&cs->dbusytimer);
                if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
                        isac_sched_event(cs, D_CLEARBUSY);
                if (cs->tx_skb) {
                        if (cs->tx_skb->len) {
                                isac_fill_fifo(cs);
                                goto afterXPR;
                        } else {
                                dev_kfree_skb(cs->tx_skb, FREE_WRITE);
                                cs->tx_cnt = 0;
                                cs->tx_skb = NULL;
                        }
                }
                if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
                        cs->tx_cnt = 0;
                        isac_fill_fifo(cs);
                } else
                        isac_sched_event(cs, D_XMTBUFREADY);
        }
      afterXPR:
        if (val & 0x04) {       /* CISQ */
                exval = cs->readisac(cs, ISAC_CIR0);
                if (cs->debug & L1_DEB_ISAC)
                        debugl1(cs, "ISAC CIR0 %02X", exval );
                if (exval & 2) {
                        cs->ph_state = (exval >> 2) & 0xf;
                        if (cs->debug & L1_DEB_ISAC)
                                debugl1(cs, "ph_state change %x", cs->ph_state);
                        isac_sched_event(cs, D_L1STATECHANGE);
                }
                if (exval & 1) {
                        exval = cs->readisac(cs, ISAC_CIR1);
                        if (cs->debug & L1_DEB_ISAC)
                                debugl1(cs, "ISAC CIR1 %02X", exval );
                }
        }
        if (val & 0x02) {       /* SIN */
                /* never */
                if (cs->debug & L1_DEB_WARN)
                        debugl1(cs, "ISAC SIN interrupt");
        }
        if (val & 0x01) {       /* EXI */
                exval = cs->readisac(cs, ISAC_EXIR);
                if (cs->debug & L1_DEB_WARN)
                        debugl1(cs, "ISAC EXIR %02x", exval);
                if (exval & 0x04) {
                        v1 = cs->readisac(cs, ISAC_MOSR);
                        if (cs->debug & L1_DEB_MONITOR)
                                debugl1(cs, "ISAC MOSR %02x", v1);
#if ARCOFI_USE
                        if (v1 & 0x08) {
                                if (!cs->mon_rx) {
                                        if (!(cs->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
                                                if (cs->debug & L1_DEB_WARN)
                                                        debugl1(cs, "ISAC MON RX out of memory!");
                                                cs->mocr &= 0xf0;
                                                cs->mocr |= 0x0a;
                                                cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                                goto afterMONR0;
                                        } else
                                                cs->mon_rxp = 0;
                                }
                                if (cs->mon_rxp >= MAX_MON_FRAME) {
                                        cs->mocr &= 0xf0;
                                        cs->mocr |= 0x0a;
                                        cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                        cs->mon_rxp = 0;
                                        if (cs->debug & L1_DEB_WARN)
                                                debugl1(cs, "ISAC MON RX overflow!");
                                        goto afterMONR0;
                                }
                                cs->mon_rx[cs->mon_rxp++] = cs->readisac(cs, ISAC_MOR0);
                                if (cs->debug & L1_DEB_MONITOR)
                                        debugl1(cs, "ISAC MOR0 %02x", cs->mon_rx[cs->mon_rxp -1]);
                                if (cs->mon_rxp == 1) {
                                        cs->mocr |= 0x04;
                                        cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                }
                        }
                      afterMONR0:
                        if (v1 & 0x80) {
                                if (!cs->mon_rx) {
                                        if (!(cs->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {
                                                if (cs->debug & L1_DEB_WARN)
                                                        debugl1(cs, "ISAC MON RX out of memory!");
                                                cs->mocr &= 0x0f;
                                                cs->mocr |= 0xa0;
                                                cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                                goto afterMONR1;
                                        } else
                                                cs->mon_rxp = 0;
                                }
                                if (cs->mon_rxp >= MAX_MON_FRAME) {
                                        cs->mocr &= 0x0f;
                                        cs->mocr |= 0xa0;
                                        cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                        cs->mon_rxp = 0;
                                        if (cs->debug & L1_DEB_WARN)
                                                debugl1(cs, "ISAC MON RX overflow!");
                                        goto afterMONR1;
                                }
                                cs->mon_rx[cs->mon_rxp++] = cs->readisac(cs, ISAC_MOR1);
                                if (cs->debug & L1_DEB_MONITOR)
                                        debugl1(cs, "ISAC MOR1 %02x", cs->mon_rx[cs->mon_rxp -1]);
                                cs->mocr |= 0x40;
                                cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                        }
                      afterMONR1:
                        if (v1 & 0x04) {
                                cs->mocr &= 0xf0;
                                cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                cs->mocr |= 0x0a;
                                cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                test_and_set_bit(HW_MON0_RX_END, &cs->HW_Flags);
                        }
                        if (v1 & 0x40) {
                                cs->mocr &= 0x0f;
                                cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                cs->mocr |= 0xa0;
                                cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                test_and_set_bit(HW_MON1_RX_END, &cs->HW_Flags);
                        }
                        if (v1 & 0x02) {
                                if ((!cs->mon_tx) || (cs->mon_txc &&
                                        (cs->mon_txp >= cs->mon_txc) &&
                                        !(v1 & 0x08))) {
                                        cs->mocr &= 0xf0;
                                        cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                        cs->mocr |= 0x0a;
                                        cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                        if (cs->mon_txc &&
                                                (cs->mon_txp >= cs->mon_txc))
                                                test_and_set_bit(HW_MON0_TX_END, &cs->HW_Flags);
                                        goto AfterMOX0;
                                }
                                if (cs->mon_txc && (cs->mon_txp >= cs->mon_txc)) {
                                        test_and_set_bit(HW_MON0_TX_END, &cs->HW_Flags);
                                        goto AfterMOX0;
                                }
                                cs->writeisac(cs, ISAC_MOX0,
                                        cs->mon_tx[cs->mon_txp++]);
                                if (cs->debug & L1_DEB_MONITOR)
                                        debugl1(cs, "ISAC %02x -> MOX0", cs->mon_tx[cs->mon_txp -1]);
                        }
                      AfterMOX0:
                        if (v1 & 0x20) {
                                if ((!cs->mon_tx) || (cs->mon_txc &&
                                        (cs->mon_txp >= cs->mon_txc) &&
                                        !(v1 & 0x80))) {
                                        cs->mocr &= 0x0f;
                                        cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                        cs->mocr |= 0xa0;
                                        cs->writeisac(cs, ISAC_MOCR, cs->mocr);
                                        if (cs->mon_txc &&
                                                (cs->mon_txp >= cs->mon_txc))
                                                test_and_set_bit(HW_MON1_TX_END, &cs->HW_Flags);
                                        goto AfterMOX1;
                                }
                                if (cs->mon_txc && (cs->mon_txp >= cs->mon_txc)) {
                                        test_and_set_bit(HW_MON1_TX_END, &cs->HW_Flags);
                                        goto AfterMOX1;
                                }
                                cs->writeisac(cs, ISAC_MOX1,
                                        cs->mon_tx[cs->mon_txp++]);
                                if (cs->debug & L1_DEB_MONITOR)
                                        debugl1(cs, "ISAC %02x -> MOX1", cs->mon_tx[cs->mon_txp -1]);
                        }
                      AfterMOX1:
#endif
                }
        }
}
 
static void
ISAC_l1hw(struct PStack *st, int pr, void *arg)
{
        struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
        struct sk_buff *skb = arg;
        int  val;
 
        switch (pr) {
                case (PH_DATA |REQUEST):
                        if (cs->debug & DEB_DLOG_HEX)
                                LogFrame(cs, skb->data, skb->len);
                        if (cs->debug & DEB_DLOG_VERBOSE)
                                dlogframe(cs, skb, 0);
                        if (cs->tx_skb) {
                                skb_queue_tail(&cs->sq, skb);
#ifdef L2FRAME_DEBUG            /* psa */
                                if (cs->debug & L1_DEB_LAPD)
                                        Logl2Frame(cs, skb, "PH_DATA Queued", 0);
#endif
                        } else {
                                cs->tx_skb = skb;
                                cs->tx_cnt = 0;
#ifdef L2FRAME_DEBUG            /* psa */
                                if (cs->debug & L1_DEB_LAPD)
                                        Logl2Frame(cs, skb, "PH_DATA", 0);
#endif
                                isac_fill_fifo(cs);
                        }
                        break;
                case (PH_PULL |INDICATION):
                        if (cs->tx_skb) {
                                if (cs->debug & L1_DEB_WARN)
                                        debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
                                skb_queue_tail(&cs->sq, skb);
                                break;
                        }
                        if (cs->debug & DEB_DLOG_HEX)
                                LogFrame(cs, skb->data, skb->len);
                        if (cs->debug & DEB_DLOG_VERBOSE)
                                dlogframe(cs, skb, 0);
                        cs->tx_skb = skb;
                        cs->tx_cnt = 0;
#ifdef L2FRAME_DEBUG            /* psa */
                        if (cs->debug & L1_DEB_LAPD)
                                Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
#endif
                        isac_fill_fifo(cs);
                        break;
                case (PH_PULL | REQUEST):
#ifdef L2FRAME_DEBUG            /* psa */
                        if (cs->debug & L1_DEB_LAPD)
                                debugl1(cs, "-> PH_REQUEST_PULL");
#endif
                        if (!cs->tx_skb) {
                                test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
                                st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
                        } else
                                test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
                        break;
                case (HW_RESET | REQUEST):
                        if ((cs->ph_state == ISAC_IND_EI) ||
                                (cs->ph_state == ISAC_IND_DR) ||
                                (cs->ph_state == ISAC_IND_RS))
                                ph_command(cs, ISAC_CMD_TIM);
                        else
                                ph_command(cs, ISAC_CMD_RS);
                        break;
                case (HW_ENABLE | REQUEST):
                        ph_command(cs, ISAC_CMD_TIM);
                        break;
                case (HW_INFO3 | REQUEST):
                        ph_command(cs, ISAC_CMD_AR8);
                        break;
                case (HW_TESTLOOP | REQUEST):
                        val = 0;
                        if (1 & (long) arg)
                                val |= 0x0c;
                        if (2 & (long) arg)
                                val |= 0x3;
                        if (test_bit(HW_IOM1, &cs->HW_Flags)) {
                                /* IOM 1 Mode */
                                if (!val) {
                                        cs->writeisac(cs, ISAC_SPCR, 0xa);
                                        cs->writeisac(cs, ISAC_ADF1, 0x2);
                                } else {
                                        cs->writeisac(cs, ISAC_SPCR, val);
                                        cs->writeisac(cs, ISAC_ADF1, 0xa);
                                }
                        } else {
                                /* IOM 2 Mode */
                                cs->writeisac(cs, ISAC_SPCR, val);
                                if (val)
                                        cs->writeisac(cs, ISAC_ADF1, 0x8);
                                else
                                        cs->writeisac(cs, ISAC_ADF1, 0x0);
                        }
                        break;
                case (HW_DEACTIVATE | RESPONSE):
                        discard_queue(&cs->rq);
                        discard_queue(&cs->sq);
                        if (cs->tx_skb) {
                                dev_kfree_skb(cs->tx_skb, FREE_WRITE);
                                cs->tx_skb = NULL;
                        }
                        if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
                                del_timer(&cs->dbusytimer);
                        if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
                                isac_sched_event(cs, D_CLEARBUSY);
                        break;
                default:
                        if (cs->debug & L1_DEB_WARN)
                                debugl1(cs, "isac_l1hw unknown %04x", pr);
                        break;
        }
}
 
void
setstack_isac(struct PStack *st, struct IsdnCardState *cs)
{
        st->l1.l1hw = ISAC_l1hw;
}
 
static void
dbusy_timer_handler(struct IsdnCardState *cs)
{
        struct PStack *stptr;
        int     val;
 
        if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
                if (cs->debug) {
                        debugl1(cs, "D-Channel Busy");
                        val = cs->readisac(cs, ISAC_RBCH);
                        if (val & ISAC_RBCH_XAC)
                                debugl1(cs, "ISAC XAC");
                        else
                                debugl1(cs, "ISAC No XAC");
                }
                test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
                stptr = cs->stlist;
 
                while (stptr != NULL) {
                        stptr->l1.l1l2(stptr, PH_PAUSE | INDICATION, NULL);
                        stptr = stptr->next;
                }
        }
}
 
HISAX_INITFUNC(void
initisac(struct IsdnCardState *cs))
{
        cs->tqueue.routine = (void *) (void *) isac_bh;
        cs->setstack_d = setstack_isac;
        cs->dbusytimer.function = (void *) dbusy_timer_handler;
        cs->dbusytimer.data = (long) cs;
        init_timer(&cs->dbusytimer);
        cs->writeisac(cs, ISAC_MASK, 0xff);
        cs->mocr = 0xaa;
        if (test_bit(HW_IOM1, &cs->HW_Flags)) {
                /* IOM 1 Mode */
                cs->writeisac(cs, ISAC_ADF2, 0x0);
                cs->writeisac(cs, ISAC_SPCR, 0xa);
                cs->writeisac(cs, ISAC_ADF1, 0x2);
                cs->writeisac(cs, ISAC_STCR, 0x70);
                cs->writeisac(cs, ISAC_MODE, 0xc9);
        } else {
                /* IOM 2 Mode */
                cs->writeisac(cs, ISAC_ADF2, 0x80);
                cs->writeisac(cs, ISAC_SQXR, 0x2f);
                cs->writeisac(cs, ISAC_SPCR, 0x00);
                cs->writeisac(cs, ISAC_STCR, 0x70);
                cs->writeisac(cs, ISAC_MODE, 0xc9);
                cs->writeisac(cs, ISAC_TIMR, 0x00);
                cs->writeisac(cs, ISAC_ADF1, 0x00);
        }
        ph_command(cs, ISAC_CMD_RS);
        cs->writeisac(cs, ISAC_MASK, 0x0);
}
 
HISAX_INITFUNC(void
clear_pending_isac_ints(struct IsdnCardState *cs))
{
        int val, eval;
 
        val = cs->readisac(cs, ISAC_STAR);
        debugl1(cs, "ISAC STAR %x", val);
        val = cs->readisac(cs, ISAC_MODE);
        debugl1(cs, "ISAC MODE %x", val);
        val = cs->readisac(cs, ISAC_ADF2);
        debugl1(cs, "ISAC ADF2 %x", val);
        val = cs->readisac(cs, ISAC_ISTA);
        debugl1(cs, "ISAC ISTA %x", val);
        if (val & 0x01) {
                eval = cs->readisac(cs, ISAC_EXIR);
                debugl1(cs, "ISAC EXIR %x", eval);
        }
        val = cs->readisac(cs, ISAC_CIR0);
        debugl1(cs, "ISAC CIR0 %x", val);
        cs->ph_state = (val >> 2) & 0xf;
        isac_sched_event(cs, D_L1STATECHANGE);
        /* Disable all IRQ */
        cs->writeisac(cs, ISAC_MASK, 0xFF);
}

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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [drivers/] [isdn/] [hisax/] [isac.c] - Blame information for rev 1777

Line No.	Rev	Author	Line
1	1626	jcastillo	`/* $Id: isac.c,v 1.1 2005-12-20 10:17:01 jcastillo Exp $`
2
3			`* isac.c ISAC specific routines`
4			`*`
5			`* Author Karsten Keil (keil@isdn4linux.de)`
6			`*`
7			`* This file is (c) under GNU PUBLIC LICENSE`
8			`* For changes and modifications please read`
9			`* ../../../Documentation/isdn/HiSax.cert`
10			`*`
11			`* $Log: not supported by cvs2svn $`
12			`* Revision 1.1.1.1 2001/09/10 07:44:18 simons`
13			`* Initial import`
14			`*`
15			`* Revision 1.1.1.1 2001/07/02 17:58:32 simons`
16			`* Initial revision`
17			`*`
18			`* Revision 1.7.2.9 1998/11/03 00:06:41 keil`
19			`* certification related changes`
20			`* fixed logging for smaller stack use`
21			`*`
22			`* Revision 1.7.2.8 1998/09/27 13:06:18 keil`
23			`* Apply most changes from 2.1.X (HiSax 3.1)`
24			`*`
25			`* Revision 1.7.2.7 1998/05/27 18:05:38 keil`
26			`* HiSax 3.0`
27			`*`
28			`* Revision 1.7.2.6 1998/04/08 21:57:31 keil`
29			`* New init code to fix problems during init if S0 is allready activ`
30			`*`
31			`* Revision 1.7.2.5 1998/03/07 23:15:24 tsbogend`
32			`* made HiSax working on Linux/Alpha`
33			`*`
34			`* Revision 1.7.2.4 1998/02/09 11:24:06 keil`
35			`* New leased line support (Read README.HiSax!)`
36			`*`
37			`* Revision 1.7.2.3 1998/01/11 22:58:55 keil`
38			`* new setstack interface`
39			`*`
40			`* Revision 1.7.2.2 1997/11/15 18:54:23 keil`
41			`* cosmetics`
42			`*`
43			`* Revision 1.7.2.1 1997/10/17 22:10:49 keil`
44			`* new files on 2.0`
45			`*`
46			`* Revision 1.6 1997/08/15 17:47:08 keil`
47			`* avoid oops because a uninitialised timer`
48			`*`
49			`* Revision 1.5 1997/08/07 17:48:49 keil`
50			`* fix wrong parenthesis`
51			`*`
52			`* Revision 1.4 1997/07/30 17:11:59 keil`
53			`* fixed Timer3`
54			`*`
55			`* Revision 1.3 1997/07/27 21:37:40 keil`
56			`* T3 implemented; supervisor l1timer; B-channel TEST_LOOP`
57			`*`
58			`* Revision 1.2 1997/06/26 11:16:15 keil`
59			`* first version`
60			`*`
61			`*`
62			`*/`
63
64			`#define __NO_VERSION__`
65			`#include "hisax.h"`
66			`#include "isac.h"`
67			`#include "isdnl1.h"`
68			`#include <linux/interrupt.h>`
69
70			`#define DBUSY_TIMER_VALUE 80`
71			`#define ARCOFI_USE 1`
72
73			`static char *ISACVer[] HISAX_INITDATA =`
74			`{"2086/2186 V1.1", "2085 B1", "2085 B2",`
75			`"2085 V2.3"};`
76
77			`void`
78			`ISACVersion(struct IsdnCardState cs, char s)`
79			`{`
80			`int val;`
81
82			`val = cs->readisac(cs, ISAC_RBCH);`
83			`printk(KERN_INFO "%s ISAC version (%x): %s\n", s, val, ISACVer[(val >> 5) & 3]);`
84			`}`
85
86			`static void`
87			`ph_command(struct IsdnCardState *cs, unsigned int command)`
88			`{`
89			`if (cs->debug & L1_DEB_ISAC)`
90			`debugl1(cs, "ph_command %x", command);`
91			`cs->writeisac(cs, ISAC_CIX0, (command << 2) \| 3);`
92			`}`
93
94
95			`static void`
96			`isac_new_ph(struct IsdnCardState *cs)`
97			`{`
98			`switch (cs->ph_state) {`
99			`case (ISAC_IND_RS):`
100			`case (ISAC_IND_EI):`
101			`ph_command(cs, ISAC_CMD_DUI);`
102			`l1_msg(cs, HW_RESET \| INDICATION, NULL);`
103			`break;`
104			`case (ISAC_IND_DID):`
105			`l1_msg(cs, HW_DEACTIVATE \| CONFIRM, NULL);`
106			`break;`
107			`case (ISAC_IND_DR):`
108			`l1_msg(cs, HW_DEACTIVATE \| INDICATION, NULL);`
109			`break;`
110			`case (ISAC_IND_PU):`
111			`l1_msg(cs, HW_POWERUP \| CONFIRM, NULL);`
112			`break;`
113			`case (ISAC_IND_RSY):`
114			`l1_msg(cs, HW_RSYNC \| INDICATION, NULL);`
115			`break;`
116			`case (ISAC_IND_ARD):`
117			`l1_msg(cs, HW_INFO2 \| INDICATION, NULL);`
118			`break;`
119			`case (ISAC_IND_AI8):`
120			`l1_msg(cs, HW_INFO4_P8 \| INDICATION, NULL);`
121			`break;`
122			`case (ISAC_IND_AI10):`
123			`l1_msg(cs, HW_INFO4_P10 \| INDICATION, NULL);`
124			`break;`
125			`default:`
126			`break;`
127			`}`
128			`}`
129
130			`static void`
131			`isac_bh(struct IsdnCardState *cs)`
132			`{`
133			`struct PStack *stptr;`
134
135			`if (!cs)`
136			`return;`
137			`if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {`
138			`if (cs->debug)`
139			`debugl1(cs, "D-Channel Busy cleared");`
140			`stptr = cs->stlist;`
141			`while (stptr != NULL) {`
142			`stptr->l1.l1l2(stptr, PH_PAUSE \| CONFIRM, NULL);`
143			`stptr = stptr->next;`
144			`}`
145			`}`
146			`if (test_and_clear_bit(D_L1STATECHANGE, &cs->event))`
147			`isac_new_ph(cs);`
148			`if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))`
149			`DChannel_proc_rcv(cs);`
150			`if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))`
151			`DChannel_proc_xmt(cs);`
152			`if (test_and_clear_bit(D_RX_MON0, &cs->event))`
153			`test_and_set_bit(HW_MON0_RX_END, &cs->HW_Flags);`
154			`if (test_and_clear_bit(D_RX_MON1, &cs->event))`
155			`test_and_set_bit(HW_MON1_RX_END, &cs->HW_Flags);`
156			`if (test_and_clear_bit(D_TX_MON0, &cs->event))`
157			`test_and_set_bit(HW_MON0_TX_END, &cs->HW_Flags);`
158			`if (test_and_clear_bit(D_TX_MON1, &cs->event))`
159			`test_and_set_bit(HW_MON1_TX_END, &cs->HW_Flags);`
160			`}`
161
162			`void`
163			`isac_empty_fifo(struct IsdnCardState *cs, int count)`
164			`{`
165			`u_char *ptr;`
166			`long flags;`
167
168			`if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))`
169			`debugl1(cs, "isac_empty_fifo");`
170
171			`if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {`
172			`if (cs->debug & L1_DEB_WARN)`
173			`debugl1(cs, "isac_empty_fifo overrun %d",`
174			`cs->rcvidx + count);`
175			`cs->writeisac(cs, ISAC_CMDR, 0x80);`
176			`cs->rcvidx = 0;`
177			`return;`
178			`}`
179			`ptr = cs->rcvbuf + cs->rcvidx;`
180			`cs->rcvidx += count;`
181			`save_flags(flags);`
182			`cli();`
183			`cs->readisacfifo(cs, ptr, count);`
184			`cs->writeisac(cs, ISAC_CMDR, 0x80);`
185			`restore_flags(flags);`
186			`if (cs->debug & L1_DEB_ISAC_FIFO) {`
187			`char *t = cs->dlog;`
188
189			`t += sprintf(t, "isac_empty_fifo cnt %d", count);`
190			`QuickHex(t, ptr, count);`
191			`debugl1(cs, cs->dlog);`
192			`}`
193			`}`
194
195			`static void`
196			`isac_fill_fifo(struct IsdnCardState *cs)`
197			`{`
198			`int count, more;`
199			`u_char *ptr;`
200			`long flags;`
201
202			`if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))`
203			`debugl1(cs, "isac_fill_fifo");`
204
205			`if (!cs->tx_skb)`
206			`return;`
207
208			`count = cs->tx_skb->len;`
209			`if (count <= 0)`
210			`return;`
211
212			`more = 0;`
213			`if (count > 32) {`
214			`more = !0;`
215			`count = 32;`
216			`}`
217			`save_flags(flags);`
218			`cli();`
219			`ptr = cs->tx_skb->data;`
220			`skb_pull(cs->tx_skb, count);`
221			`cs->tx_cnt += count;`
222			`cs->writeisacfifo(cs, ptr, count);`
223			`cs->writeisac(cs, ISAC_CMDR, more ? 0x8 : 0xa);`
224			`restore_flags(flags);`
225			`if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {`
226			`debugl1(cs, "isac_fill_fifo dbusytimer running");`
227			`del_timer(&cs->dbusytimer);`
228			`}`
229			`init_timer(&cs->dbusytimer);`
230			`cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);`
231			`add_timer(&cs->dbusytimer);`
232			`if (cs->debug & L1_DEB_ISAC_FIFO) {`
233			`char *t = cs->dlog;`
234
235			`t += sprintf(t, "isac_fill_fifo cnt %d", count);`
236			`QuickHex(t, ptr, count);`
237			`debugl1(cs, cs->dlog);`
238			`}`
239			`}`
240
241			`void`
242			`isac_sched_event(struct IsdnCardState *cs, int event)`
243			`{`
244			`test_and_set_bit(event, &cs->event);`
245			`queue_task(&cs->tqueue, &tq_immediate);`
246			`mark_bh(IMMEDIATE_BH);`
247			`}`
248
249			`void`
250			`isac_interrupt(struct IsdnCardState *cs, u_char val)`
251			`{`
252			`u_char exval, v1;`
253			`struct sk_buff *skb;`
254			`unsigned int count;`
255			`long flags;`
256
257			`if (cs->debug & L1_DEB_ISAC)`
258			`debugl1(cs, "ISAC interrupt %x", val);`
259			`if (val & 0x80) { /* RME */`
260			`exval = cs->readisac(cs, ISAC_RSTA);`
261			`if ((exval & 0x70) != 0x20) {`
262			`if (exval & 0x40)`
263			`if (cs->debug & L1_DEB_WARN)`
264			`debugl1(cs, "ISAC RDO");`
265			`if (!(exval & 0x20))`
266			`if (cs->debug & L1_DEB_WARN)`
267			`debugl1(cs, "ISAC CRC error");`
268			`cs->writeisac(cs, ISAC_CMDR, 0x80);`
269			`} else {`
270			`count = cs->readisac(cs, ISAC_RBCL) & 0x1f;`
271			`if (count == 0)`
272			`count = 32;`
273			`isac_empty_fifo(cs, count);`
274			`save_flags(flags);`
275			`cli();`
276			`if ((count = cs->rcvidx) > 0) {`
277			`cs->rcvidx = 0;`
278			`if (!(skb = alloc_skb(count, GFP_ATOMIC)))`
279			`printk(KERN_WARNING "HiSax: D receive out of memory\n");`
280			`else {`
281			`SET_SKB_FREE(skb);`
282			`memcpy(skb_put(skb, count), cs->rcvbuf, count);`
283			`skb_queue_tail(&cs->rq, skb);`
284			`}`
285			`}`
286			`restore_flags(flags);`
287			`}`
288			`cs->rcvidx = 0;`
289			`isac_sched_event(cs, D_RCVBUFREADY);`
290			`}`
291			`if (val & 0x40) { /* RPF */`
292			`isac_empty_fifo(cs, 32);`
293			`}`
294			`if (val & 0x20) { /* RSC */`
295			`/* never */`
296			`if (cs->debug & L1_DEB_WARN)`
297			`debugl1(cs, "ISAC RSC interrupt");`
298			`}`
299			`if (val & 0x10) { /* XPR */`
300			`if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))`
301			`del_timer(&cs->dbusytimer);`
302			`if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))`
303			`isac_sched_event(cs, D_CLEARBUSY);`
304			`if (cs->tx_skb) {`
305			`if (cs->tx_skb->len) {`
306			`isac_fill_fifo(cs);`
307			`goto afterXPR;`
308			`} else {`
309			`dev_kfree_skb(cs->tx_skb, FREE_WRITE);`
310			`cs->tx_cnt = 0;`
311			`cs->tx_skb = NULL;`
312			`}`
313			`}`
314			`if ((cs->tx_skb = skb_dequeue(&cs->sq))) {`
315			`cs->tx_cnt = 0;`
316			`isac_fill_fifo(cs);`
317			`} else`
318			`isac_sched_event(cs, D_XMTBUFREADY);`
319			`}`
320			`afterXPR:`
321			`if (val & 0x04) { /* CISQ */`
322			`exval = cs->readisac(cs, ISAC_CIR0);`
323			`if (cs->debug & L1_DEB_ISAC)`
324			`debugl1(cs, "ISAC CIR0 %02X", exval );`
325			`if (exval & 2) {`
326			`cs->ph_state = (exval >> 2) & 0xf;`
327			`if (cs->debug & L1_DEB_ISAC)`
328			`debugl1(cs, "ph_state change %x", cs->ph_state);`
329			`isac_sched_event(cs, D_L1STATECHANGE);`
330			`}`
331			`if (exval & 1) {`
332			`exval = cs->readisac(cs, ISAC_CIR1);`
333			`if (cs->debug & L1_DEB_ISAC)`
334			`debugl1(cs, "ISAC CIR1 %02X", exval );`
335			`}`
336			`}`
337			`if (val & 0x02) { /* SIN */`
338			`/* never */`
339			`if (cs->debug & L1_DEB_WARN)`
340			`debugl1(cs, "ISAC SIN interrupt");`
341			`}`
342			`if (val & 0x01) { /* EXI */`
343			`exval = cs->readisac(cs, ISAC_EXIR);`
344			`if (cs->debug & L1_DEB_WARN)`
345			`debugl1(cs, "ISAC EXIR %02x", exval);`
346			`if (exval & 0x04) {`
347			`v1 = cs->readisac(cs, ISAC_MOSR);`
348			`if (cs->debug & L1_DEB_MONITOR)`
349			`debugl1(cs, "ISAC MOSR %02x", v1);`
350			`#if ARCOFI_USE`
351			`if (v1 & 0x08) {`
352			`if (!cs->mon_rx) {`
353			`if (!(cs->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {`
354			`if (cs->debug & L1_DEB_WARN)`
355			`debugl1(cs, "ISAC MON RX out of memory!");`
356			`cs->mocr &= 0xf0;`
357			`cs->mocr \|= 0x0a;`
358			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
359			`goto afterMONR0;`
360			`} else`
361			`cs->mon_rxp = 0;`
362			`}`
363			`if (cs->mon_rxp >= MAX_MON_FRAME) {`
364			`cs->mocr &= 0xf0;`
365			`cs->mocr \|= 0x0a;`
366			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
367			`cs->mon_rxp = 0;`
368			`if (cs->debug & L1_DEB_WARN)`
369			`debugl1(cs, "ISAC MON RX overflow!");`
370			`goto afterMONR0;`
371			`}`
372			`cs->mon_rx[cs->mon_rxp++] = cs->readisac(cs, ISAC_MOR0);`
373			`if (cs->debug & L1_DEB_MONITOR)`
374			`debugl1(cs, "ISAC MOR0 %02x", cs->mon_rx[cs->mon_rxp -1]);`
375			`if (cs->mon_rxp == 1) {`
376			`cs->mocr \|= 0x04;`
377			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
378			`}`
379			`}`
380			`afterMONR0:`
381			`if (v1 & 0x80) {`
382			`if (!cs->mon_rx) {`
383			`if (!(cs->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {`
384			`if (cs->debug & L1_DEB_WARN)`
385			`debugl1(cs, "ISAC MON RX out of memory!");`
386			`cs->mocr &= 0x0f;`
387			`cs->mocr \|= 0xa0;`
388			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
389			`goto afterMONR1;`
390			`} else`
391			`cs->mon_rxp = 0;`
392			`}`
393			`if (cs->mon_rxp >= MAX_MON_FRAME) {`
394			`cs->mocr &= 0x0f;`
395			`cs->mocr \|= 0xa0;`
396			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
397			`cs->mon_rxp = 0;`
398			`if (cs->debug & L1_DEB_WARN)`
399			`debugl1(cs, "ISAC MON RX overflow!");`
400			`goto afterMONR1;`
401			`}`
402			`cs->mon_rx[cs->mon_rxp++] = cs->readisac(cs, ISAC_MOR1);`
403			`if (cs->debug & L1_DEB_MONITOR)`
404			`debugl1(cs, "ISAC MOR1 %02x", cs->mon_rx[cs->mon_rxp -1]);`
405			`cs->mocr \|= 0x40;`
406			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
407			`}`
408			`afterMONR1:`
409			`if (v1 & 0x04) {`
410			`cs->mocr &= 0xf0;`
411			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
412			`cs->mocr \|= 0x0a;`
413			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
414			`test_and_set_bit(HW_MON0_RX_END, &cs->HW_Flags);`
415			`}`
416			`if (v1 & 0x40) {`
417			`cs->mocr &= 0x0f;`
418			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
419			`cs->mocr \|= 0xa0;`
420			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
421			`test_and_set_bit(HW_MON1_RX_END, &cs->HW_Flags);`
422			`}`
423			`if (v1 & 0x02) {`
424			`if ((!cs->mon_tx) \|\| (cs->mon_txc &&`
425			`(cs->mon_txp >= cs->mon_txc) &&`
426			`!(v1 & 0x08))) {`
427			`cs->mocr &= 0xf0;`
428			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
429			`cs->mocr \|= 0x0a;`
430			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
431			`if (cs->mon_txc &&`
432			`(cs->mon_txp >= cs->mon_txc))`
433			`test_and_set_bit(HW_MON0_TX_END, &cs->HW_Flags);`
434			`goto AfterMOX0;`
435			`}`
436			`if (cs->mon_txc && (cs->mon_txp >= cs->mon_txc)) {`
437			`test_and_set_bit(HW_MON0_TX_END, &cs->HW_Flags);`
438			`goto AfterMOX0;`
439			`}`
440			`cs->writeisac(cs, ISAC_MOX0,`
441			`cs->mon_tx[cs->mon_txp++]);`
442			`if (cs->debug & L1_DEB_MONITOR)`
443			`debugl1(cs, "ISAC %02x -> MOX0", cs->mon_tx[cs->mon_txp -1]);`
444			`}`
445			`AfterMOX0:`
446			`if (v1 & 0x20) {`
447			`if ((!cs->mon_tx) \|\| (cs->mon_txc &&`
448			`(cs->mon_txp >= cs->mon_txc) &&`
449			`!(v1 & 0x80))) {`
450			`cs->mocr &= 0x0f;`
451			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
452			`cs->mocr \|= 0xa0;`
453			`cs->writeisac(cs, ISAC_MOCR, cs->mocr);`
454			`if (cs->mon_txc &&`
455			`(cs->mon_txp >= cs->mon_txc))`
456			`test_and_set_bit(HW_MON1_TX_END, &cs->HW_Flags);`
457			`goto AfterMOX1;`
458			`}`
459			`if (cs->mon_txc && (cs->mon_txp >= cs->mon_txc)) {`
460			`test_and_set_bit(HW_MON1_TX_END, &cs->HW_Flags);`
461			`goto AfterMOX1;`
462			`}`
463			`cs->writeisac(cs, ISAC_MOX1,`
464			`cs->mon_tx[cs->mon_txp++]);`
465			`if (cs->debug & L1_DEB_MONITOR)`
466			`debugl1(cs, "ISAC %02x -> MOX1", cs->mon_tx[cs->mon_txp -1]);`
467			`}`
468			`AfterMOX1:`
469			`#endif`
470			`}`
471			`}`
472			`}`
473
474			`static void`
475			`ISAC_l1hw(struct PStack st, int pr, void arg)`
476			`{`
477			`struct IsdnCardState cs = (struct IsdnCardState ) st->l1.hardware;`
478			`struct sk_buff *skb = arg;`
479			`int val;`
480
481			`switch (pr) {`
482			`case (PH_DATA \|REQUEST):`
483			`if (cs->debug & DEB_DLOG_HEX)`
484			`LogFrame(cs, skb->data, skb->len);`
485			`if (cs->debug & DEB_DLOG_VERBOSE)`
486			`dlogframe(cs, skb, 0);`
487			`if (cs->tx_skb) {`
488			`skb_queue_tail(&cs->sq, skb);`
489			`#ifdef L2FRAME_DEBUG /* psa */`
490			`if (cs->debug & L1_DEB_LAPD)`
491			`Logl2Frame(cs, skb, "PH_DATA Queued", 0);`
492			`#endif`
493			`} else {`
494			`cs->tx_skb = skb;`
495			`cs->tx_cnt = 0;`
496			`#ifdef L2FRAME_DEBUG /* psa */`
497			`if (cs->debug & L1_DEB_LAPD)`
498			`Logl2Frame(cs, skb, "PH_DATA", 0);`
499			`#endif`
500			`isac_fill_fifo(cs);`
501			`}`
502			`break;`
503			`case (PH_PULL \|INDICATION):`
504			`if (cs->tx_skb) {`
505			`if (cs->debug & L1_DEB_WARN)`
506			`debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");`
507			`skb_queue_tail(&cs->sq, skb);`
508			`break;`
509			`}`
510			`if (cs->debug & DEB_DLOG_HEX)`
511			`LogFrame(cs, skb->data, skb->len);`
512			`if (cs->debug & DEB_DLOG_VERBOSE)`
513			`dlogframe(cs, skb, 0);`
514			`cs->tx_skb = skb;`
515			`cs->tx_cnt = 0;`
516			`#ifdef L2FRAME_DEBUG /* psa */`
517			`if (cs->debug & L1_DEB_LAPD)`
518			`Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);`
519			`#endif`
520			`isac_fill_fifo(cs);`
521			`break;`
522			`case (PH_PULL \| REQUEST):`
523			`#ifdef L2FRAME_DEBUG /* psa */`
524			`if (cs->debug & L1_DEB_LAPD)`
525			`debugl1(cs, "-> PH_REQUEST_PULL");`
526			`#endif`
527			`if (!cs->tx_skb) {`
528			`test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);`
529			`st->l1.l1l2(st, PH_PULL \| CONFIRM, NULL);`
530			`} else`
531			`test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);`
532			`break;`
533			`case (HW_RESET \| REQUEST):`
534			`if ((cs->ph_state == ISAC_IND_EI) \|\|`
535			`(cs->ph_state == ISAC_IND_DR) \|\|`
536			`(cs->ph_state == ISAC_IND_RS))`
537			`ph_command(cs, ISAC_CMD_TIM);`
538			`else`
539			`ph_command(cs, ISAC_CMD_RS);`
540			`break;`
541			`case (HW_ENABLE \| REQUEST):`
542			`ph_command(cs, ISAC_CMD_TIM);`
543			`break;`
544			`case (HW_INFO3 \| REQUEST):`
545			`ph_command(cs, ISAC_CMD_AR8);`
546			`break;`
547			`case (HW_TESTLOOP \| REQUEST):`
548			`val = 0;`
549			`if (1 & (long) arg)`
550			`val \|= 0x0c;`
551			`if (2 & (long) arg)`
552			`val \|= 0x3;`
553			`if (test_bit(HW_IOM1, &cs->HW_Flags)) {`
554			`/* IOM 1 Mode */`
555			`if (!val) {`
556			`cs->writeisac(cs, ISAC_SPCR, 0xa);`
557			`cs->writeisac(cs, ISAC_ADF1, 0x2);`
558			`} else {`
559			`cs->writeisac(cs, ISAC_SPCR, val);`
560			`cs->writeisac(cs, ISAC_ADF1, 0xa);`
561			`}`
562			`} else {`
563			`/* IOM 2 Mode */`
564			`cs->writeisac(cs, ISAC_SPCR, val);`
565			`if (val)`
566			`cs->writeisac(cs, ISAC_ADF1, 0x8);`
567			`else`
568			`cs->writeisac(cs, ISAC_ADF1, 0x0);`
569			`}`
570			`break;`
571			`case (HW_DEACTIVATE \| RESPONSE):`
572			`discard_queue(&cs->rq);`
573			`discard_queue(&cs->sq);`
574			`if (cs->tx_skb) {`
575			`dev_kfree_skb(cs->tx_skb, FREE_WRITE);`
576			`cs->tx_skb = NULL;`
577			`}`
578			`if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))`
579			`del_timer(&cs->dbusytimer);`
580			`if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))`
581			`isac_sched_event(cs, D_CLEARBUSY);`
582			`break;`
583			`default:`
584			`if (cs->debug & L1_DEB_WARN)`
585			`debugl1(cs, "isac_l1hw unknown %04x", pr);`
586			`break;`
587			`}`
588			`}`
589
590			`void`
591			`setstack_isac(struct PStack st, struct IsdnCardState cs)`
592			`{`
593			`st->l1.l1hw = ISAC_l1hw;`
594			`}`
595
596			`static void`
597			`dbusy_timer_handler(struct IsdnCardState *cs)`
598			`{`
599			`struct PStack *stptr;`
600			`int val;`
601
602			`if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {`
603			`if (cs->debug) {`
604			`debugl1(cs, "D-Channel Busy");`
605			`val = cs->readisac(cs, ISAC_RBCH);`
606			`if (val & ISAC_RBCH_XAC)`
607			`debugl1(cs, "ISAC XAC");`
608			`else`
609			`debugl1(cs, "ISAC No XAC");`
610			`}`
611			`test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags);`
612			`stptr = cs->stlist;`
613
614			`while (stptr != NULL) {`
615			`stptr->l1.l1l2(stptr, PH_PAUSE \| INDICATION, NULL);`
616			`stptr = stptr->next;`
617			`}`
618			`}`
619			`}`
620
621			`HISAX_INITFUNC(void`
622			`initisac(struct IsdnCardState *cs))`
623			`{`
624			`cs->tqueue.routine = (void ) (void ) isac_bh;`
625			`cs->setstack_d = setstack_isac;`
626			`cs->dbusytimer.function = (void *) dbusy_timer_handler;`
627			`cs->dbusytimer.data = (long) cs;`
628			`init_timer(&cs->dbusytimer);`
629			`cs->writeisac(cs, ISAC_MASK, 0xff);`
630			`cs->mocr = 0xaa;`
631			`if (test_bit(HW_IOM1, &cs->HW_Flags)) {`
632			`/* IOM 1 Mode */`
633			`cs->writeisac(cs, ISAC_ADF2, 0x0);`
634			`cs->writeisac(cs, ISAC_SPCR, 0xa);`
635			`cs->writeisac(cs, ISAC_ADF1, 0x2);`
636			`cs->writeisac(cs, ISAC_STCR, 0x70);`
637			`cs->writeisac(cs, ISAC_MODE, 0xc9);`
638			`} else {`
639			`/* IOM 2 Mode */`
640			`cs->writeisac(cs, ISAC_ADF2, 0x80);`
641			`cs->writeisac(cs, ISAC_SQXR, 0x2f);`
642			`cs->writeisac(cs, ISAC_SPCR, 0x00);`
643			`cs->writeisac(cs, ISAC_STCR, 0x70);`
644			`cs->writeisac(cs, ISAC_MODE, 0xc9);`
645			`cs->writeisac(cs, ISAC_TIMR, 0x00);`
646			`cs->writeisac(cs, ISAC_ADF1, 0x00);`
647			`}`
648			`ph_command(cs, ISAC_CMD_RS);`
649			`cs->writeisac(cs, ISAC_MASK, 0x0);`
650			`}`
651
652			`HISAX_INITFUNC(void`
653			`clear_pending_isac_ints(struct IsdnCardState *cs))`
654			`{`
655			`int val, eval;`
656
657			`val = cs->readisac(cs, ISAC_STAR);`
658			`debugl1(cs, "ISAC STAR %x", val);`
659			`val = cs->readisac(cs, ISAC_MODE);`
660			`debugl1(cs, "ISAC MODE %x", val);`
661			`val = cs->readisac(cs, ISAC_ADF2);`
662			`debugl1(cs, "ISAC ADF2 %x", val);`
663			`val = cs->readisac(cs, ISAC_ISTA);`
664			`debugl1(cs, "ISAC ISTA %x", val);`
665			`if (val & 0x01) {`
666			`eval = cs->readisac(cs, ISAC_EXIR);`
667			`debugl1(cs, "ISAC EXIR %x", eval);`
668			`}`
669			`val = cs->readisac(cs, ISAC_CIR0);`
670			`debugl1(cs, "ISAC CIR0 %x", val);`
671			`cs->ph_state = (val >> 2) & 0xf;`
672			`isac_sched_event(cs, D_L1STATECHANGE);`
673			`/* Disable all IRQ */`
674			`cs->writeisac(cs, ISAC_MASK, 0xFF);`
675			`}`