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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [drivers/] [net/] [3c503.h] - Blame information for rev 1765

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1 1626 jcastillo
/* Definitions for the 3Com 3c503 Etherlink 2. */
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/* This file is distributed under the GPL.
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   Many of these names and comments are directly from the Crynwr packet
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   drivers, which are released under the GPL. */
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#define EL2H (dev->base_addr + 0x400)
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#define EL2L (dev->base_addr)
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/* Vendor unique hardware addr. prefix. 3Com has 2 because they ran
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   out of available addresses on the first one... */
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#define OLD_3COM_ID     0x02608c
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#define NEW_3COM_ID     0x0020af
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/* Shared memory management parameters. NB: The 8 bit cards have only
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   one bank (MB1) which serves both Tx and Rx packet space. The 16bit
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   cards have 2 banks, MB0 for Tx packets, and MB1 for Rx packets.
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   You choose which bank appears in the sh. mem window with EGACFR_MBSn */
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#define EL2_MB0_START_PG        (0x00)  /* EL2/16 Tx packets go in bank 0 */
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#define EL2_MB1_START_PG        (0x20)  /* First page of bank 1 */
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#define EL2_MB1_STOP_PG         (0x40)  /* Last page +1 of bank 1 */
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/* 3Com 3c503 ASIC registers */
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#define E33G_STARTPG    (EL2H+0)        /* Start page, matching EN0_STARTPG */
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#define E33G_STOPPG     (EL2H+1)        /* Stop page, must match EN0_STOPPG */
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#define E33G_DRQCNT     (EL2H+2)        /* DMA burst count */
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#define E33G_IOBASE     (EL2H+3)        /* Read of I/O base jumpers. */
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        /* (non-useful, but it also appears at the end of EPROM space) */
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#define E33G_ROMBASE    (EL2H+4)        /* Read of memory base jumpers. */
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#define E33G_GACFR      (EL2H+5)        /* Config/setup bits for the ASIC GA */
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#define E33G_CNTRL      (EL2H+6)        /* Board's main control register */
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#define E33G_STATUS     (EL2H+7)        /* Status on completions. */
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#define E33G_IDCFR      (EL2H+8)        /* Interrupt/DMA config register */
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                                /* (Which IRQ to assert, DMA chan to use) */
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#define E33G_DMAAH      (EL2H+9)        /* High byte of DMA address reg */
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#define E33G_DMAAL      (EL2H+10)       /* Low byte of DMA address reg */
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/* "Vector pointer" - if this address matches a read, the EPROM (rather than
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   shared RAM) is mapped into memory space. */
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#define E33G_VP2        (EL2H+11)
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#define E33G_VP1        (EL2H+12)
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#define E33G_VP0        (EL2H+13)
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#define E33G_FIFOH      (EL2H+14)       /* FIFO for programmed I/O moves */
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#define E33G_FIFOL      (EL2H+15)       /* ... low byte of above. */
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/* Bits in E33G_CNTRL register: */
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#define ECNTRL_RESET    (0x01)  /* Software reset of the ASIC and 8390 */
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#define ECNTRL_THIN     (0x02)  /* Onboard xcvr enable, AUI disable */
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#define ECNTRL_AUI      (0x00)  /* Onboard xcvr disable, AUI enable */
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#define ECNTRL_SAPROM   (0x04)  /* Map the station address prom */
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#define ECNTRL_DBLBFR   (0x20)  /* FIFO configuration bit */
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#define ECNTRL_OUTPUT   (0x40)  /* PC-to-3C503 direction if 1 */
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#define ECNTRL_INPUT    (0x00)  /* 3C503-to-PC direction if 0 */
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#define ECNTRL_START    (0x80)  /* Start the DMA logic */
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/* Bits in E33G_STATUS register: */
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#define ESTAT_DPRDY     (0x80)  /* Data port (of FIFO) ready */
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#define ESTAT_UFLW      (0x40)  /* Tried to read FIFO when it was empty */
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#define ESTAT_OFLW      (0x20)  /* Tried to write FIFO when it was full */
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#define ESTAT_DTC       (0x10)  /* Terminal Count from PC bus DMA logic */
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#define ESTAT_DIP       (0x08)  /* DMA In Progress */
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/* Bits in E33G_GACFR register: */
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#define EGACFR_NIM      (0x80)  /* NIC interrupt mask */
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#define EGACFR_TCM      (0x40)  /* DMA term. count interrupt mask */
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#define EGACFR_RSEL     (0x08)  /* Map a bank of card mem into system mem */
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#define EGACFR_MBS2     (0x04)  /* Memory bank select, bit 2. */
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#define EGACFR_MBS1     (0x02)  /* Memory bank select, bit 1. */
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#define EGACFR_MBS0     (0x01)  /* Memory bank select, bit 0. */
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#define EGACFR_NORM     (0x49)  /* TCM | RSEL | MBS0 */
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#define EGACFR_IRQOFF   (0xc9)  /* TCM | RSEL | MBS0 | NIM */
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/*
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        MBS2    MBS1    MBS0    Sh. mem windows card mem at:
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        ----    ----    ----    -----------------------------
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There was going to be a 32k card that used bank 2 and 3, but it
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never got produced.
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*/
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/* End of 3C503 parameter definitions */

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