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1626 |
jcastillo |
/* Generic NS8390 register definitions. */
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/* This file is part of Donald Becker's 8390 drivers, and is distributed
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under the same license.
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Some of these names and comments originated from the Crynwr
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packet drivers, which are distributed under the GPL. */
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#ifndef _8390_h
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#define _8390_h
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#include <linux/if_ether.h>
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#include <linux/ioport.h>
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#include <linux/skbuff.h>
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#define TX_2X_PAGES 12
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#define TX_1X_PAGES 6
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/* Should always use two Tx slots to get back-to-back transmits. */
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#define EI_PINGPONG
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#ifdef EI_PINGPONG
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#define TX_PAGES TX_2X_PAGES
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#else
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#define TX_PAGES TX_1X_PAGES
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#endif
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#define ETHER_ADDR_LEN 6
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/* The 8390 specific per-packet-header format. */
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struct e8390_pkt_hdr {
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unsigned char status; /* status */
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unsigned char next; /* pointer to next packet. */
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unsigned short count; /* header + packet length in bytes */
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};
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/* From 8390.c */
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extern int ei_debug;
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extern struct sigaction ei_sigaction;
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extern int ethif_init(struct device *dev);
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extern int ethdev_init(struct device *dev);
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extern void NS8390_init(struct device *dev, int startp);
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extern int ei_open(struct device *dev);
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extern int ei_close(struct device *dev);
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extern void ei_interrupt(int irq, void *dev_id, struct pt_regs *regs);
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#ifndef HAVE_AUTOIRQ
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/* From auto_irq.c */
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extern struct device *irq2dev_map[16];
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extern int autoirq_setup(int waittime);
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extern int autoirq_report(int waittime);
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#endif
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/* Most of these entries should be in 'struct device' (or most of the
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things in there should be here!) */
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/* You have one of these per-board */
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struct ei_device {
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const char *name;
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void (*reset_8390)(struct device *);
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void (*get_8390_hdr)(struct device *, struct e8390_pkt_hdr *, int);
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void (*block_output)(struct device *, int, const unsigned char *, int);
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void (*block_input)(struct device *, int, struct sk_buff *, int);
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unsigned open:1;
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unsigned word16:1; /* We have the 16-bit (vs 8-bit) version of the card. */
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unsigned txing:1; /* Transmit Active */
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unsigned irqlock:1; /* 8390's intrs disabled when '1'. */
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unsigned dmaing:1; /* Remote DMA Active */
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unsigned char tx_start_page, rx_start_page, stop_page;
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unsigned char current_page; /* Read pointer in buffer */
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unsigned char interface_num; /* Net port (AUI, 10bT.) to use. */
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unsigned char txqueue; /* Tx Packet buffer queue length. */
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short tx1, tx2; /* Packet lengths for ping-pong tx. */
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short lasttx; /* Alpha version consistency check. */
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unsigned char reg0; /* Register '0' in a WD8013 */
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unsigned char reg5; /* Register '5' in a WD8013 */
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unsigned char saved_irq; /* Original dev->irq value. */
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/* The new statistics table. */
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struct enet_statistics stat;
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};
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/* The maximum number of 8390 interrupt service routines called per IRQ. */
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#define MAX_SERVICE 12
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/* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */
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#define TX_TIMEOUT (20*HZ/100)
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#define ei_status (*(struct ei_device *)(dev->priv))
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/* Some generic ethernet register configurations. */
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#define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */
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#define E8390_RX_IRQ_MASK 0x5
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#define E8390_RXCONFIG 0x4 /* EN0_RXCR: broadcasts, no multicast,errors */
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#define E8390_RXOFF 0x20 /* EN0_RXCR: Accept no packets */
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#define E8390_TXCONFIG 0x00 /* EN0_TXCR: Normal transmit mode */
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#define E8390_TXOFF 0x02 /* EN0_TXCR: Transmitter off */
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/* Register accessed at EN_CMD, the 8390 base addr. */
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#define E8390_STOP 0x01 /* Stop and reset the chip */
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#define E8390_START 0x02 /* Start the chip, clear reset */
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#define E8390_TRANS 0x04 /* Transmit a frame */
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#define E8390_RREAD 0x08 /* Remote read */
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#define E8390_RWRITE 0x10 /* Remote write */
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#define E8390_NODMA 0x20 /* Remote DMA */
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#define E8390_PAGE0 0x00 /* Select page chip registers */
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#define E8390_PAGE1 0x40 /* using the two high-order bits */
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#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
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#define E8390_CMD 0x00 /* The command register (for all pages) */
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/* Page 0 register offsets. */
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#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
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#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
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#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
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#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
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#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
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#define EN0_TSR 0x04 /* Transmit status reg RD */
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#define EN0_TPSR 0x04 /* Transmit starting page WR */
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#define EN0_NCR 0x05 /* Number of collision reg RD */
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#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
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#define EN0_FIFO 0x06 /* FIFO RD */
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#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
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#define EN0_ISR 0x07 /* Interrupt status reg RD WR */
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#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
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#define EN0_RSARLO 0x08 /* Remote start address reg 0 */
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#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
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#define EN0_RSARHI 0x09 /* Remote start address reg 1 */
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#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
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#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
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#define EN0_RSR 0x0c /* rx status reg RD */
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#define EN0_RXCR 0x0c /* RX configuration reg WR */
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#define EN0_TXCR 0x0d /* TX configuration reg WR */
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#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
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#define EN0_DCFG 0x0e /* Data configuration reg WR */
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#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
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#define EN0_IMR 0x0f /* Interrupt mask reg WR */
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#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
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/* Bits in EN0_ISR - Interrupt status register */
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#define ENISR_RX 0x01 /* Receiver, no error */
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#define ENISR_TX 0x02 /* Transmitter, no error */
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#define ENISR_RX_ERR 0x04 /* Receiver, with error */
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#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
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#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
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#define ENISR_COUNTERS 0x20 /* Counters need emptying */
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#define ENISR_RDC 0x40 /* remote dma complete */
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#define ENISR_RESET 0x80 /* Reset completed */
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#define ENISR_ALL 0x3f /* Interrupts we will enable */
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/* Bits in EN0_DCFG - Data config register */
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#define ENDCFG_WTS 0x01 /* word transfer mode selection */
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/* Page 1 register offsets. */
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#define EN1_PHYS 0x01 /* This board's physical enet addr RD WR */
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#define EN1_CURPAG 0x07 /* Current memory page RD WR */
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#define EN1_MULT 0x08 /* Multicast filter mask array (8 bytes) RD WR */
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/* Bits in received packet status byte and EN0_RSR*/
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#define ENRSR_RXOK 0x01 /* Received a good packet */
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#define ENRSR_CRC 0x02 /* CRC error */
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#define ENRSR_FAE 0x04 /* frame alignment error */
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#define ENRSR_FO 0x08 /* FIFO overrun */
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#define ENRSR_MPA 0x10 /* missed pkt */
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#define ENRSR_PHY 0x20 /* physical/multicase address */
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#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
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#define ENRSR_DEF 0x80 /* deferring */
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/* Transmitted packet status, EN0_TSR. */
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#define ENTSR_PTX 0x01 /* Packet transmitted without error */
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#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
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#define ENTSR_COL 0x04 /* The transmit collided at least once. */
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#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
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#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
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#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
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#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
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#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
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#endif /* _8390_h */
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