OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [drivers/] [net/] [de4x5.c] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1626 jcastillo
/*  de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2
             ethernet driver for Linux.
3
 
4
    Copyright 1994, 1995 Digital Equipment Corporation.
5
 
6
    Testing resources for this driver have been made available
7
    in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
 
9
    The author may be reached at davies@maniac.ultranet.com.
10
 
11
    This program is free software; you can redistribute  it and/or modify it
12
    under  the terms of  the GNU General  Public License as published by the
13
    Free Software Foundation;  either version 2 of the  License, or (at your
14
    option) any later version.
15
 
16
    THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR   IMPLIED
17
    WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
18
    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
19
    NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
20
    INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21
    NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
22
    USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23
    ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
24
    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25
    THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
 
27
    You should have received a copy of the  GNU General Public License along
28
    with this program; if not, write  to the Free Software Foundation, Inc.,
29
    675 Mass Ave, Cambridge, MA 02139, USA.
30
 
31
    Originally,   this  driver  was    written  for the  Digital   Equipment
32
    Corporation series of EtherWORKS ethernet cards:
33
 
34
        DE425 TP/COAX EISA
35
        DE434 TP PCI
36
        DE435 TP/COAX/AUI PCI
37
        DE450 TP/COAX/AUI PCI
38
        DE500 10/100 PCI Fasternet
39
 
40
    but it  will  now attempt  to  support all  cards which   conform to the
41
    Digital Semiconductor   SROM   Specification.    The  driver   currently
42
    recognises the following chips:
43
 
44
        DC21040  (no SROM)
45
        DC21041[A]
46
        DC21140[A]
47
        DC21142
48
        DC21143
49
 
50
    So far the driver is known to work with the following cards:
51
 
52
        KINGSTON
53
        Linksys
54
        ZNYX342
55
        SMC8432
56
        SMC9332 (w/new SROM)
57
        ZNYX31[45]
58
        ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
59
 
60
    The driver has been tested on a relatively busy network using the DE425,
61
    DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62
    16M of data to a DECstation 5000/200 as follows:
63
 
64
                TCP           UDP
65
             TX     RX     TX     RX
66
    DE425   1030k  997k   1170k  1128k
67
    DE434   1063k  995k   1170k  1125k
68
    DE435   1063k  995k   1170k  1125k
69
    DE500   1063k  998k   1170k  1125k  in 10Mb/s mode
70
 
71
    All  values are typical (in   kBytes/sec) from a  sample  of 4 for  each
72
    measurement. Their error is +/-20k on a quiet (private) network and also
73
    depend on what load the CPU has.
74
 
75
    =========================================================================
76
    This driver  has been written substantially  from  scratch, although its
77
    inheritance of style and stack interface from 'ewrk3.c' and in turn from
78
    Donald Becker's 'lance.c' should be obvious. With the module autoload of
79
    every  usable DECchip board,  I  pinched Donald's 'next_module' field to
80
    link my modules together.
81
 
82
    Upto 15 EISA cards can be supported under this driver, limited primarily
83
    by the available IRQ lines.  I have  checked different configurations of
84
    multiple depca, EtherWORKS 3 cards and de4x5 cards and  have not found a
85
    problem yet (provided you have at least depca.c v0.38) ...
86
 
87
    PCI support has been added  to allow the driver  to work with the DE434,
88
    DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89
    to the differences in the EISA and PCI CSR address offsets from the base
90
    address.
91
 
92
    The ability to load this  driver as a loadable  module has been included
93
    and used extensively  during the driver development  (to save those long
94
    reboot sequences).  Loadable module support  under PCI and EISA has been
95
    achieved by letting the driver autoprobe as if it were compiled into the
96
    kernel. Do make sure  you're not sharing  interrupts with anything  that
97
    cannot accommodate  interrupt  sharing!
98
 
99
    To utilise this ability, you have to do 8 things:
100
 
101
    0) have a copy of the loadable modules code installed on your system.
102
    1) copy de4x5.c from the  /linux/drivers/net directory to your favourite
103
    temporary directory.
104
    2) for fixed  autoprobes (not  recommended),  edit the source code  near
105
    line 5594 to reflect the I/O address  you're using, or assign these when
106
    loading by:
107
 
108
                   insmod de4x5 io=0xghh           where g = bus number
109
                                                        hh = device number
110
 
111
       NB: autoprobing for modules is now supported by default. You may just
112
           use:
113
 
114
                   insmod de4x5
115
 
116
           to load all available boards. For a specific board, still use
117
           the 'io=?' above.
118
    3) compile  de4x5.c, but include -DMODULE in  the command line to ensure
119
    that the correct bits are compiled (see end of source code).
120
    4) if you are wanting to add a new  card, goto 5. Otherwise, recompile a
121
    kernel with the de4x5 configuration turned off and reboot.
122
    5) insmod de4x5 [io=0xghh]
123
    6) run the net startup bits for your new eth?? interface(s) manually
124
    (usually /etc/rc.inet[12] at boot time).
125
    7) enjoy!
126
 
127
    To unload a module, turn off the associated interface(s)
128
    'ifconfig eth?? down' then 'rmmod de4x5'.
129
 
130
    Automedia detection is included so that in  principal you can disconnect
131
    from, e.g.  TP, reconnect  to BNC  and  things will still work  (after a
132
    pause whilst the   driver figures out   where its media went).  My tests
133
    using ping showed that it appears to work....
134
 
135
    By  default,  the driver will  now   autodetect any  DECchip based card.
136
    Should you have a need to restrict the driver to DIGITAL only cards, you
137
    can compile with a  DEC_ONLY define, or if  loading as a module, use the
138
    'dec_only=1'  parameter.
139
 
140
    I've changed the timing routines to  use the kernel timer and scheduling
141
    functions  so that the  hangs  and other assorted problems that occurred
142
    while autosensing the  media  should be gone.  A  bonus  for the DC21040
143
    auto  media sense algorithm is  that it can now  use one that is more in
144
    line with the  rest (the DC21040  chip doesn't  have a hardware  timer).
145
    The downside is the 1 'jiffies' (10ms) resolution.
146
 
147
    IEEE 802.3u MII interface code has  been added in anticipation that some
148
    products may use it in the future.
149
 
150
    The SMC9332 card  has a non-compliant SROM  which needs fixing -  I have
151
    patched this  driver to detect it  because the SROM format used complies
152
    to a previous DEC-STD format.
153
 
154
    I have removed the buffer copies needed for receive on Intels.  I cannot
155
    remove them for   Alphas since  the  Tulip hardware   only does longword
156
    aligned  DMA transfers  and  the  Alphas get   alignment traps with  non
157
    longword aligned data copies (which makes them really slow). No comment.
158
 
159
    I  have added SROM decoding  routines to make this  driver work with any
160
    card that  supports the Digital  Semiconductor SROM spec. This will help
161
    all  cards running the dc2114x  series chips in particular.  Cards using
162
    the dc2104x  chips should run correctly with  the basic  driver.  I'm in
163
    debt to <mjacob@feral.com> for the  testing and feedback that helped get
164
    this feature working.  So far we have  tested KINGSTON, SMC8432, SMC9332
165
    (with the latest SROM complying  with the SROM spec  V3: their first was
166
    broken), ZNYX342  and  LinkSys. ZYNX314 (dual  21041  MAC) and  ZNYX 315
167
    (quad 21041 MAC)  cards also  appear  to work despite their  incorrectly
168
    wired IRQs.
169
 
170
    I have added a temporary fix for interrupt problems when some SCSI cards
171
    share the same interrupt as the DECchip based  cards. The problem occurs
172
    because  the SCSI card wants to  grab the interrupt  as a fast interrupt
173
    (runs the   service routine with interrupts turned   off) vs.  this card
174
    which really needs to run the service routine with interrupts turned on.
175
    This driver will  now   add the interrupt service   routine  as  a  fast
176
    interrupt if it   is bounced from the   slow interrupt.  THIS IS NOT   A
177
    RECOMMENDED WAY TO RUN THE DRIVER  and has been done  for a limited time
178
    until  people   sort  out their  compatibility    issues and the  kernel
179
    interrupt  service code  is  fixed.   YOU  SHOULD SEPARATE OUT  THE FAST
180
    INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181
    run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
 
183
    Finally, I think  I have really  fixed  the module  loading problem with
184
    more than one DECchip based  card.  As a  side effect, I don't mess with
185
    the  device structure any  more which means that  if more than 1 card in
186
    2.0.x is    installed (4  in   2.1.x),  the  user   will have   to  edit
187
    linux/drivers/net/Space.c  to make room for  them. Hence, module loading
188
    is  the preferred way to use   this driver, since  it  doesn't have this
189
    limitation.
190
 
191
    Where SROM media  detection is used and  full duplex is specified in the
192
    SROM,  the feature is  ignored unless  lp->params.fdx  is set at compile
193
    time  OR during  a   module load  (insmod  de4x5   args='eth??:fdx' [see
194
    below]).  This is because there  is no way  to automatically detect full
195
    duplex   links  except through   autonegotiation.    When I  include the
196
    autonegotiation feature in  the SROM autoconf  code, this detection will
197
    occur automatically for that case.
198
 
199
    Command  line arguments are  now  allowed, similar  to passing arguments
200
    through LILO. This will allow a per adapter board  set up of full duplex
201
    and media. The only lexical constraints  are: the board name (dev->name)
202
    appears in the list before its  parameters.  The list of parameters ends
203
    either at the end of the parameter list or with another board name.  The
204
    following parameters are allowed:
205
 
206
            fdx        for full duplex
207
            autosense  to set the media/speed; with the following
208
                       sub-parameters:
209
                       TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
 
211
    Case sensitivity is important  for  the sub-parameters. They *must*   be
212
    upper case. Examples:
213
 
214
        insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
 
216
    For a compiled in driver, in linux/drivers/net/CONFIG, place e.g.
217
        DE4X5_OPTS = -DDE4X5_PARM='"eth0:fdx autosense=AUI eth2:autosense=TP"'
218
 
219
    Yes,  I know full duplex  isn't permissible on BNC  or AUI; they're just
220
    examples. By default, full duplex is turned  off and AUTO is the default
221
    autosense setting. In  reality, I expect only the  full duplex option to
222
    be used. Note the use of single quotes in the two examples above and the
223
    lack of commas to separate items.
224
 
225
    TO DO:
226
    ------
227
 
228
    o check what revision numbers the 21142 and 21143 have
229
    o
230
 
231
    Revision History
232
    ----------------
233
 
234
    Version   Date        Description
235
 
236
      0.1     17-Nov-94   Initial writing. ALPHA code release.
237
      0.2     13-Jan-95   Added PCI support for DE435's.
238
      0.21    19-Jan-95   Added auto media detection.
239
      0.22    10-Feb-95   Fix interrupt handler call <chris@cosy.sbg.ac.at>.
240
                          Fix recognition bug reported by <bkm@star.rl.ac.uk>.
241
                          Add request/release_region code.
242
                          Add loadable modules support for PCI.
243
                          Clean up loadable modules support.
244
      0.23    28-Feb-95   Added DC21041 and DC21140 support.
245
                          Fix missed frame counter value and initialisation.
246
                          Fixed EISA probe.
247
      0.24    11-Apr-95   Change delay routine to use <linux/udelay>.
248
                          Change TX_BUFFS_AVAIL macro.
249
                          Change media autodetection to allow manual setting.
250
                          Completed DE500 (DC21140) support.
251
      0.241   18-Apr-95   Interim release without DE500 Autosense Algorithm.
252
      0.242   10-May-95   Minor changes.
253
      0.30    12-Jun-95   Timer fix for DC21140.
254
                          Portability changes.
255
                          Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
256
                          Add DE500 semi automatic autosense.
257
                          Add Link Fail interrupt TP failure detection.
258
                          Add timer based link change detection.
259
                          Plugged a memory leak in de4x5_queue_pkt().
260
      0.31    13-Jun-95   Fixed PCI stuff for 1.3.1.
261
      0.32    26-Jun-95   Added verify_area() calls in de4x5_ioctl() from a
262
                          suggestion by <heiko@colossus.escape.de>.
263
      0.33     8-Aug-95   Add shared interrupt support (not released yet).
264
      0.331   21-Aug-95   Fix de4x5_open() with fast CPUs.
265
                          Fix de4x5_interrupt().
266
                          Fix dc21140_autoconf() mess.
267
                          No shared interrupt support.
268
      0.332   11-Sep-95   Added MII management interface routines.
269
      0.40     5-Mar-96   Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
270
                          Add kernel timer code (h/w is too flaky).
271
                          Add MII based PHY autosense.
272
                          Add new multicasting code.
273
                          Add new autosense algorithms for media/mode
274
                          selection using kernel scheduling/timing.
275
                          Re-formatted.
276
                          Made changes suggested by <jeff@router.patch.net>:
277
                            Change driver to detect all DECchip based cards
278
                            with DEC_ONLY restriction a special case.
279
                            Changed driver to autoprobe as a module. No irq
280
                            checking is done now - assume BIOS is good!
281
                          Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
282
      0.41    21-Mar-96   Don't check for get_hw_addr checksum unless DEC card
283
                          only <niles@axp745gsfc.nasa.gov>
284
                          Fix for multiple PCI cards reported by <jos@xos.nl>
285
                          Duh, put the SA_SHIRQ flag into request_interrupt().
286
                          Fix SMC ethernet address in enet_det[].
287
                          Print chip name instead of "UNKNOWN" during boot.
288
      0.42    26-Apr-96   Fix MII write TA bit error.
289
                          Fix bug in dc21040 and dc21041 autosense code.
290
                          Remove buffer copies on receive for Intels.
291
                          Change sk_buff handling during media disconnects to
292
                           eliminate DUP packets.
293
                          Add dynamic TX thresholding.
294
                          Change all chips to use perfect multicast filtering.
295
                          Fix alloc_device() bug <jari@markkus2.fimr.fi>
296
      0.43   21-Jun-96    Fix unconnected media TX retry bug.
297
                          Add Accton to the list of broken cards.
298
                          Fix TX under-run bug for non DC21140 chips.
299
                          Fix boot command probe bug in alloc_device() as
300
                           reported by <koen.gadeyne@barco.com> and
301
                           <orava@nether.tky.hut.fi>.
302
                          Add cache locks to prevent a race condition as
303
                           reported by <csd@microplex.com> and
304
                           <baba@beckman.uiuc.edu>.
305
                          Upgraded alloc_device() code.
306
      0.431  28-Jun-96    Fix potential bug in queue_pkt() from discussion
307
                          with <csd@microplex.com>
308
      0.44   13-Aug-96    Fix RX overflow bug in 2114[023] chips.
309
                          Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
310
                          and <michael@compurex.com>.
311
      0.441   9-Sep-96    Change dc21041_autoconf() to probe quiet BNC media
312
                           with a loopback packet.
313
      0.442   9-Sep-96    Include AUI in dc21041 media printout. Bug reported
314
                           by <bhat@mundook.cs.mu.OZ.AU>
315
      0.45    8-Dec-96    Include endian functions for PPC use, from work
316
                           by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
317
      0.451  28-Dec-96    Added fix to allow autoprobe for modules after
318
                           suggestion from <mjacob@feral.com>.
319
      0.5    30-Jan-97    Added SROM decoding functions.
320
                          Updated debug flags.
321
                          Fix sleep/wakeup calls for PCI cards, bug reported
322
                           by <cross@gweep.lkg.dec.com>.
323
                          Added multi-MAC, one SROM feature from discussion
324
                           with <mjacob@feral.com>.
325
                          Added full module autoprobe capability.
326
                          Added attempt to use an SMC9332 with broken SROM.
327
                          Added fix for ZYNX multi-mac cards that didn't
328
                           get their IRQs wired correctly.
329
      0.51   13-Feb-97    Added endian fixes for the SROM accesses from
330
                           <paubert@iram.es>
331
                          Fix init_connection() to remove extra device reset.
332
                          Fix MAC/PHY reset ordering in dc21140m_autoconf().
333
                          Fix initialisation problem with lp->timeout in
334
                           typeX_infoblock() from <paubert@iram.es>.
335
                          Fix MII PHY reset problem from work done by
336
                           <paubert@iram.es>.
337
      0.52   26-Apr-97    Some changes may not credit the right people -
338
                           a disk crash meant I lost some mail.
339
                          Change RX interrupt routine to drop rather than
340
                           defer packets to avoid hang reported by
341
                           <g.thomas@opengroup.org>.
342
                          Fix srom_exec() to return for COMPACT and type 1
343
                           infoblocks.
344
                          Added DC21142 and DC21143 functions.
345
                          Added byte counters from <phil@tazenda.demon.co.uk>
346
                          Added SA_INTERRUPT temporary fix from
347
                           <mjacob@feral.com>.
348
      0.53   12-Nov-97    Fix the *_probe() to include 'eth??' name during
349
                           module load: bug reported by
350
                           <Piete.Brooks@cl.cam.ac.uk>
351
                          Fix multi-MAC, one SROM, to work with 2114x chips:
352
                           bug reported by <cmetz@inner.net>.
353
                          Make above search independent of BIOS device scan
354
                           direction.
355
                          Completed DC2114[23] autosense functions.
356
      0.531  21-Dec-97    Fix DE500-XA 100Mb/s bug reported by
357
                           <robin@intercore.com
358
                          Fix type1_infoblock() bug introduced in 0.53, from
359
                           problem reports by
360
                           <parmee@postecss.ncrfran.france.ncr.com> and
361
                           <jo@ice.dillingen.baynet.de>.
362
                          Added argument list to set up each board from either
363
                           a module's command line or a compiled in #define.
364
                          Added generic MII PHY functionality to deal with
365
                           newer PHY chips.
366
                          Fix the mess in 2.1.67.
367
      0.532   5-Jan-98    Fix bug in mii_get_phy() reported by
368
                           <redhat@cococo.net>.
369
                          Fix bug in pci_probe() for 64 bit systems reported
370
                           by <belliott@accessone.com>.
371
      0.533   9-Jan-98    Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
372
      0.534  24-Jan-98    Fix last (?) endian bug from
373
                           <Geert.Uytterhoeven@cs.kuleuven.ac.be>
374
      0.535  21-Feb-98    Fix Ethernet Address PROM reset bug for DC21040.
375
      0.5351  4-Oct-98    Atomicize assertion of dev->interrupt for SMP (not
376
                           for Alpha arch.) from <lma@varesearch.com>
377
                          Add TP, AUI and BNC cases to 21140m_autoconf() for
378
                           case where a 21140 under SROM control uses, e.g. AUI
379
                           from problem report by <delchini@lpnp09.in2p3.fr>
380
                          Add MII parallel detection to 2114x_autoconf() for
381
                           case where no autonegotiation partner exists from
382
                           problem report by <mlapsley@ndirect.co.uk>.
383
                          Add ability to force connection type directly even
384
                           when using SROM control from problem report by
385
                           <earl@exis.net>.
386
                          Fix is_anc_capable() bug reported by
387
                           <Austin.Donnelly@cl.cam.ac.uk>.
388
                          Fix type[13]_infoblock() bug: during MII search, PHY
389
                           lp->rst not run because lp->ibn not initialised -
390
                           from report & fix by <paubert@iram.es>.
391
                          Fix probe bug with EISA & PCI cards present from
392
                           report by <eirik@netcom.com>.
393
                          Fix compiler problems associated with i386-string
394
                           ops from multiple bug reports and temporary fix
395
                           from <paubert@iram.es>.
396
                          Add an_exception() for old ZYNX346 and fix compile
397
                           warning on PPC & SPARC, from <ecd@skynet.be>.
398
                          Fix lastPCI to correctly work with compiled in
399
                           kernels and modules from bug report by
400
                           <Zlatko.Calusic@CARNet.hr> et al.
401
                          Fix dc2114x_autoconf() to stop multiple messages
402
                           when media is unconnected.
403
                          Change dev->interrupt to lp->interrupt to ensure
404
                           alignment for Alpha's and avoid their unaligned
405
                           access traps. This flag is merely for log messages:
406
                           should do something more definitive though...
407
      0.5352 30-Dec-98    Fix driver recognition of the newer DECchips.
408
 
409
    =========================================================================
410
*/
411
 
412
static const char *version = "de4x5.c:V0.5352 1998/12/30 davies@maniac.ultranet.com\n";
413
 
414
#include <linux/module.h>
415
 
416
#include <linux/kernel.h>
417
#include <linux/sched.h>
418
#include <linux/string.h>
419
#include <linux/interrupt.h>
420
#include <linux/ptrace.h>
421
#include <linux/errno.h>
422
#include <linux/ioport.h>
423
#include <linux/malloc.h>
424
#include <linux/bios32.h>
425
#include <linux/pci.h>
426
#include <linux/delay.h>
427
#include <asm/bitops.h>
428
#include <asm/io.h>
429
#include <asm/dma.h>
430
#include <asm/byteorder.h>
431
#include <asm/unaligned.h>
432
 
433
#include <linux/netdevice.h>
434
#include <linux/etherdevice.h>
435
#include <linux/skbuff.h>
436
 
437
#include <linux/time.h>
438
#include <linux/types.h>
439
#include <linux/unistd.h>
440
#include <linux/ctype.h>
441
 
442
#include "de4x5.h"
443
 
444
#define c_char const char
445
 
446
#include <linux/version.h>
447
#if     LINUX_VERSION_CODE < LinuxVersionCode(2,1,0)
448
#  define __initfunc(__arginit) __arginit
449
#  define test_and_set_bit      set_bit
450
#  define net_device_stats      enet_statistics
451
#  define copy_to_user(a,b,c)   memcpy_tofs(a,b,c)
452
#  define copy_from_user(a,b,c) memcpy_fromfs(a,b,c)
453
#  define le16_to_cpu(a)        cpu_to_le16(a) 
454
#  define le32_to_cpu(a)        cpu_to_le32(a) 
455
#  ifdef __powerpc__
456
#    define cpu_to_le16(a) ((((a) & 0x00ffU) << 8) | (((a) & 0xff00U) >> 8))
457
#    define cpu_to_le32(a) ((((a) & 0x000000ffU) << 24) |\
458
                            (((a) & 0x0000ff00U) <<  8) |\
459
                            (((a) & 0x00ff0000U) >>  8) |\
460
                            (((a) & 0xff000000U) >> 24))
461
#  else
462
#    define cpu_to_le16(a)      (a)
463
#    define cpu_to_le32(a)      (a)
464
#  endif  /* __powerpc__ */
465
#  include <asm/segment.h>
466
#else
467
#  include <asm/uaccess.h>
468
#  include <linux/init.h>
469
#endif  /* LINUX_VERSION_CODE */
470
#define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a)))
471
 
472
/*
473
** MII Information
474
*/
475
struct phy_table {
476
    int reset;              /* Hard reset required?                         */
477
    int id;                 /* IEEE OUI                                     */
478
    int ta;                 /* One cycle TA time - 802.3u is confusing here */
479
    struct {                /* Non autonegotiation (parallel) speed det.    */
480
        int reg;
481
        int mask;
482
        int value;
483
    } spd;
484
};
485
 
486
struct mii_phy {
487
    int reset;              /* Hard reset required?                      */
488
    int id;                 /* IEEE OUI                                  */
489
    int ta;                 /* One cycle TA time                         */
490
    struct {                /* Non autonegotiation (parallel) speed det. */
491
        int reg;
492
        int mask;
493
        int value;
494
    } spd;
495
    int addr;               /* MII address for the PHY                   */
496
    u_char  *gep;           /* Start of GEP sequence block in SROM       */
497
    u_char  *rst;           /* Start of reset sequence in SROM           */
498
    u_int mc;               /* Media Capabilities                        */
499
    u_int ana;              /* NWay Advertisement                        */
500
    u_int fdx;              /* Full DupleX capabilites for each media    */
501
    u_int ttm;              /* Transmit Threshold Mode for each media    */
502
    u_int mci;              /* 21142 MII Connector Interrupt info        */
503
};
504
 
505
#define DE4X5_MAX_PHY 8     /* Allow upto 8 attached PHY devices per board */
506
 
507
struct sia_phy {
508
    u_char mc;              /* Media Code                                */
509
    u_char ext;             /* csr13-15 valid when set                   */
510
    int csr13;              /* SIA Connectivity Register                 */
511
    int csr14;              /* SIA TX/RX Register                        */
512
    int csr15;              /* SIA General Register                      */
513
    int gepc;               /* SIA GEP Control Information               */
514
    int gep;                /* SIA GEP Data                              */
515
};
516
 
517
/*
518
** Define the know universe of PHY devices that can be
519
** recognised by this driver.
520
*/
521
static struct phy_table phy_info[] = {
522
    {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}},       /* National TX */
523
    {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}},       /* Broadcom T4 */
524
    {0, SEEQ_T4    , 1, {0x12, 0x10, 0x10}},       /* SEEQ T4     */
525
    {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}},       /* Cypress T4  */
526
    {0, 0x7810     , 1, {0x05, 0x0380, 0x0380}}    /* Level One?  */
527
};
528
 
529
/*
530
** These GENERIC values assumes that the PHY devices follow 802.3u and
531
** allow parallel detection to set the link partner ability register.
532
** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
533
*/
534
#define GENERIC_REG   0x05      /* Autoneg. Link Partner Advertisement Reg. */
535
#define GENERIC_MASK  MII_ANLPA_100M /* All 100Mb/s Technologies            */
536
#define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4       */
537
 
538
/*
539
** Define special SROM detection cases
540
*/
541
static c_char enet_det[][ETH_ALEN] = {
542
    {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
543
    {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
544
};
545
 
546
#define SMC    1
547
#define ACCTON 2
548
 
549
/*
550
** SROM Repair definitions. If a broken SROM is detected a card may
551
** use this information to help figure out what to do. This is a
552
** "stab in the dark" and so far for SMC9332's only.
553
*/
554
static c_char srom_repair_info[][100] = {
555
    {0x00,0x1e,0x00,0x00,0x00,0x08,             /* SMC9332 */
556
     0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
557
     0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
558
     0x00,0x18,}
559
};
560
 
561
 
562
#ifdef DE4X5_DEBUG
563
static int de4x5_debug = DE4X5_DEBUG;
564
#else
565
/*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
566
static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
567
#endif
568
 
569
/*
570
** Allow per adapter set up. For modules this is simply a command line
571
** parameter, e.g.:
572
** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
573
**
574
** For a compiled in driver, place e.g.
575
** DE4X5_OPTS = -DDE4X5_PARM='"eth0:fdx autosense=AUI eth2:autosense=TP"'
576
** in linux/drivers/net/CONFIG
577
*/
578
#ifdef DE4X5_PARM
579
static char *args = DE4X5_PARM;
580
#else
581
static char *args = NULL;
582
#endif
583
 
584
struct parameters {
585
    int fdx;
586
    int autosense;
587
};
588
 
589
#define DE4X5_AUTOSENSE_MS 250      /* msec autosense tick (DE500) */
590
 
591
#define DE4X5_NDA 0xffe0            /* No Device (I/O) Address */
592
 
593
/*
594
** Ethernet PROM defines
595
*/
596
#define PROBE_LENGTH    32
597
#define ETH_PROM_SIG    0xAA5500FFUL
598
 
599
/*
600
** Ethernet Info
601
*/
602
#define PKT_BUF_SZ      1536            /* Buffer size for each Tx/Rx buffer */
603
#define IEEE802_3_SZ    1518            /* Packet + CRC */
604
#define MAX_PKT_SZ      1514            /* Maximum ethernet packet length */
605
#define MAX_DAT_SZ      1500            /* Maximum ethernet data length */
606
#define MIN_DAT_SZ      1               /* Minimum ethernet data length */
607
#define PKT_HDR_LEN     14              /* Addresses and data length info */
608
#define FAKE_FRAME_LEN  (MAX_PKT_SZ + 1)
609
#define QUEUE_PKT_TIMEOUT (3*HZ)        /* 3 second timeout */
610
 
611
 
612
#define CRC_POLYNOMIAL_BE 0x04c11db7UL  /* Ethernet CRC, big endian */
613
#define CRC_POLYNOMIAL_LE 0xedb88320UL  /* Ethernet CRC, little endian */
614
 
615
/*
616
** EISA bus defines
617
*/
618
#define DE4X5_EISA_IO_PORTS   0x0c00    /* I/O port base address, slot 0 */
619
#define DE4X5_EISA_TOTAL_SIZE 0x100     /* I/O address extent */
620
 
621
#define MAX_EISA_SLOTS 16
622
#define EISA_SLOT_INC 0x1000
623
#define EISA_ALLOWED_IRQ_LIST  {5, 9, 10, 11}
624
 
625
#define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
626
#define DE4X5_NAME_LENGTH 8
627
 
628
/*
629
** Ethernet PROM defines for DC21040
630
*/
631
#define PROBE_LENGTH    32
632
#define ETH_PROM_SIG    0xAA5500FFUL
633
 
634
/*
635
** PCI Bus defines
636
*/
637
#define PCI_MAX_BUS_NUM      8
638
#define DE4X5_PCI_TOTAL_SIZE 0x80       /* I/O address extent */
639
#define DE4X5_CLASS_CODE     0x00020000 /* Network controller, Ethernet */
640
#define NO_MORE_PCI          -2         /* PCI bus search all done */
641
 
642
/*
643
** Memory Alignment. Each descriptor is 4 longwords long. To force a
644
** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
645
** DESC_ALIGN. ALIGN aligns the start address of the private memory area
646
** and hence the RX descriptor ring's first entry.
647
*/
648
#define ALIGN4      ((u_long)4 - 1)     /* 1 longword align */
649
#define ALIGN8      ((u_long)8 - 1)     /* 2 longword align */
650
#define ALIGN16     ((u_long)16 - 1)    /* 4 longword align */
651
#define ALIGN32     ((u_long)32 - 1)    /* 8 longword align */
652
#define ALIGN64     ((u_long)64 - 1)    /* 16 longword align */
653
#define ALIGN128    ((u_long)128 - 1)   /* 32 longword align */
654
 
655
#define ALIGN         ALIGN32           /* Keep the DC21040 happy... */
656
#define CACHE_ALIGN   CAL_16LONG
657
#define DESC_SKIP_LEN DSL_0             /* Must agree with DESC_ALIGN */
658
/*#define DESC_ALIGN    u32 dummy[4];  / * Must agree with DESC_SKIP_LEN */
659
#define DESC_ALIGN
660
 
661
#ifndef DEC_ONLY                        /* See README.de4x5 for using this */
662
static int dec_only = 0;
663
#else
664
static int dec_only = 1;
665
#endif
666
 
667
/*
668
** DE4X5 IRQ ENABLE/DISABLE
669
*/
670
#define ENABLE_IRQs { \
671
    imr |= lp->irq_en;\
672
    outl(imr, DE4X5_IMR);               /* Enable the IRQs */\
673
}
674
 
675
#define DISABLE_IRQs {\
676
    imr = inl(DE4X5_IMR);\
677
    imr &= ~lp->irq_en;\
678
    outl(imr, DE4X5_IMR);               /* Disable the IRQs */\
679
}
680
 
681
#define UNMASK_IRQs {\
682
    imr |= lp->irq_mask;\
683
    outl(imr, DE4X5_IMR);               /* Unmask the IRQs */\
684
}
685
 
686
#define MASK_IRQs {\
687
    imr = inl(DE4X5_IMR);\
688
    imr &= ~lp->irq_mask;\
689
    outl(imr, DE4X5_IMR);               /* Mask the IRQs */\
690
}
691
 
692
/*
693
** DE4X5 START/STOP
694
*/
695
#define START_DE4X5 {\
696
    omr = inl(DE4X5_OMR);\
697
    omr |= OMR_ST | OMR_SR;\
698
    outl(omr, DE4X5_OMR);               /* Enable the TX and/or RX */\
699
}
700
 
701
#define STOP_DE4X5 {\
702
    omr = inl(DE4X5_OMR);\
703
    omr &= ~(OMR_ST|OMR_SR);\
704
    outl(omr, DE4X5_OMR);               /* Disable the TX and/or RX */ \
705
}
706
 
707
/*
708
** DE4X5 SIA RESET
709
*/
710
#define RESET_SIA outl(0, DE4X5_SICR);  /* Reset SIA connectivity regs */
711
 
712
/*
713
** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
714
*/
715
#define DE4X5_AUTOSENSE_MS  250
716
 
717
/*
718
** SROM Structure
719
*/
720
struct de4x5_srom {
721
    char sub_vendor_id[2];
722
    char sub_system_id[2];
723
    char reserved[12];
724
    char id_block_crc;
725
    char reserved2;
726
    char version;
727
    char num_controllers;
728
    char ieee_addr[6];
729
    char info[100];
730
    short chksum;
731
};
732
#define SUB_VENDOR_ID 0x500a
733
 
734
/*
735
** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
736
** and have sizes of both a power of 2 and a multiple of 4.
737
** A size of 256 bytes for each buffer could be chosen because over 90% of
738
** all packets in our network are <256 bytes long and 64 longword alignment
739
** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
740
** descriptors are needed for machines with an ALPHA CPU.
741
*/
742
#define NUM_RX_DESC 8                   /* Number of RX descriptors   */
743
#define NUM_TX_DESC 32                  /* Number of TX descriptors   */
744
#define RX_BUFF_SZ  1536                /* Power of 2 for kmalloc and */
745
                                        /* Multiple of 4 for DC21040  */
746
                                        /* Allows 512 byte alignment  */
747
struct de4x5_desc {
748
    volatile s32 status;
749
    u32 des1;
750
    u32 buf;
751
    u32 next;
752
    DESC_ALIGN
753
};
754
 
755
/*
756
** The DE4X5 private structure
757
*/
758
#define DE4X5_PKT_STAT_SZ 16
759
#define DE4X5_PKT_BIN_SZ  128            /* Should be >=100 unless you
760
                                            increase DE4X5_PKT_STAT_SZ */
761
 
762
struct de4x5_private {
763
    char adapter_name[80];                  /* Adapter name                 */
764
    u_long interrupt;                       /* Aligned ISR flag             */
765
    struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring           */
766
    struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring           */
767
    struct sk_buff *tx_skb[NUM_TX_DESC];    /* TX skb for freeing when sent */
768
    struct sk_buff *rx_skb[NUM_RX_DESC];    /* RX skb's                     */
769
    int rx_new, rx_old;                     /* RX descriptor ring pointers  */
770
    int tx_new, tx_old;                     /* TX descriptor ring pointers  */
771
    char setup_frame[SETUP_FRAME_LEN];      /* Holds MCA and PA info.       */
772
    char frame[64];                         /* Min sized packet for loopback*/
773
    struct net_device_stats stats;          /* Public stats                 */
774
    struct {
775
        u_int bins[DE4X5_PKT_STAT_SZ];      /* Private stats counters       */
776
        u_int unicast;
777
        u_int multicast;
778
        u_int broadcast;
779
        u_int excessive_collisions;
780
        u_int tx_underruns;
781
        u_int excessive_underruns;
782
        u_int rx_runt_frames;
783
        u_int rx_collision;
784
        u_int rx_dribble;
785
        u_int rx_overflow;
786
    } pktStats;
787
    char rxRingSize;
788
    char txRingSize;
789
    int  bus;                               /* EISA or PCI                  */
790
    int  bus_num;                           /* PCI Bus number               */
791
    int  device;                            /* Device number on PCI bus     */
792
    int  state;                             /* Adapter OPENED or CLOSED     */
793
    int  chipset;                           /* DC21040, DC21041 or DC21140  */
794
    s32  irq_mask;                          /* Interrupt Mask (Enable) bits */
795
    s32  irq_en;                            /* Summary interrupt bits       */
796
    int  media;                             /* Media (eg TP), mode (eg 100B)*/
797
    int  c_media;                           /* Remember the last media conn */
798
    int  fdx;                               /* media full duplex flag       */
799
    int  linkOK;                            /* Link is OK                   */
800
    int  autosense;                         /* Allow/disallow autosensing   */
801
    int  tx_enable;                         /* Enable descriptor polling    */
802
    int  setup_f;                           /* Setup frame filtering type   */
803
    int  local_state;                       /* State within a 'media' state */
804
    struct mii_phy phy[DE4X5_MAX_PHY];      /* List of attached PHY devices */
805
    struct sia_phy sia;                     /* SIA PHY Information          */
806
    int  active;                            /* Index to active PHY device   */
807
    int  mii_cnt;                           /* Number of attached PHY's     */
808
    int  timeout;                           /* Scheduling counter           */
809
    struct timer_list timer;                /* Timer info for kernel        */
810
    int tmp;                                /* Temporary global per card    */
811
    struct {
812
        void *priv;                         /* Original kmalloc'd mem addr  */
813
        void *buf;                          /* Original kmalloc'd mem addr  */
814
        u_long lock;                        /* Lock the cache accesses      */
815
        s32 csr0;                           /* Saved Bus Mode Register      */
816
        s32 csr6;                           /* Saved Operating Mode Reg.    */
817
        s32 csr7;                           /* Saved IRQ Mask Register      */
818
        s32 gep;                            /* Saved General Purpose Reg.   */
819
        s32 gepc;                           /* Control info for GEP         */
820
        s32 csr13;                          /* Saved SIA Connectivity Reg.  */
821
        s32 csr14;                          /* Saved SIA TX/RX Register     */
822
        s32 csr15;                          /* Saved SIA General Register   */
823
        int save_cnt;                       /* Flag if state already saved  */
824
        struct sk_buff *skb;                /* Save the (re-ordered) skb's  */
825
    } cache;
826
    struct de4x5_srom srom;                 /* A copy of the SROM           */
827
    struct device *next_module;             /* Link to the next module      */
828
    int rx_ovf;                             /* Check for 'RX overflow' tag  */
829
    int useSROM;                            /* For non-DEC card use SROM    */
830
    int useMII;                             /* Infoblock using the MII      */
831
    int asBitValid;                         /* Autosense bits in GEP?       */
832
    int asPolarity;                         /* 0 => asserted high           */
833
    int asBit;                              /* Autosense bit number in GEP  */
834
    int defMedium;                          /* SROM default medium          */
835
    int tcount;                             /* Last infoblock number        */
836
    int infoblock_init;                     /* Initialised this infoblock?  */
837
    int infoleaf_offset;                    /* SROM infoleaf for controller */
838
    s32 infoblock_csr6;                     /* csr6 value in SROM infoblock */
839
    int infoblock_media;                    /* infoblock media              */
840
    int (*infoleaf_fn)(struct device *);    /* Pointer to infoleaf function */
841
    u_char *rst;                            /* Pointer to Type 5 reset info */
842
    u_char  ibn;                            /* Infoblock number             */
843
    struct parameters params;               /* Command line/ #defined params */
844
};
845
 
846
/*
847
** Kludge to get around the fact that the CSR addresses have different
848
** offsets in the PCI and EISA boards. Also note that the ethernet address
849
** PROM is accessed differently.
850
*/
851
static struct bus_type {
852
    int bus;
853
    int bus_num;
854
    int device;
855
    int chipset;
856
    struct de4x5_srom srom;
857
    int autosense;
858
    int useSROM;
859
} bus;
860
 
861
/*
862
** To get around certain poxy cards that don't provide an SROM
863
** for the second and more DECchip, I have to key off the first
864
** chip's address. I'll assume there's not a bad SROM iff:
865
**
866
**      o the chipset is the same
867
**      o the bus number is the same and > 0
868
**      o the sum of all the returned hw address bytes is 0 or 0x5fa
869
**
870
** Also have to save the irq for those cards whose hardware designers
871
** can't follow the PCI to PCI Bridge Architecture spec.
872
*/
873
static struct {
874
    int chipset;
875
    int bus;
876
    int irq;
877
    u_char addr[ETH_ALEN];
878
} last = {0,};
879
 
880
/*
881
** The transmit ring full condition is described by the tx_old and tx_new
882
** pointers by:
883
**    tx_old            = tx_new    Empty ring
884
**    tx_old            = tx_new+1  Full ring
885
**    tx_old+txRingSize = tx_new+1  Full ring  (wrapped condition)
886
*/
887
#define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
888
                        lp->tx_old+lp->txRingSize-lp->tx_new-1:\
889
                        lp->tx_old               -lp->tx_new-1)
890
 
891
#define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
892
 
893
/*
894
** Public Functions
895
*/
896
static int     de4x5_open(struct device *dev);
897
static int     de4x5_queue_pkt(struct sk_buff *skb, struct device *dev);
898
static void    de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs);
899
static int     de4x5_close(struct device *dev);
900
static struct  net_device_stats *de4x5_get_stats(struct device *dev);
901
static void    de4x5_local_stats(struct device *dev, char *buf, int pkt_len);
902
static void    set_multicast_list(struct device *dev);
903
static int     de4x5_ioctl(struct device *dev, struct ifreq *rq, int cmd);
904
 
905
/*
906
** Private functions
907
*/
908
static int     de4x5_hw_init(struct device *dev, u_long iobase);
909
static int     de4x5_init(struct device *dev);
910
static int     de4x5_sw_reset(struct device *dev);
911
static int     de4x5_rx(struct device *dev);
912
static int     de4x5_tx(struct device *dev);
913
static int     de4x5_ast(struct device *dev);
914
static int     de4x5_txur(struct device *dev);
915
static int     de4x5_rx_ovfc(struct device *dev);
916
 
917
static int     autoconf_media(struct device *dev);
918
static void    create_packet(struct device *dev, char *frame, int len);
919
static void    de4x5_us_delay(u32 usec);
920
static void    de4x5_ms_delay(u32 msec);
921
static void    load_packet(struct device *dev, char *buf, u32 flags, struct sk_buff *skb);
922
static int     dc21040_autoconf(struct device *dev);
923
static int     dc21041_autoconf(struct device *dev);
924
static int     dc21140m_autoconf(struct device *dev);
925
static int     dc2114x_autoconf(struct device *dev);
926
static int     srom_autoconf(struct device *dev);
927
static int     de4x5_suspect_state(struct device *dev, int timeout, int prev_state, int (*fn)(struct device *, int), int (*asfn)(struct device *));
928
static int     dc21040_state(struct device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct device *, int));
929
static int     test_media(struct device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
930
static int     test_for_100Mb(struct device *dev, int msec);
931
static int     wait_for_link(struct device *dev);
932
static int     test_mii_reg(struct device *dev, int reg, int mask, int pol, long msec);
933
static int     is_spd_100(struct device *dev);
934
static int     is_100_up(struct device *dev);
935
static int     is_10_up(struct device *dev);
936
static int     is_anc_capable(struct device *dev);
937
static int     ping_media(struct device *dev, int msec);
938
static struct sk_buff *de4x5_alloc_rx_buff(struct device *dev, int index, int len);
939
static void    de4x5_free_rx_buffs(struct device *dev);
940
static void    de4x5_free_tx_buffs(struct device *dev);
941
static void    de4x5_save_skbs(struct device *dev);
942
static void    de4x5_rst_desc_ring(struct device *dev);
943
static void    de4x5_cache_state(struct device *dev, int flag);
944
static void    de4x5_put_cache(struct device *dev, struct sk_buff *skb);
945
static void    de4x5_putb_cache(struct device *dev, struct sk_buff *skb);
946
static struct  sk_buff *de4x5_get_cache(struct device *dev);
947
static void    de4x5_setup_intr(struct device *dev);
948
static void    de4x5_init_connection(struct device *dev);
949
static int     de4x5_reset_phy(struct device *dev);
950
static void    reset_init_sia(struct device *dev, s32 sicr, s32 strr, s32 sigr);
951
static int     test_ans(struct device *dev, s32 irqs, s32 irq_mask, s32 msec);
952
static int     test_tp(struct device *dev, s32 msec);
953
static int     EISA_signature(char *name, s32 eisa_id);
954
static int     PCI_signature(char *name, struct bus_type *lp);
955
static void    DevicePresent(u_long iobase);
956
static void    enet_addr_rst(u_long aprom_addr);
957
static int     de4x5_bad_srom(struct bus_type *lp);
958
static short   srom_rd(u_long address, u_char offset);
959
static void    srom_latch(u_int command, u_long address);
960
static void    srom_command(u_int command, u_long address);
961
static void    srom_address(u_int command, u_long address, u_char offset);
962
static short   srom_data(u_int command, u_long address);
963
/*static void    srom_busy(u_int command, u_long address);*/
964
static void    sendto_srom(u_int command, u_long addr);
965
static int     getfrom_srom(u_long addr);
966
static int     srom_map_media(struct device *dev);
967
static int     srom_infoleaf_info(struct device *dev);
968
static void    srom_init(struct device *dev);
969
static void    srom_exec(struct device *dev, u_char *p);
970
static int     mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
971
static void    mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
972
static int     mii_rdata(u_long ioaddr);
973
static void    mii_wdata(int data, int len, u_long ioaddr);
974
static void    mii_ta(u_long rw, u_long ioaddr);
975
static int     mii_swap(int data, int len);
976
static void    mii_address(u_char addr, u_long ioaddr);
977
static void    sendto_mii(u32 command, int data, u_long ioaddr);
978
static int     getfrom_mii(u32 command, u_long ioaddr);
979
static int     mii_get_oui(u_char phyaddr, u_long ioaddr);
980
static int     mii_get_phy(struct device *dev);
981
static void    SetMulticastFilter(struct device *dev);
982
static int     get_hw_addr(struct device *dev);
983
static void    srom_repair(struct device *dev, int card);
984
static int     test_bad_enet(struct device *dev, int status);
985
static int     an_exception(struct bus_type *lp);
986
#if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
987
static void    eisa_probe(struct device *dev, u_long iobase);
988
#endif
989
static void    pci_probe(struct device *dev, u_long iobase);
990
static void    srom_search(int index);
991
static char    *build_setup_frame(struct device *dev, int mode);
992
static void    disable_ast(struct device *dev);
993
static void    enable_ast(struct device *dev, u32 time_out);
994
static long    de4x5_switch_mac_port(struct device *dev);
995
static int     gep_rd(struct device *dev);
996
static void    gep_wr(s32 data, struct device *dev);
997
static void    timeout(struct device *dev, void (*fn)(u_long data), u_long data, u_long msec);
998
static void    yawn(struct device *dev, int state);
999
static void    link_modules(struct device *dev, struct device *tmp);
1000
static void    de4x5_parse_params(struct device *dev);
1001
static void    de4x5_dbg_open(struct device *dev);
1002
static void    de4x5_dbg_mii(struct device *dev, int k);
1003
static void    de4x5_dbg_media(struct device *dev);
1004
static void    de4x5_dbg_srom(struct de4x5_srom *p);
1005
static void    de4x5_dbg_rx(struct sk_buff *skb, int len);
1006
static int     de4x5_strncmp(char *a, char *b, int n);
1007
static int     dc21041_infoleaf(struct device *dev);
1008
static int     dc21140_infoleaf(struct device *dev);
1009
static int     dc21142_infoleaf(struct device *dev);
1010
static int     dc21143_infoleaf(struct device *dev);
1011
static int     type0_infoblock(struct device *dev, u_char count, u_char *p);
1012
static int     type1_infoblock(struct device *dev, u_char count, u_char *p);
1013
static int     type2_infoblock(struct device *dev, u_char count, u_char *p);
1014
static int     type3_infoblock(struct device *dev, u_char count, u_char *p);
1015
static int     type4_infoblock(struct device *dev, u_char count, u_char *p);
1016
static int     type5_infoblock(struct device *dev, u_char count, u_char *p);
1017
static int     compact_infoblock(struct device *dev, u_char count, u_char *p);
1018
 
1019
#ifdef MODULE
1020
int  init_module(void);
1021
void cleanup_module(void);
1022
static struct  device *unlink_modules(struct device *p);
1023
static struct  device *insert_device(struct device *dev, u_long iobase,
1024
                                     int (*init)(struct device *));
1025
static int count_adapters(void);
1026
static int loading_module = 1;
1027
#if LINUX_VERSION_CODE >= LinuxVersionCode(2,1,0)
1028
MODULE_PARM(de4x5_debug, "i");
1029
MODULE_PARM(dec_only, "i");
1030
MODULE_PARM(args, "s");
1031
#endif /* LINUX_VERSION_CODE */
1032
# else
1033
static int loading_module = 0;
1034
#endif /* MODULE */
1035
 
1036
static char name[DE4X5_NAME_LENGTH + 1];
1037
#if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
1038
static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
1039
static int lastEISA = 0;
1040
#else
1041
static int lastEISA = MAX_EISA_SLOTS;           /* Only PCI probes */
1042
#endif
1043
static int num_de4x5s = 0;
1044
static int cfrv = 0, useSROM = 0;
1045
static int lastPCI = -1;
1046
static struct device *lastModule = NULL;
1047
 
1048
/*
1049
** List the SROM infoleaf functions and chipsets
1050
*/
1051
struct InfoLeaf {
1052
    int chipset;
1053
    int (*fn)(struct device *);
1054
};
1055
static struct InfoLeaf infoleaf_array[] = {
1056
    {DC21041, dc21041_infoleaf},
1057
    {DC21140, dc21140_infoleaf},
1058
    {DC21142, dc21142_infoleaf},
1059
    {DC21143, dc21143_infoleaf}
1060
};
1061
#define INFOLEAF_SIZE (sizeof(infoleaf_array)/(sizeof(int)+sizeof(int *)))
1062
 
1063
/*
1064
** List the SROM info block functions
1065
*/
1066
static int (*dc_infoblock[])(struct device *dev, u_char, u_char *) = {
1067
    type0_infoblock,
1068
    type1_infoblock,
1069
    type2_infoblock,
1070
    type3_infoblock,
1071
    type4_infoblock,
1072
    type5_infoblock,
1073
    compact_infoblock
1074
};
1075
 
1076
#define COMPACT (sizeof(dc_infoblock)/sizeof(int *) - 1)
1077
 
1078
/*
1079
** Miscellaneous defines...
1080
*/
1081
#define RESET_DE4X5 {\
1082
    int i;\
1083
    i=inl(DE4X5_BMR);\
1084
    de4x5_ms_delay(1);\
1085
    outl(i | BMR_SWR, DE4X5_BMR);\
1086
    de4x5_ms_delay(1);\
1087
    outl(i, DE4X5_BMR);\
1088
    de4x5_ms_delay(1);\
1089
    for (i=0;i<5;i++) {inl(DE4X5_BMR); de4x5_ms_delay(1);}\
1090
    de4x5_ms_delay(1);\
1091
}
1092
 
1093
#define PHY_HARD_RESET {\
1094
    outl(GEP_HRST, DE4X5_GEP);           /* Hard RESET the PHY dev. */\
1095
    udelay(1000);                        /* Assert for 1ms */\
1096
    outl(0x00, DE4X5_GEP);\
1097
    udelay(2000);                        /* Wait for 2ms */\
1098
}
1099
 
1100
 
1101
/*
1102
** Autoprobing in modules is allowed here. See the top of the file for
1103
** more info.
1104
*/
1105
__initfunc(int
1106
de4x5_probe(struct device *dev))
1107
{
1108
    u_long iobase = dev->base_addr;
1109
 
1110
#if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
1111
    eisa_probe(dev, iobase);
1112
#endif
1113
    if (lastEISA == MAX_EISA_SLOTS) {
1114
        pci_probe(dev, iobase);
1115
    }
1116
 
1117
    return (dev->priv ? 0 : -ENODEV);
1118
}
1119
 
1120
__initfunc(static int
1121
de4x5_hw_init(struct device *dev, u_long iobase))
1122
{
1123
    struct bus_type *lp = &bus;
1124
    int i, status=0;
1125
    char *tmp;
1126
 
1127
    /* Ensure we're not sleeping */
1128
    if (lp->bus == EISA) {
1129
        outb(WAKEUP, PCI_CFPM);
1130
    } else {
1131
        pcibios_write_config_byte(lp->bus_num, lp->device << 3,
1132
                                  PCI_CFDA_PSM, WAKEUP);
1133
    }
1134
    de4x5_ms_delay(10);
1135
 
1136
    RESET_DE4X5;
1137
 
1138
    if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1139
        return -ENXIO;                       /* Hardware could not reset */
1140
    }
1141
 
1142
    /*
1143
    ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1144
    */
1145
    useSROM = FALSE;
1146
    if (lp->bus == PCI) {
1147
        PCI_signature(name, lp);
1148
    } else {
1149
        EISA_signature(name, EISA_ID0);
1150
    }
1151
 
1152
    if (*name == '\0') {                     /* Not found a board signature */
1153
        return -ENXIO;
1154
    }
1155
 
1156
    dev->base_addr = iobase;
1157
    if (lp->bus == EISA) {
1158
        printk("%s: %s at 0x%04lx (EISA slot %ld)",
1159
               dev->name, name, iobase, ((iobase>>12)&0x0f));
1160
    } else {                                 /* PCI port address */
1161
        printk("%s: %s at 0x%04lx (PCI bus %d, device %d)", dev->name, name,
1162
               iobase, lp->bus_num, lp->device);
1163
    }
1164
 
1165
    printk(", h/w address ");
1166
    status = get_hw_addr(dev);
1167
    for (i = 0; i < ETH_ALEN - 1; i++) {     /* get the ethernet addr. */
1168
        printk("%2.2x:", dev->dev_addr[i]);
1169
    }
1170
    printk("%2.2x,\n", dev->dev_addr[i]);
1171
 
1172
    if (status != 0) {
1173
        printk("      which has an Ethernet PROM CRC error.\n");
1174
        return -ENXIO;
1175
    } else {
1176
        struct de4x5_private *lp;
1177
 
1178
        /*
1179
        ** Reserve a section of kernel memory for the adapter
1180
        ** private area and the TX/RX descriptor rings.
1181
        */
1182
        dev->priv = (void *) kmalloc(sizeof(struct de4x5_private) + ALIGN,
1183
                                     GFP_KERNEL);
1184
        if (dev->priv == NULL) {
1185
            return -ENOMEM;
1186
        }
1187
 
1188
        /*
1189
        ** Align to a longword boundary
1190
        */
1191
        tmp = dev->priv;
1192
        dev->priv = (void *)(((u_long)dev->priv + ALIGN) & ~ALIGN);
1193
        lp = (struct de4x5_private *)dev->priv;
1194
        memset(dev->priv, 0, sizeof(struct de4x5_private));
1195
        lp->bus = bus.bus;
1196
        lp->bus_num = bus.bus_num;
1197
        lp->device = bus.device;
1198
        lp->chipset = bus.chipset;
1199
        lp->cache.priv = tmp;
1200
        lp->cache.gepc = GEP_INIT;
1201
        lp->asBit = GEP_SLNK;
1202
        lp->asPolarity = GEP_SLNK;
1203
        lp->asBitValid = TRUE;
1204
        lp->timeout = -1;
1205
        lp->useSROM = useSROM;
1206
        memcpy((char *)&lp->srom,(char *)&bus.srom,sizeof(struct de4x5_srom));
1207
        de4x5_parse_params(dev);
1208
 
1209
        /*
1210
        ** Choose correct autosensing in case someone messed up
1211
        */
1212
        lp->autosense = lp->params.autosense;
1213
        if (lp->chipset != DC21140) {
1214
            if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1215
                lp->params.autosense = TP;
1216
            }
1217
            if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1218
                lp->params.autosense = BNC;
1219
            }
1220
        }
1221
        lp->fdx = lp->params.fdx;
1222
        sprintf(lp->adapter_name,"%s (%s)", name, dev->name);
1223
 
1224
        /*
1225
        ** Set up the RX descriptor ring (Intels)
1226
        ** Allocate contiguous receive buffers, long word aligned (Alphas)
1227
        */
1228
#if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
1229
        for (i=0; i<NUM_RX_DESC; i++) {
1230
            lp->rx_ring[i].status = 0;
1231
            lp->rx_ring[i].des1 = RX_BUFF_SZ;
1232
            lp->rx_ring[i].buf = 0;
1233
            lp->rx_ring[i].next = 0;
1234
            lp->rx_skb[i] = (struct sk_buff *) 1;     /* Dummy entry */
1235
        }
1236
 
1237
#else
1238
        if ((tmp = (void *)kmalloc(RX_BUFF_SZ * NUM_RX_DESC + ALIGN,
1239
                                   GFP_KERNEL)) == NULL) {
1240
            kfree(lp->cache.priv);
1241
            return -ENOMEM;
1242
        }
1243
 
1244
        lp->cache.buf = tmp;
1245
        tmp = (char *)(((u_long) tmp + ALIGN) & ~ALIGN);
1246
        for (i=0; i<NUM_RX_DESC; i++) {
1247
            lp->rx_ring[i].status = 0;
1248
            lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1249
            lp->rx_ring[i].buf = cpu_to_le32(virt_to_bus(tmp+i*RX_BUFF_SZ));
1250
            lp->rx_ring[i].next = 0;
1251
            lp->rx_skb[i] = (struct sk_buff *) 1;     /* Dummy entry */
1252
        }
1253
#endif
1254
 
1255
        barrier();
1256
 
1257
        request_region(iobase, (lp->bus == PCI ? DE4X5_PCI_TOTAL_SIZE :
1258
                                DE4X5_EISA_TOTAL_SIZE),
1259
                       lp->adapter_name);
1260
 
1261
        lp->rxRingSize = NUM_RX_DESC;
1262
        lp->txRingSize = NUM_TX_DESC;
1263
 
1264
        /* Write the end of list marker to the descriptor lists */
1265
        lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1266
        lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1267
 
1268
        /* Tell the adapter where the TX/RX rings are located. */
1269
        outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
1270
        outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
1271
 
1272
        /* Initialise the IRQ mask and Enable/Disable */
1273
        lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1274
        lp->irq_en   = IMR_NIM | IMR_AIM;
1275
 
1276
        /* Create a loopback packet frame for later media probing */
1277
        create_packet(dev, lp->frame, sizeof(lp->frame));
1278
 
1279
        /* Check if the RX overflow bug needs testing for */
1280
        i = cfrv & 0x000000fe;
1281
        if ((lp->chipset == DC21140) && (i == 0x20)) {
1282
            lp->rx_ovf = 1;
1283
        }
1284
 
1285
        /* Initialise the SROM pointers if possible */
1286
        if (lp->useSROM) {
1287
            lp->state = INITIALISED;
1288
            if (srom_infoleaf_info(dev)) {
1289
                return -ENXIO;
1290
            }
1291
            srom_init(dev);
1292
        }
1293
 
1294
        lp->state = CLOSED;
1295
 
1296
        /*
1297
        ** Check for an MII interface
1298
        */
1299
        if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1300
            mii_get_phy(dev);
1301
        }
1302
 
1303
#ifndef __sparc_v9__
1304
        printk("      and requires IRQ%d (provided by %s).\n", dev->irq,
1305
#else
1306
        printk("      and requires IRQ%x (provided by %s).\n", dev->irq,
1307
#endif
1308
               ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1309
    }
1310
 
1311
    if (de4x5_debug & DEBUG_VERSION) {
1312
        printk(version);
1313
    }
1314
 
1315
    /* The DE4X5-specific entries in the device structure. */
1316
    dev->open = &de4x5_open;
1317
    dev->hard_start_xmit = &de4x5_queue_pkt;
1318
    dev->stop = &de4x5_close;
1319
    dev->get_stats = &de4x5_get_stats;
1320
    dev->set_multicast_list = &set_multicast_list;
1321
    dev->do_ioctl = &de4x5_ioctl;
1322
 
1323
    dev->mem_start = 0;
1324
 
1325
    /* Fill in the generic fields of the device structure. */
1326
    ether_setup(dev);
1327
 
1328
    /* Let the adapter sleep to save power */
1329
    yawn(dev, SLEEP);
1330
 
1331
    return status;
1332
}
1333
 
1334
 
1335
static int
1336
de4x5_open(struct device *dev)
1337
{
1338
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1339
    u_long iobase = dev->base_addr;
1340
    int i, status = 0;
1341
    s32 omr;
1342
 
1343
    /* Allocate the RX buffers */
1344
    for (i=0; i<lp->rxRingSize; i++) {
1345
        if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1346
            de4x5_free_rx_buffs(dev);
1347
            return -EAGAIN;
1348
        }
1349
    }
1350
 
1351
    /*
1352
    ** Wake up the adapter
1353
    */
1354
    yawn(dev, WAKEUP);
1355
 
1356
    /*
1357
    ** Re-initialize the DE4X5...
1358
    */
1359
    status = de4x5_init(dev);
1360
    lp->state = OPEN;
1361
    de4x5_dbg_open(dev);
1362
 
1363
    if (request_irq(dev->irq, (void *)de4x5_interrupt, SA_SHIRQ,
1364
                                                     lp->adapter_name, dev)) {
1365
        printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1366
        if (request_irq(dev->irq, de4x5_interrupt, SA_INTERRUPT | SA_SHIRQ,
1367
                                                     lp->adapter_name, dev)) {
1368
            printk("\n              Cannot get IRQ- reconfigure your hardware.\n");
1369
            disable_ast(dev);
1370
            de4x5_free_rx_buffs(dev);
1371
            de4x5_free_tx_buffs(dev);
1372
            yawn(dev, SLEEP);
1373
            lp->state = CLOSED;
1374
            return -EAGAIN;
1375
        } else {
1376
            printk("\n              Succeeded, but you should reconfigure your hardware to avoid this.\n");
1377
            printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1378
        }
1379
    }
1380
 
1381
    dev->tbusy = 0;
1382
    dev->start = 1;
1383
    lp->interrupt = UNMASK_INTERRUPTS;
1384
    dev->trans_start = jiffies;
1385
 
1386
    START_DE4X5;
1387
 
1388
    de4x5_setup_intr(dev);
1389
 
1390
    if (de4x5_debug & DEBUG_OPEN) {
1391
        printk("\tsts:  0x%08x\n", inl(DE4X5_STS));
1392
        printk("\tbmr:  0x%08x\n", inl(DE4X5_BMR));
1393
        printk("\timr:  0x%08x\n", inl(DE4X5_IMR));
1394
        printk("\tomr:  0x%08x\n", inl(DE4X5_OMR));
1395
        printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1396
        printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1397
        printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1398
        printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1399
    }
1400
 
1401
    MOD_INC_USE_COUNT;
1402
 
1403
    return status;
1404
}
1405
 
1406
/*
1407
** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1408
** DC21140 requires using perfect filtering mode for that chip. Since I can't
1409
** see why I'd want > 14 multicast addresses, I have changed all chips to use
1410
** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1411
** to be data corruption problems if it is larger (UDP errors seen from a
1412
** ttcp source).
1413
*/
1414
static int
1415
de4x5_init(struct device *dev)
1416
{
1417
    /* Lock out other processes whilst setting up the hardware */
1418
    test_and_set_bit(0, (void *)&dev->tbusy);
1419
 
1420
    de4x5_sw_reset(dev);
1421
 
1422
    /* Autoconfigure the connected port */
1423
    autoconf_media(dev);
1424
 
1425
    return 0;
1426
}
1427
 
1428
static int
1429
de4x5_sw_reset(struct device *dev)
1430
{
1431
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1432
    u_long iobase = dev->base_addr;
1433
    int i, j, status = 0;
1434
    s32 bmr, omr;
1435
 
1436
    /* Select the MII or SRL port now and RESET the MAC */
1437
    if (!lp->useSROM) {
1438
        if (lp->phy[lp->active].id != 0) {
1439
            lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1440
        } else {
1441
            lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1442
        }
1443
        de4x5_switch_mac_port(dev);
1444
    }
1445
 
1446
    /*
1447
    ** Set the programmable burst length to 8 longwords for all the DC21140
1448
    ** Fasternet chips and 4 longwords for all others: DMA errors result
1449
    ** without these values. Cache align 16 long.
1450
    */
1451
    bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | CACHE_ALIGN;
1452
    bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1453
    outl(bmr, DE4X5_BMR);
1454
 
1455
    omr = inl(DE4X5_OMR) & ~OMR_PR;             /* Turn off promiscuous mode */
1456
    if (lp->chipset == DC21140) {
1457
        omr |= (OMR_SDP | OMR_SB);
1458
    }
1459
    lp->setup_f = PERFECT;
1460
    outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
1461
    outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
1462
 
1463
    lp->rx_new = lp->rx_old = 0;
1464
    lp->tx_new = lp->tx_old = 0;
1465
 
1466
    for (i = 0; i < lp->rxRingSize; i++) {
1467
        lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1468
    }
1469
 
1470
    for (i = 0; i < lp->txRingSize; i++) {
1471
        lp->tx_ring[i].status = cpu_to_le32(0);
1472
    }
1473
 
1474
    barrier();
1475
 
1476
    /* Build the setup frame depending on filtering mode */
1477
    SetMulticastFilter(dev);
1478
 
1479
    load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, NULL);
1480
    outl(omr|OMR_ST, DE4X5_OMR);
1481
 
1482
    /* Poll for setup frame completion (adapter interrupts are disabled now) */
1483
    sti();                                       /* Ensure timer interrupts */
1484
    for (j=0, i=0;(i<500) && (j==0);i++) {       /* Upto 500ms delay */
1485
        udelay(1000);
1486
        if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1487
    }
1488
    outl(omr, DE4X5_OMR);                        /* Stop everything! */
1489
 
1490
    if (j == 0) {
1491
        printk("%s: Setup frame timed out, status %08x\n", dev->name,
1492
               inl(DE4X5_STS));
1493
        status = -EIO;
1494
    }
1495
 
1496
    lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1497
    lp->tx_old = lp->tx_new;
1498
 
1499
    return status;
1500
}
1501
 
1502
/*
1503
** Writes a socket buffer address to the next available transmit descriptor.
1504
*/
1505
static int
1506
de4x5_queue_pkt(struct sk_buff *skb, struct device *dev)
1507
{
1508
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1509
    u_long iobase = dev->base_addr;
1510
    int status = 0;
1511
 
1512
    test_and_set_bit(0, (void*)&dev->tbusy);     /* Stop send re-tries */
1513
    if (lp->tx_enable == NO) {                   /* Cannot send for now */
1514
        return -1;
1515
    }
1516
 
1517
    /*
1518
    ** Clean out the TX ring asynchronously to interrupts - sometimes the
1519
    ** interrupts are lost by delayed descriptor status updates relative to
1520
    ** the irq assertion, especially with a busy PCI bus.
1521
    */
1522
    cli();
1523
    de4x5_tx(dev);
1524
    sti();
1525
 
1526
    /* Test if cache is already locked - requeue skb if so */
1527
    if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1528
        return -1;
1529
 
1530
    /* Transmit descriptor ring full or stale skb */
1531
    if (dev->tbusy || lp->tx_skb[lp->tx_new]) {
1532
        if (lp->interrupt) {
1533
            de4x5_putb_cache(dev, skb);          /* Requeue the buffer */
1534
        } else {
1535
            de4x5_put_cache(dev, skb);
1536
        }
1537
        if (de4x5_debug & DEBUG_TX) {
1538
            printk("%s: transmit busy, lost media or stale skb found:\n  STS:%08x\n  tbusy:%ld\n  IMR:%08x\n  OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), dev->tbusy, inl(DE4X5_IMR), inl(DE4X5_OMR), (lp->tx_skb[lp->tx_new] ? "YES" : "NO"));
1539
        }
1540
    } else if (skb->len > 0) {
1541
        /* If we already have stuff queued locally, use that first */
1542
        if (lp->cache.skb && !lp->interrupt) {
1543
            de4x5_put_cache(dev, skb);
1544
            skb = de4x5_get_cache(dev);
1545
        }
1546
 
1547
        while (skb && !dev->tbusy && !lp->tx_skb[lp->tx_new]) {
1548
            cli();
1549
            test_and_set_bit(0, (void*)&dev->tbusy);
1550
            load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1551
#if     LINUX_VERSION_CODE >= ((2 << 16) | (1 << 8))
1552
            lp->stats.tx_bytes += skb->len;
1553
#endif
1554
            outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1555
 
1556
            lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1557
            dev->trans_start = jiffies;
1558
 
1559
            if (TX_BUFFS_AVAIL) {
1560
                dev->tbusy = 0;         /* Another pkt may be queued */
1561
            }
1562
            skb = de4x5_get_cache(dev);
1563
            sti();
1564
        }
1565
        if (skb) de4x5_putb_cache(dev, skb);
1566
    }
1567
 
1568
    lp->cache.lock = 0;
1569
 
1570
    return status;
1571
}
1572
 
1573
/*
1574
** The DE4X5 interrupt handler.
1575
**
1576
** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1577
** so that the asserted interrupt always has some real data to work with -
1578
** if these I/O accesses are ever changed to memory accesses, ensure the
1579
** STS write is read immediately to complete the transaction if the adapter
1580
** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1581
** is high and descriptor status bits cannot be set before the associated
1582
** interrupt is asserted and this routine entered.
1583
*/
1584
static void
1585
de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1586
{
1587
    struct device *dev = (struct device *)dev_id;
1588
    struct de4x5_private *lp;
1589
    s32 imr, omr, sts, limit;
1590
    u_long iobase;
1591
 
1592
    if (dev == NULL) {
1593
        printk ("de4x5_interrupt(): irq %d for unknown device.\n", irq);
1594
        return;
1595
    }
1596
    lp = (struct de4x5_private *)dev->priv;
1597
    iobase = dev->base_addr;
1598
 
1599
    DISABLE_IRQs;                        /* Ensure non re-entrancy */
1600
 
1601
    if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1602
        printk("%s: Re-entering the interrupt handler.\n", dev->name);
1603
 
1604
#if     LINUX_VERSION_CODE >= ((2 << 16) | (1 << 8))
1605
    synchronize_irq();
1606
#endif
1607
 
1608
    for (limit=0; limit<8; limit++) {
1609
        sts = inl(DE4X5_STS);            /* Read IRQ status */
1610
        outl(sts, DE4X5_STS);            /* Reset the board interrupts */
1611
 
1612
        if (!(sts & lp->irq_mask)) break;/* All done */
1613
 
1614
        if (sts & (STS_RI | STS_RU))     /* Rx interrupt (packet[s] arrived) */
1615
          de4x5_rx(dev);
1616
 
1617
        if (sts & (STS_TI | STS_TU))     /* Tx interrupt (packet sent) */
1618
          de4x5_tx(dev);
1619
 
1620
        if (sts & STS_LNF) {             /* TP Link has failed */
1621
            lp->irq_mask &= ~IMR_LFM;
1622
        }
1623
 
1624
        if (sts & STS_UNF) {             /* Transmit underrun */
1625
            de4x5_txur(dev);
1626
        }
1627
 
1628
        if (sts & STS_SE) {              /* Bus Error */
1629
            STOP_DE4X5;
1630
            printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1631
                   dev->name, sts);
1632
            return;
1633
        }
1634
    }
1635
 
1636
    /* Load the TX ring with any locally stored packets */
1637
    if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1638
        while (lp->cache.skb && !dev->tbusy && lp->tx_enable) {
1639
            de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1640
        }
1641
        lp->cache.lock = 0;
1642
    }
1643
 
1644
    lp->interrupt = UNMASK_INTERRUPTS;
1645
    ENABLE_IRQs;
1646
 
1647
    return;
1648
}
1649
 
1650
static int
1651
de4x5_rx(struct device *dev)
1652
{
1653
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1654
    u_long iobase = dev->base_addr;
1655
    int entry;
1656
    s32 status;
1657
 
1658
    for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1659
                                                            entry=lp->rx_new) {
1660
        status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1661
 
1662
        if (lp->rx_ovf) {
1663
            if (inl(DE4X5_MFC) & MFC_FOCM) {
1664
                de4x5_rx_ovfc(dev);
1665
                break;
1666
            }
1667
        }
1668
 
1669
        if (status & RD_FS) {                 /* Remember the start of frame */
1670
            lp->rx_old = entry;
1671
        }
1672
 
1673
        if (status & RD_LS) {                 /* Valid frame status */
1674
            if (lp->tx_enable) lp->linkOK++;
1675
            if (status & RD_ES) {             /* There was an error. */
1676
                lp->stats.rx_errors++;        /* Update the error stats. */
1677
                if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1678
                if (status & RD_CE)           lp->stats.rx_crc_errors++;
1679
                if (status & RD_OF)           lp->stats.rx_fifo_errors++;
1680
                if (status & RD_TL)           lp->stats.rx_length_errors++;
1681
                if (status & RD_RF)           lp->pktStats.rx_runt_frames++;
1682
                if (status & RD_CS)           lp->pktStats.rx_collision++;
1683
                if (status & RD_DB)           lp->pktStats.rx_dribble++;
1684
                if (status & RD_OF)           lp->pktStats.rx_overflow++;
1685
            } else {                          /* A valid frame received */
1686
                struct sk_buff *skb;
1687
                short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1688
                                                                    >> 16) - 4;
1689
 
1690
                if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1691
                    printk("%s: Insufficient memory; nuking packet.\n",
1692
                                                                    dev->name);
1693
                    lp->stats.rx_dropped++;
1694
                } else {
1695
                    de4x5_dbg_rx(skb, pkt_len);
1696
 
1697
                    /* Push up the protocol stack */
1698
                    skb->protocol=eth_type_trans(skb,dev);
1699
                    netif_rx(skb);
1700
 
1701
                    /* Update stats */
1702
                    lp->stats.rx_packets++;
1703
#if     LINUX_VERSION_CODE >= ((2 << 16) | (1 << 8))
1704
                    lp->stats.rx_bytes += pkt_len;
1705
#endif
1706
                    de4x5_local_stats(dev, skb->data, pkt_len);
1707
                }
1708
            }
1709
 
1710
            /* Change buffer ownership for this frame, back to the adapter */
1711
            for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1712
                lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1713
                barrier();
1714
            }
1715
            lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1716
            barrier();
1717
        }
1718
 
1719
        /*
1720
        ** Update entry information
1721
        */
1722
        lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1723
    }
1724
 
1725
    return 0;
1726
}
1727
 
1728
/*
1729
** Buffer sent - check for TX buffer errors.
1730
*/
1731
static int
1732
de4x5_tx(struct device *dev)
1733
{
1734
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1735
    u_long iobase = dev->base_addr;
1736
    int entry;
1737
    s32 status;
1738
 
1739
    for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1740
        status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1741
        if (status < 0) {                     /* Buffer not sent yet */
1742
            break;
1743
        } else if (status != 0x7fffffff) {    /* Not setup frame */
1744
            if (status & TD_ES) {             /* An error happened */
1745
                lp->stats.tx_errors++;
1746
                if (status & TD_NC) lp->stats.tx_carrier_errors++;
1747
                if (status & TD_LC) lp->stats.tx_window_errors++;
1748
                if (status & TD_UF) lp->stats.tx_fifo_errors++;
1749
                if (status & TD_EC) lp->pktStats.excessive_collisions++;
1750
                if (status & TD_DE) lp->stats.tx_aborted_errors++;
1751
 
1752
                if (TX_PKT_PENDING) {
1753
                    outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1754
                }
1755
            } else {                      /* Packet sent */
1756
                lp->stats.tx_packets++;
1757
                if (lp->tx_enable) lp->linkOK++;
1758
            }
1759
            /* Update the collision counter */
1760
            lp->stats.collisions += ((status & TD_EC) ? 16 :
1761
                                                      ((status & TD_CC) >> 3));
1762
 
1763
            /* Free the buffer. */
1764
            if (lp->tx_skb[entry] != NULL) {
1765
                dev_kfree_skb(lp->tx_skb[entry], FREE_WRITE);
1766
                lp->tx_skb[entry] = NULL;
1767
            }
1768
        }
1769
 
1770
        /* Update all the pointers */
1771
        lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1772
    }
1773
 
1774
    if (TX_BUFFS_AVAIL && dev->tbusy) {  /* Any resources available? */
1775
        dev->tbusy = 0;                  /* Clear TX busy flag */
1776
        if (lp->interrupt) mark_bh(NET_BH);
1777
    }
1778
 
1779
    return 0;
1780
}
1781
 
1782
static int
1783
de4x5_ast(struct device *dev)
1784
{
1785
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1786
    int next_tick = DE4X5_AUTOSENSE_MS;
1787
 
1788
    disable_ast(dev);
1789
 
1790
    if (lp->useSROM) {
1791
        next_tick = srom_autoconf(dev);
1792
    } else if (lp->chipset == DC21140) {
1793
        next_tick = dc21140m_autoconf(dev);
1794
    } else if (lp->chipset == DC21041) {
1795
        next_tick = dc21041_autoconf(dev);
1796
    } else if (lp->chipset == DC21040) {
1797
        next_tick = dc21040_autoconf(dev);
1798
    }
1799
    lp->linkOK = 0;
1800
    enable_ast(dev, next_tick);
1801
 
1802
    return 0;
1803
}
1804
 
1805
static int
1806
de4x5_txur(struct device *dev)
1807
{
1808
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1809
    u_long iobase = dev->base_addr;
1810
    int omr;
1811
 
1812
    omr = inl(DE4X5_OMR);
1813
    if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1814
        omr &= ~(OMR_ST|OMR_SR);
1815
        outl(omr, DE4X5_OMR);
1816
        while (inl(DE4X5_STS) & STS_TS);
1817
        if ((omr & OMR_TR) < OMR_TR) {
1818
            omr += 0x4000;
1819
        } else {
1820
            omr |= OMR_SF;
1821
        }
1822
        outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1823
    }
1824
 
1825
    return 0;
1826
}
1827
 
1828
static int
1829
de4x5_rx_ovfc(struct device *dev)
1830
{
1831
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1832
    u_long iobase = dev->base_addr;
1833
    int omr;
1834
 
1835
    omr = inl(DE4X5_OMR);
1836
    outl(omr & ~OMR_SR, DE4X5_OMR);
1837
    while (inl(DE4X5_STS) & STS_RS);
1838
 
1839
    for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1840
        lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1841
        lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1842
    }
1843
 
1844
    outl(omr, DE4X5_OMR);
1845
 
1846
    return 0;
1847
}
1848
 
1849
static int
1850
de4x5_close(struct device *dev)
1851
{
1852
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1853
    u_long iobase = dev->base_addr;
1854
    s32 imr, omr;
1855
 
1856
    disable_ast(dev);
1857
    dev->start = 0;
1858
    dev->tbusy = 1;
1859
 
1860
    if (de4x5_debug & DEBUG_CLOSE) {
1861
        printk("%s: Shutting down ethercard, status was %8.8x.\n",
1862
               dev->name, inl(DE4X5_STS));
1863
    }
1864
 
1865
    /*
1866
    ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1867
    */
1868
    DISABLE_IRQs;
1869
    STOP_DE4X5;
1870
 
1871
    /* Free the associated irq */
1872
    free_irq(dev->irq, dev);
1873
    lp->state = CLOSED;
1874
 
1875
    /* Free any socket buffers */
1876
    de4x5_free_rx_buffs(dev);
1877
    de4x5_free_tx_buffs(dev);
1878
 
1879
    MOD_DEC_USE_COUNT;
1880
 
1881
    /* Put the adapter to sleep to save power */
1882
    yawn(dev, SLEEP);
1883
 
1884
    return 0;
1885
}
1886
 
1887
static struct net_device_stats *
1888
de4x5_get_stats(struct device *dev)
1889
{
1890
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1891
    u_long iobase = dev->base_addr;
1892
 
1893
    lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1894
 
1895
    return &lp->stats;
1896
}
1897
 
1898
static void
1899
de4x5_local_stats(struct device *dev, char *buf, int pkt_len)
1900
{
1901
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1902
    int i;
1903
 
1904
    for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1905
        if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1906
            lp->pktStats.bins[i]++;
1907
            i = DE4X5_PKT_STAT_SZ;
1908
        }
1909
    }
1910
    if (buf[0] & 0x01) {          /* Multicast/Broadcast */
1911
        if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1912
            lp->pktStats.broadcast++;
1913
        } else {
1914
            lp->pktStats.multicast++;
1915
        }
1916
    } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1917
               (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1918
        lp->pktStats.unicast++;
1919
    }
1920
 
1921
    lp->pktStats.bins[0]++;       /* Duplicates stats.rx_packets */
1922
    if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1923
        memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1924
    }
1925
 
1926
    return;
1927
}
1928
 
1929
static void
1930
load_packet(struct device *dev, char *buf, u32 flags, struct sk_buff *skb)
1931
{
1932
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1933
 
1934
    lp->tx_ring[lp->tx_new].buf = cpu_to_le32(virt_to_bus(buf));
1935
    lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1936
    lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1937
    lp->tx_skb[lp->tx_new] = skb;
1938
    barrier();
1939
    lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1940
    barrier();
1941
 
1942
    return;
1943
}
1944
 
1945
/*
1946
** Set or clear the multicast filter for this adaptor.
1947
*/
1948
static void
1949
set_multicast_list(struct device *dev)
1950
{
1951
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1952
    u_long iobase = dev->base_addr;
1953
 
1954
    /* First, double check that the adapter is open */
1955
    if (lp->state == OPEN) {
1956
        if (dev->flags & IFF_PROMISC) {         /* set promiscuous mode */
1957
            u32 omr;
1958
            omr = inl(DE4X5_OMR);
1959
            omr |= OMR_PR;
1960
            outl(omr, DE4X5_OMR);
1961
        } else {
1962
            SetMulticastFilter(dev);
1963
            load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1964
                                                        SETUP_FRAME_LEN, NULL);
1965
 
1966
            lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1967
            outl(POLL_DEMAND, DE4X5_TPD);       /* Start the TX */
1968
            dev->trans_start = jiffies;
1969
        }
1970
    }
1971
 
1972
    return;
1973
}
1974
 
1975
/*
1976
** Calculate the hash code and update the logical address filter
1977
** from a list of ethernet multicast addresses.
1978
** Little endian crc one liner from Matt Thomas, DEC.
1979
*/
1980
static void
1981
SetMulticastFilter(struct device *dev)
1982
{
1983
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1984
    struct dev_mc_list *dmi=dev->mc_list;
1985
    u_long iobase = dev->base_addr;
1986
    int i, j, bit, byte;
1987
    u16 hashcode;
1988
    u32 omr, crc, poly = CRC_POLYNOMIAL_LE;
1989
    char *pa;
1990
    unsigned char *addrs;
1991
 
1992
    omr = inl(DE4X5_OMR);
1993
    omr &= ~(OMR_PR | OMR_PM);
1994
    pa = build_setup_frame(dev, ALL);        /* Build the basic frame */
1995
 
1996
    if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
1997
        omr |= OMR_PM;                       /* Pass all multicasts */
1998
    } else if (lp->setup_f == HASH_PERF) {   /* Hash Filtering */
1999
        for (i=0;i<dev->mc_count;i++) {      /* for each address in the list */
2000
            addrs=dmi->dmi_addr;
2001
            dmi=dmi->next;
2002
            if ((*addrs & 0x01) == 1) {      /* multicast address? */
2003
                crc = 0xffffffff;            /* init CRC for each address */
2004
                for (byte=0;byte<ETH_ALEN;byte++) {/* for each address byte */
2005
                                             /* process each address bit */
2006
                    for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
2007
                        crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
2008
                    }
2009
                }
2010
                hashcode = crc & HASH_BITS;  /* hashcode is 9 LSb of CRC */
2011
 
2012
                byte = hashcode >> 3;        /* bit[3-8] -> byte in filter */
2013
                bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
2014
 
2015
                byte <<= 1;                  /* calc offset into setup frame */
2016
                if (byte & 0x02) {
2017
                    byte -= 1;
2018
                }
2019
                lp->setup_frame[byte] |= bit;
2020
            }
2021
        }
2022
    } else {                                 /* Perfect filtering */
2023
        for (j=0; j<dev->mc_count; j++) {
2024
            addrs=dmi->dmi_addr;
2025
            dmi=dmi->next;
2026
            for (i=0; i<ETH_ALEN; i++) {
2027
                *(pa + (i&1)) = *addrs++;
2028
                if (i & 0x01) pa += 4;
2029
            }
2030
        }
2031
    }
2032
    outl(omr, DE4X5_OMR);
2033
 
2034
    return;
2035
}
2036
 
2037
#if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
2038
/*
2039
** EISA bus I/O device probe. Probe from slot 1 since slot 0 is usually
2040
** the motherboard. Upto 15 EISA devices are supported.
2041
*/
2042
__initfunc(static void
2043
eisa_probe(struct device *dev, u_long ioaddr))
2044
{
2045
    int i, maxSlots, status, device;
2046
    u_char irq;
2047
    u_short vendor;
2048
    u32 cfid;
2049
    u_long iobase;
2050
    struct bus_type *lp = &bus;
2051
    char name[DE4X5_STRLEN];
2052
 
2053
    if (lastEISA == MAX_EISA_SLOTS) return;/* No more EISA devices to search */
2054
 
2055
    lp->bus = EISA;
2056
 
2057
    if (ioaddr == 0) {                     /* Autoprobing */
2058
        iobase = EISA_SLOT_INC;            /* Get the first slot address */
2059
        i = 1;
2060
        maxSlots = MAX_EISA_SLOTS;
2061
    } else {                               /* Probe a specific location */
2062
        iobase = ioaddr;
2063
        i = (ioaddr >> 12);
2064
        maxSlots = i + 1;
2065
    }
2066
 
2067
    for (status = -ENODEV; (i<maxSlots) && (dev!=NULL); i++, iobase+=EISA_SLOT_INC) {
2068
        if (EISA_signature(name, EISA_ID)) {
2069
            cfid = (u32) inl(PCI_CFID);
2070
            cfrv = (u_short) inl(PCI_CFRV);
2071
            device = (cfid >> 8) & 0x00ffff00;
2072
            vendor = (u_short) cfid;
2073
 
2074
            /* Read the EISA Configuration Registers */
2075
            irq = inb(EISA_REG0);
2076
            irq = de4x5_irq[(irq >> 1) & 0x03];
2077
 
2078
            if (is_DC2114x) {
2079
                device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2080
            }
2081
            lp->chipset = device;
2082
 
2083
            /* Write the PCI Configuration Registers */
2084
            outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2085
            outl(0x00006000, PCI_CFLT);
2086
            outl(iobase, PCI_CBIO);
2087
 
2088
            DevicePresent(EISA_APROM);
2089
            if (check_region(iobase, DE4X5_EISA_TOTAL_SIZE) == 0) {
2090
                dev->irq = irq;
2091
                if ((status = de4x5_hw_init(dev, iobase)) == 0) {
2092
                    num_de4x5s++;
2093
                    if (loading_module) link_modules(lastModule, dev);
2094
                    lastEISA = i;
2095
                    return;
2096
                }
2097
            } else if (ioaddr != 0) {
2098
                printk("%s: region already allocated at 0x%04lx.\n", dev->name,iobase);
2099
            }
2100
        }
2101
    }
2102
 
2103
    if (ioaddr == 0) lastEISA = i;
2104
 
2105
    return;
2106
}
2107
#endif          /* !(__sparc_v9__) && !(__powerpc__) && !defined(__alpha__)*/
2108
 
2109
/*
2110
** PCI bus I/O device probe
2111
** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2112
** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2113
** enabled by the user first in the set up utility. Hence we just check for
2114
** enabled features and silently ignore the card if they're not.
2115
**
2116
** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2117
** bit. Here, check for I/O accesses and then set BM. If you put the card in
2118
** a non BM slot, you're on your own (and complain to the PC vendor that your
2119
** PC doesn't conform to the PCI standard)!
2120
*/
2121
#define PCI_DEVICE    (dev_num << 3)
2122
#define PCI_LAST_DEV  32
2123
 
2124
__initfunc(static void
2125
pci_probe(struct device *dev, u_long ioaddr))
2126
{
2127
    u_char pb, pbus, dev_num, dnum, dev_fn, timer, tirq;
2128
    u_short dev_id, vendor, index, status;
2129
    u_int tmp, irq = 0, device, class = DE4X5_CLASS_CODE;
2130
    u_long iobase = 0;                     /* Clear upper 32 bits in Alphas */
2131
    struct bus_type *lp = &bus;
2132
 
2133
    if (lastPCI == NO_MORE_PCI) return;
2134
 
2135
    if (!pcibios_present()) {
2136
        lastPCI = NO_MORE_PCI;
2137
        return;          /* No PCI bus in this machine! */
2138
    }
2139
 
2140
    lp->bus = PCI;
2141
    lp->bus_num = 0;
2142
 
2143
    if ((ioaddr < 0x1000) && loading_module) {
2144
        pbus = (u_short)(ioaddr >> 8);
2145
        dnum = (u_short)(ioaddr & 0xff);
2146
    } else {
2147
        pbus = 0;
2148
        dnum = 0;
2149
    }
2150
 
2151
    for (index=lastPCI+1;
2152
         (pcibios_find_class(class, index, &pb, &dev_fn)!= PCIBIOS_DEVICE_NOT_FOUND);
2153
         index++) {
2154
        dev_num = PCI_SLOT(dev_fn);
2155
        if ((!pbus && !dnum) || ((pbus == pb) && (dnum == dev_num))) {
2156
#ifdef __sparc_v9__
2157
            struct pci_dev *pdev;
2158
            for (pdev = pci_devices; pdev; pdev = pdev->next) {
2159
                if ((pdev->bus->number==pb) && (pdev->devfn==dev_fn)) break;
2160
            }
2161
#endif
2162
            device = 0;
2163
            pcibios_read_config_word(pb, PCI_DEVICE, PCI_VENDOR_ID, &vendor);
2164
            pcibios_read_config_word(pb, PCI_DEVICE, PCI_DEVICE_ID, &dev_id);
2165
            device = dev_id;
2166
            device <<= 8;
2167
            if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) {
2168
                continue;
2169
            }
2170
 
2171
            /* Search for an SROM on this bus */
2172
            if (lp->bus_num != pb) {
2173
                lp->bus_num = pb;
2174
                srom_search(index);
2175
            }
2176
 
2177
            /* Get the chip configuration revision register */
2178
            pcibios_read_config_dword(pb, PCI_DEVICE, PCI_REVISION_ID, &cfrv);
2179
 
2180
            /* Set the device number information */
2181
            lp->device = dev_num;
2182
            lp->bus_num = pb;
2183
 
2184
            /* Set the chipset information */
2185
            if (is_DC2114x) {
2186
                device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2187
            }
2188
            lp->chipset = device;
2189
 
2190
            /* Get the board I/O address (64 bits on sparc64) */
2191
#ifndef __sparc_v9__
2192
            pcibios_read_config_dword(pb, PCI_DEVICE, PCI_BASE_ADDRESS_0, &tmp);
2193
            iobase = tmp;
2194
#else
2195
            iobase = pdev->base_address[0];
2196
#endif
2197
            iobase &= CBIO_MASK;
2198
 
2199
            /* Fetch the IRQ to be used */
2200
#ifndef __sparc_v9__
2201
            pcibios_read_config_byte(pb, PCI_DEVICE, PCI_INTERRUPT_LINE, &tirq);
2202
            irq = tirq;
2203
#else
2204
            irq = pdev->irq;
2205
#endif
2206
            if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2207
 
2208
            /* Check if I/O accesses and Bus Mastering are enabled */
2209
            pcibios_read_config_word(pb, PCI_DEVICE, PCI_COMMAND, &status);
2210
#ifdef __powerpc__
2211
            if (!(status & PCI_COMMAND_IO)) {
2212
                status |= PCI_COMMAND_IO;
2213
                pcibios_write_config_word(pb, PCI_DEVICE, PCI_COMMAND, status);
2214
                pcibios_read_config_word(pb, PCI_DEVICE, PCI_COMMAND, &status);
2215
            }
2216
#endif /* __powerpc__ */
2217
            if (!(status & PCI_COMMAND_IO)) continue;
2218
 
2219
            if (!(status & PCI_COMMAND_MASTER)) {
2220
                status |= PCI_COMMAND_MASTER;
2221
                pcibios_write_config_word(pb, PCI_DEVICE, PCI_COMMAND, status);
2222
                pcibios_read_config_word(pb, PCI_DEVICE, PCI_COMMAND, &status);
2223
            }
2224
            if (!(status & PCI_COMMAND_MASTER)) continue;
2225
 
2226
            /* Check the latency timer for values >= 0x60 */
2227
            pcibios_read_config_byte(pb, PCI_DEVICE, PCI_LATENCY_TIMER, &timer);
2228
            if (timer < 0x60) {
2229
                pcibios_write_config_byte(pb, PCI_DEVICE, PCI_LATENCY_TIMER, 0x60);
2230
            }
2231
 
2232
            DevicePresent(DE4X5_APROM);
2233
            if (check_region(iobase, DE4X5_PCI_TOTAL_SIZE) == 0) {
2234
                dev->irq = irq;
2235
                if ((status = de4x5_hw_init(dev, iobase)) == 0) {
2236
                    num_de4x5s++;
2237
                    lastPCI = index;
2238
                    if (loading_module) link_modules(lastModule, dev);
2239
                    return;
2240
                }
2241
            } else if (ioaddr != 0) {
2242
                printk("%s: region already allocated at 0x%04lx.\n", dev->name,
2243
                       iobase);
2244
            }
2245
        }
2246
    }
2247
 
2248
    lastPCI = NO_MORE_PCI;
2249
 
2250
    return;
2251
}
2252
 
2253
/*
2254
** This function searches the current bus (which is >0) for a DECchip with an
2255
** SROM, so that in multiport cards that have one SROM shared between multiple
2256
** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2257
** For single port cards this is a time waster...
2258
*/
2259
__initfunc(static void
2260
srom_search(int index))
2261
{
2262
    u_char pb, dev_fn, tirq;
2263
    u_short dev_id, dev_num, vendor, status;
2264
    u_int tmp, irq = 0, device, class = DE4X5_CLASS_CODE;
2265
    u_long iobase = 0;                     /* Clear upper 32 bits in Alphas */
2266
    int i, j;
2267
    struct bus_type *lp = &bus;
2268
 
2269
    for (;
2270
         (pcibios_find_class(class, index, &pb, &dev_fn)!= PCIBIOS_DEVICE_NOT_FOUND);
2271
         index++) {
2272
 
2273
        if (lp->bus_num != pb) return;
2274
        dev_num = PCI_SLOT(dev_fn);
2275
#ifdef __sparc_v9__
2276
        struct pci_dev *pdev;
2277
        for (pdev = pci_devices; pdev; pdev = pdev->next) {
2278
            if ((pdev->bus->number == pb) && (pdev->devfn == dev_fn)) break;
2279
        }
2280
#endif
2281
        device = 0;
2282
        pcibios_read_config_word(pb, PCI_DEVICE, PCI_VENDOR_ID, &vendor);
2283
        pcibios_read_config_word(pb, PCI_DEVICE, PCI_DEVICE_ID, &dev_id);
2284
        device = dev_id;
2285
        device <<= 8;
2286
        if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) {
2287
            continue;
2288
        }
2289
 
2290
        /* Get the chip configuration revision register */
2291
        pcibios_read_config_dword(pb, PCI_DEVICE, PCI_REVISION_ID, &cfrv);
2292
 
2293
        /* Set the device number information */
2294
        lp->device = dev_num;
2295
        lp->bus_num = pb;
2296
 
2297
        /* Set the chipset information */
2298
        if (is_DC2114x) {
2299
            device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2300
        }
2301
        lp->chipset = device;
2302
 
2303
        /* Get the board I/O address (64 bits on sparc64) */
2304
#ifndef __sparc_v9__
2305
        pcibios_read_config_dword(pb, PCI_DEVICE, PCI_BASE_ADDRESS_0, &tmp);
2306
        iobase = tmp;
2307
#else
2308
        iobase = pdev->base_address[0];
2309
#endif
2310
        iobase &= CBIO_MASK;
2311
 
2312
        /* Fetch the IRQ to be used */
2313
#ifndef __sparc_v9__
2314
        pcibios_read_config_byte(pb, PCI_DEVICE, PCI_INTERRUPT_LINE, &tirq);
2315
        irq = tirq;
2316
#else
2317
        irq = pdev->irq;
2318
#endif
2319
        if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2320
 
2321
        /* Check if I/O accesses are enabled */
2322
        pcibios_read_config_word(pb, PCI_DEVICE, PCI_COMMAND, &status);
2323
        if (!(status & PCI_COMMAND_IO)) continue;
2324
 
2325
        /* Search for a valid SROM attached to this DECchip */
2326
        DevicePresent(DE4X5_APROM);
2327
        for (j=0, i=0; i<ETH_ALEN; i++) {
2328
            j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2329
        }
2330
        if ((j != 0) && (j != 0x5fa)) {
2331
            last.chipset = device;
2332
            last.bus = pb;
2333
            last.irq = irq;
2334
            for (i=0; i<ETH_ALEN; i++) {
2335
                last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2336
            }
2337
            return;
2338
        }
2339
    }
2340
 
2341
    return;
2342
}
2343
 
2344
__initfunc(static void
2345
link_modules(struct device *dev, struct device *tmp))
2346
{
2347
    struct device *p=dev;
2348
 
2349
    if (p) {
2350
        while (((struct de4x5_private *)(p->priv))->next_module) {
2351
            p = ((struct de4x5_private *)(p->priv))->next_module;
2352
        }
2353
 
2354
        if (dev != tmp) {
2355
            ((struct de4x5_private *)(p->priv))->next_module = tmp;
2356
        } else {
2357
            ((struct de4x5_private *)(p->priv))->next_module = NULL;
2358
        }
2359
    }
2360
 
2361
    return;
2362
}
2363
 
2364
/*
2365
** Auto configure the media here rather than setting the port at compile
2366
** time. This routine is called by de4x5_init() and when a loss of media is
2367
** detected (excessive collisions, loss of carrier, no carrier or link fail
2368
** [TP] or no recent receive activity) to check whether the user has been
2369
** sneaky and changed the port on us.
2370
*/
2371
static int
2372
autoconf_media(struct device *dev)
2373
{
2374
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2375
    u_long iobase = dev->base_addr;
2376
    int next_tick = DE4X5_AUTOSENSE_MS;
2377
 
2378
    lp->linkOK = 0;
2379
    lp->c_media = AUTO;                     /* Bogus last media */
2380
    disable_ast(dev);
2381
    inl(DE4X5_MFC);                         /* Zero the lost frames counter */
2382
    lp->media = INIT;
2383
    lp->tcount = 0;
2384
 
2385
    if (lp->useSROM) {
2386
        next_tick = srom_autoconf(dev);
2387
    } else if (lp->chipset == DC21040) {
2388
        next_tick = dc21040_autoconf(dev);
2389
    } else if (lp->chipset == DC21041) {
2390
        next_tick = dc21041_autoconf(dev);
2391
    } else if (lp->chipset == DC21140) {
2392
        next_tick = dc21140m_autoconf(dev);
2393
    }
2394
 
2395
    enable_ast(dev, next_tick);
2396
 
2397
    return (lp->media);
2398
}
2399
 
2400
/*
2401
** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2402
** from BNC as the port has a jumper to set thick or thin wire. When set for
2403
** BNC, the BNC port will indicate activity if it's not terminated correctly.
2404
** The only way to test for that is to place a loopback packet onto the
2405
** network and watch for errors. Since we're messing with the interrupt mask
2406
** register, disable the board interrupts and do not allow any more packets to
2407
** be queued to the hardware. Re-enable everything only when the media is
2408
** found.
2409
** I may have to "age out" locally queued packets so that the higher layer
2410
** timeouts don't effectively duplicate packets on the network.
2411
*/
2412
static int
2413
dc21040_autoconf(struct device *dev)
2414
{
2415
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2416
    u_long iobase = dev->base_addr;
2417
    int next_tick = DE4X5_AUTOSENSE_MS;
2418
    s32 imr;
2419
 
2420
    switch (lp->media) {
2421
    case INIT:
2422
        DISABLE_IRQs;
2423
        lp->tx_enable = NO;
2424
        lp->timeout = -1;
2425
        de4x5_save_skbs(dev);
2426
        if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2427
            lp->media = TP;
2428
        } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2429
            lp->media = BNC_AUI;
2430
        } else if (lp->autosense == EXT_SIA) {
2431
            lp->media = EXT_SIA;
2432
        } else {
2433
            lp->media = NC;
2434
        }
2435
        lp->local_state = 0;
2436
        next_tick = dc21040_autoconf(dev);
2437
        break;
2438
 
2439
    case TP:
2440
        next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2441
                                                         TP_SUSPECT, test_tp);
2442
        break;
2443
 
2444
    case TP_SUSPECT:
2445
        next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2446
        break;
2447
 
2448
    case BNC:
2449
    case AUI:
2450
    case BNC_AUI:
2451
        next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2452
                                                  BNC_AUI_SUSPECT, ping_media);
2453
        break;
2454
 
2455
    case BNC_AUI_SUSPECT:
2456
        next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2457
        break;
2458
 
2459
    case EXT_SIA:
2460
        next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2461
                                              NC, EXT_SIA_SUSPECT, ping_media);
2462
        break;
2463
 
2464
    case EXT_SIA_SUSPECT:
2465
        next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2466
        break;
2467
 
2468
    case NC:
2469
        /* default to TP for all */
2470
        reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2471
        if (lp->media != lp->c_media) {
2472
            de4x5_dbg_media(dev);
2473
            lp->c_media = lp->media;
2474
        }
2475
        lp->media = INIT;
2476
        lp->tx_enable = NO;
2477
        break;
2478
    }
2479
 
2480
    return next_tick;
2481
}
2482
 
2483
static int
2484
dc21040_state(struct device *dev, int csr13, int csr14, int csr15, int timeout,
2485
              int next_state, int suspect_state,
2486
              int (*fn)(struct device *, int))
2487
{
2488
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2489
    int next_tick = DE4X5_AUTOSENSE_MS;
2490
    int linkBad;
2491
 
2492
    switch (lp->local_state) {
2493
    case 0:
2494
        reset_init_sia(dev, csr13, csr14, csr15);
2495
        lp->local_state++;
2496
        next_tick = 500;
2497
        break;
2498
 
2499
    case 1:
2500
        if (!lp->tx_enable) {
2501
            linkBad = fn(dev, timeout);
2502
            if (linkBad < 0) {
2503
                next_tick = linkBad & ~TIMER_CB;
2504
            } else {
2505
                if (linkBad && (lp->autosense == AUTO)) {
2506
                    lp->local_state = 0;
2507
                    lp->media = next_state;
2508
                } else {
2509
                    de4x5_init_connection(dev);
2510
                }
2511
            }
2512
        } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2513
            lp->media = suspect_state;
2514
            next_tick = 3000;
2515
        }
2516
        break;
2517
    }
2518
 
2519
    return next_tick;
2520
}
2521
 
2522
static int
2523
de4x5_suspect_state(struct device *dev, int timeout, int prev_state,
2524
                      int (*fn)(struct device *, int),
2525
                      int (*asfn)(struct device *))
2526
{
2527
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2528
    int next_tick = DE4X5_AUTOSENSE_MS;
2529
    int linkBad;
2530
 
2531
    switch (lp->local_state) {
2532
    case 1:
2533
        if (lp->linkOK) {
2534
            lp->media = prev_state;
2535
        } else {
2536
            lp->local_state++;
2537
            next_tick = asfn(dev);
2538
        }
2539
        break;
2540
 
2541
    case 2:
2542
        linkBad = fn(dev, timeout);
2543
        if (linkBad < 0) {
2544
            next_tick = linkBad & ~TIMER_CB;
2545
        } else if (!linkBad) {
2546
            lp->local_state--;
2547
            lp->media = prev_state;
2548
        } else {
2549
            lp->media = INIT;
2550
            lp->tcount++;
2551
        }
2552
    }
2553
 
2554
    return next_tick;
2555
}
2556
 
2557
/*
2558
** Autoconfigure the media when using the DC21041. AUI needs to be tested
2559
** before BNC, because the BNC port will indicate activity if it's not
2560
** terminated correctly. The only way to test for that is to place a loopback
2561
** packet onto the network and watch for errors. Since we're messing with
2562
** the interrupt mask register, disable the board interrupts and do not allow
2563
** any more packets to be queued to the hardware. Re-enable everything only
2564
** when the media is found.
2565
*/
2566
static int
2567
dc21041_autoconf(struct device *dev)
2568
{
2569
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2570
    u_long iobase = dev->base_addr;
2571
    s32 sts, irqs, irq_mask, imr, omr;
2572
    int next_tick = DE4X5_AUTOSENSE_MS;
2573
 
2574
    switch (lp->media) {
2575
    case INIT:
2576
        DISABLE_IRQs;
2577
        lp->tx_enable = NO;
2578
        lp->timeout = -1;
2579
        de4x5_save_skbs(dev);          /* Save non transmitted skb's */
2580
        if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2581
            lp->media = TP;            /* On chip auto negotiation is broken */
2582
        } else if (lp->autosense == TP) {
2583
            lp->media = TP;
2584
        } else if (lp->autosense == BNC) {
2585
            lp->media = BNC;
2586
        } else if (lp->autosense == AUI) {
2587
            lp->media = AUI;
2588
        } else {
2589
            lp->media = NC;
2590
        }
2591
        lp->local_state = 0;
2592
        next_tick = dc21041_autoconf(dev);
2593
        break;
2594
 
2595
    case TP_NW:
2596
        if (lp->timeout < 0) {
2597
            omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2598
            outl(omr | OMR_FDX, DE4X5_OMR);
2599
        }
2600
        irqs = STS_LNF | STS_LNP;
2601
        irq_mask = IMR_LFM | IMR_LPM;
2602
        sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2603
        if (sts < 0) {
2604
            next_tick = sts & ~TIMER_CB;
2605
        } else {
2606
            if (sts & STS_LNP) {
2607
                lp->media = ANS;
2608
            } else {
2609
                lp->media = AUI;
2610
            }
2611
            next_tick = dc21041_autoconf(dev);
2612
        }
2613
        break;
2614
 
2615
    case ANS:
2616
        if (!lp->tx_enable) {
2617
            irqs = STS_LNP;
2618
            irq_mask = IMR_LPM;
2619
            sts = test_ans(dev, irqs, irq_mask, 3000);
2620
            if (sts < 0) {
2621
                next_tick = sts & ~TIMER_CB;
2622
            } else {
2623
                if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2624
                    lp->media = TP;
2625
                    next_tick = dc21041_autoconf(dev);
2626
                } else {
2627
                    lp->local_state = 1;
2628
                    de4x5_init_connection(dev);
2629
                }
2630
            }
2631
        } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2632
            lp->media = ANS_SUSPECT;
2633
            next_tick = 3000;
2634
        }
2635
        break;
2636
 
2637
    case ANS_SUSPECT:
2638
        next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2639
        break;
2640
 
2641
    case TP:
2642
        if (!lp->tx_enable) {
2643
            if (lp->timeout < 0) {
2644
                omr = inl(DE4X5_OMR);          /* Set up half duplex for TP */
2645
                outl(omr & ~OMR_FDX, DE4X5_OMR);
2646
            }
2647
            irqs = STS_LNF | STS_LNP;
2648
            irq_mask = IMR_LFM | IMR_LPM;
2649
            sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2650
            if (sts < 0) {
2651
                next_tick = sts & ~TIMER_CB;
2652
            } else {
2653
                if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2654
                    if (inl(DE4X5_SISR) & SISR_NRA) {
2655
                        lp->media = AUI;       /* Non selected port activity */
2656
                    } else {
2657
                        lp->media = BNC;
2658
                    }
2659
                    next_tick = dc21041_autoconf(dev);
2660
                } else {
2661
                    lp->local_state = 1;
2662
                    de4x5_init_connection(dev);
2663
                }
2664
            }
2665
        } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2666
            lp->media = TP_SUSPECT;
2667
            next_tick = 3000;
2668
        }
2669
        break;
2670
 
2671
    case TP_SUSPECT:
2672
        next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2673
        break;
2674
 
2675
    case AUI:
2676
        if (!lp->tx_enable) {
2677
            if (lp->timeout < 0) {
2678
                omr = inl(DE4X5_OMR);          /* Set up half duplex for AUI */
2679
                outl(omr & ~OMR_FDX, DE4X5_OMR);
2680
            }
2681
            irqs = 0;
2682
            irq_mask = 0;
2683
            sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2684
            if (sts < 0) {
2685
                next_tick = sts & ~TIMER_CB;
2686
            } else {
2687
                if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2688
                    lp->media = BNC;
2689
                    next_tick = dc21041_autoconf(dev);
2690
                } else {
2691
                    lp->local_state = 1;
2692
                    de4x5_init_connection(dev);
2693
                }
2694
            }
2695
        } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2696
            lp->media = AUI_SUSPECT;
2697
            next_tick = 3000;
2698
        }
2699
        break;
2700
 
2701
    case AUI_SUSPECT:
2702
        next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2703
        break;
2704
 
2705
    case BNC:
2706
        switch (lp->local_state) {
2707
        case 0:
2708
            if (lp->timeout < 0) {
2709
                omr = inl(DE4X5_OMR);          /* Set up half duplex for BNC */
2710
                outl(omr & ~OMR_FDX, DE4X5_OMR);
2711
            }
2712
            irqs = 0;
2713
            irq_mask = 0;
2714
            sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2715
            if (sts < 0) {
2716
                next_tick = sts & ~TIMER_CB;
2717
            } else {
2718
                lp->local_state++;             /* Ensure media connected */
2719
                next_tick = dc21041_autoconf(dev);
2720
            }
2721
            break;
2722
 
2723
        case 1:
2724
            if (!lp->tx_enable) {
2725
                if ((sts = ping_media(dev, 3000)) < 0) {
2726
                    next_tick = sts & ~TIMER_CB;
2727
                } else {
2728
                    if (sts) {
2729
                        lp->local_state = 0;
2730
                        lp->media = NC;
2731
                    } else {
2732
                        de4x5_init_connection(dev);
2733
                    }
2734
                }
2735
            } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2736
                lp->media = BNC_SUSPECT;
2737
                next_tick = 3000;
2738
            }
2739
            break;
2740
        }
2741
        break;
2742
 
2743
    case BNC_SUSPECT:
2744
        next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2745
        break;
2746
 
2747
    case NC:
2748
        omr = inl(DE4X5_OMR);    /* Set up full duplex for the autonegotiate */
2749
        outl(omr | OMR_FDX, DE4X5_OMR);
2750
        reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2751
        if (lp->media != lp->c_media) {
2752
            de4x5_dbg_media(dev);
2753
            lp->c_media = lp->media;
2754
        }
2755
        lp->media = INIT;
2756
        lp->tx_enable = NO;
2757
        break;
2758
    }
2759
 
2760
    return next_tick;
2761
}
2762
 
2763
/*
2764
** Some autonegotiation chips are broken in that they do not return the
2765
** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2766
** register, except at the first power up negotiation.
2767
*/
2768
static int
2769
dc21140m_autoconf(struct device *dev)
2770
{
2771
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2772
    int ana, anlpa, cap, cr, slnk, sr;
2773
    int next_tick = DE4X5_AUTOSENSE_MS;
2774
    u_long imr, omr, iobase = dev->base_addr;
2775
 
2776
    switch(lp->media) {
2777
    case INIT:
2778
        if (lp->timeout < 0) {
2779
            DISABLE_IRQs;
2780
            lp->tx_enable = FALSE;
2781
            lp->linkOK = 0;
2782
            de4x5_save_skbs(dev);          /* Save non transmitted skb's */
2783
        }
2784
        if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2785
            next_tick &= ~TIMER_CB;
2786
        } else {
2787
            if (lp->useSROM) {
2788
                if (srom_map_media(dev) < 0) {
2789
                    lp->tcount++;
2790
                    return next_tick;
2791
                }
2792
                srom_exec(dev, lp->phy[lp->active].gep);
2793
                if (lp->infoblock_media == ANS) {
2794
                    ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2795
                    mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2796
                }
2797
            } else {
2798
                lp->tmp = MII_SR_ASSC;     /* Fake out the MII speed set */
2799
                SET_10Mb;
2800
                if (lp->autosense == _100Mb) {
2801
                    lp->media = _100Mb;
2802
                } else if (lp->autosense == _10Mb) {
2803
                    lp->media = _10Mb;
2804
                } else if ((lp->autosense == AUTO) &&
2805
                                    ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2806
                    ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2807
                    ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2808
                    mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2809
                    lp->media = ANS;
2810
                } else if (lp->autosense == AUTO) {
2811
                    lp->media = SPD_DET;
2812
                } else if (is_spd_100(dev) && is_100_up(dev)) {
2813
                    lp->media = _100Mb;
2814
                } else {
2815
                    lp->media = NC;
2816
                }
2817
            }
2818
            lp->local_state = 0;
2819
            next_tick = dc21140m_autoconf(dev);
2820
        }
2821
        break;
2822
 
2823
    case ANS:
2824
        switch (lp->local_state) {
2825
        case 0:
2826
            if (lp->timeout < 0) {
2827
                mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2828
            }
2829
            cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
2830
            if (cr < 0) {
2831
                next_tick = cr & ~TIMER_CB;
2832
            } else {
2833
                if (cr) {
2834
                    lp->local_state = 0;
2835
                    lp->media = SPD_DET;
2836
                } else {
2837
                    lp->local_state++;
2838
                }
2839
                next_tick = dc21140m_autoconf(dev);
2840
            }
2841
            break;
2842
 
2843
        case 1:
2844
            if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
2845
                next_tick = sr & ~TIMER_CB;
2846
            } else {
2847
                lp->media = SPD_DET;
2848
                lp->local_state = 0;
2849
                if (sr) {                         /* Success! */
2850
                    lp->tmp = MII_SR_ASSC;
2851
                    anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2852
                    ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2853
                    if (!(anlpa & MII_ANLPA_RF) &&
2854
                         (cap = anlpa & MII_ANLPA_TAF & ana)) {
2855
                        if (cap & MII_ANA_100M) {
2856
                            lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
2857
                            lp->media = _100Mb;
2858
                        } else if (cap & MII_ANA_10M) {
2859
                            lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
2860
 
2861
                            lp->media = _10Mb;
2862
                        }
2863
                    }
2864
                }                       /* Auto Negotiation failed to finish */
2865
                next_tick = dc21140m_autoconf(dev);
2866
            }                           /* Auto Negotiation failed to start */
2867
            break;
2868
        }
2869
        break;
2870
 
2871
    case SPD_DET:                              /* Choose 10Mb/s or 100Mb/s */
2872
        if (lp->timeout < 0) {
2873
            lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2874
                                                  (~gep_rd(dev) & GEP_LNP));
2875
            SET_100Mb_PDET;
2876
        }
2877
        if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2878
            next_tick = slnk & ~TIMER_CB;
2879
        } else {
2880
            if (is_spd_100(dev) && is_100_up(dev)) {
2881
                lp->media = _100Mb;
2882
            } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2883
                lp->media = _10Mb;
2884
            } else {
2885
                lp->media = NC;
2886
            }
2887
            next_tick = dc21140m_autoconf(dev);
2888
        }
2889
        break;
2890
 
2891
    case _100Mb:                               /* Set 100Mb/s */
2892
        next_tick = 3000;
2893
        if (!lp->tx_enable) {
2894
            SET_100Mb;
2895
            de4x5_init_connection(dev);
2896
        } else {
2897
            if (!lp->linkOK && (lp->autosense == AUTO)) {
2898
                if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2899
                    lp->media = INIT;
2900
                    lp->tcount++;
2901
                    next_tick = DE4X5_AUTOSENSE_MS;
2902
                }
2903
            }
2904
        }
2905
        break;
2906
 
2907
    case BNC:
2908
    case AUI:
2909
    case _10Mb:                                /* Set 10Mb/s */
2910
        next_tick = 3000;
2911
        if (!lp->tx_enable) {
2912
            SET_10Mb;
2913
            de4x5_init_connection(dev);
2914
        } else {
2915
            if (!lp->linkOK && (lp->autosense == AUTO)) {
2916
                if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2917
                    lp->media = INIT;
2918
                    lp->tcount++;
2919
                    next_tick = DE4X5_AUTOSENSE_MS;
2920
                }
2921
            }
2922
        }
2923
        break;
2924
 
2925
    case NC:
2926
        if (lp->media != lp->c_media) {
2927
            de4x5_dbg_media(dev);
2928
            lp->c_media = lp->media;
2929
        }
2930
        lp->media = INIT;
2931
        lp->tx_enable = FALSE;
2932
        break;
2933
    }
2934
 
2935
    return next_tick;
2936
}
2937
 
2938
/*
2939
** This routine may be merged into dc21140m_autoconf() sometime as I'm
2940
** changing how I figure out the media - but trying to keep it backwards
2941
** compatible with the de500-xa and de500-aa.
2942
** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2943
** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2944
** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2945
** active.
2946
** When autonegotiation is working, the ANS part searches the SROM for
2947
** the highest common speed (TP) link that both can run and if that can
2948
** be full duplex. That infoblock is executed and then the link speed set.
2949
**
2950
** Only _10Mb and _100Mb are tested here.
2951
*/
2952
static int
2953
dc2114x_autoconf(struct device *dev)
2954
{
2955
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2956
    u_long iobase = dev->base_addr;
2957
    s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2958
    int next_tick = DE4X5_AUTOSENSE_MS;
2959
 
2960
    switch (lp->media) {
2961
    case INIT:
2962
        if (lp->timeout < 0) {
2963
            DISABLE_IRQs;
2964
            lp->tx_enable = FALSE;
2965
            lp->linkOK = 0;
2966
            lp->timeout = -1;
2967
            de4x5_save_skbs(dev);            /* Save non transmitted skb's */
2968
            if (lp->params.autosense & ~AUTO) {
2969
                srom_map_media(dev);         /* Fixed media requested      */
2970
                if (lp->media != lp->params.autosense) {
2971
                    lp->tcount++;
2972
                    lp->media = INIT;
2973
                    return next_tick;
2974
                }
2975
                lp->media = INIT;
2976
            }
2977
        }
2978
        if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2979
            next_tick &= ~TIMER_CB;
2980
        } else {
2981
            if (lp->autosense == _100Mb) {
2982
                lp->media = _100Mb;
2983
            } else if (lp->autosense == _10Mb) {
2984
                lp->media = _10Mb;
2985
            } else if (lp->autosense == TP) {
2986
                lp->media = TP;
2987
            } else if (lp->autosense == BNC) {
2988
                lp->media = BNC;
2989
            } else if (lp->autosense == AUI) {
2990
                lp->media = AUI;
2991
            } else {
2992
                lp->media = SPD_DET;
2993
                if ((lp->infoblock_media == ANS) &&
2994
                                    ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2995
                    ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2996
                    ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2997
                    mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2998
                    lp->media = ANS;
2999
                }
3000
            }
3001
            lp->local_state = 0;
3002
            next_tick = dc2114x_autoconf(dev);
3003
        }
3004
        break;
3005
 
3006
    case ANS:
3007
        switch (lp->local_state) {
3008
        case 0:
3009
            if (lp->timeout < 0) {
3010
                mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3011
            }
3012
            cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
3013
            if (cr < 0) {
3014
                next_tick = cr & ~TIMER_CB;
3015
            } else {
3016
                if (cr) {
3017
                    lp->local_state = 0;
3018
                    lp->media = SPD_DET;
3019
                } else {
3020
                    lp->local_state++;
3021
                }
3022
                next_tick = dc2114x_autoconf(dev);
3023
            }
3024
            break;
3025
 
3026
        case 1:
3027
            if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
3028
                next_tick = sr & ~TIMER_CB;
3029
            } else {
3030
                lp->media = SPD_DET;
3031
                lp->local_state = 0;
3032
                if (sr) {                         /* Success! */
3033
                    lp->tmp = MII_SR_ASSC;
3034
                    anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3035
                    ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3036
                    if (!(anlpa & MII_ANLPA_RF) &&
3037
                         (cap = anlpa & MII_ANLPA_TAF & ana)) {
3038
                        if (cap & MII_ANA_100M) {
3039
                            lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
3040
                            lp->media = _100Mb;
3041
                        } else if (cap & MII_ANA_10M) {
3042
                            lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
3043
                            lp->media = _10Mb;
3044
                        }
3045
                    }
3046
                }                       /* Auto Negotiation failed to finish */
3047
                next_tick = dc2114x_autoconf(dev);
3048
            }                           /* Auto Negotiation failed to start  */
3049
            break;
3050
        }
3051
        break;
3052
 
3053
    case AUI:
3054
        if (!lp->tx_enable) {
3055
            if (lp->timeout < 0) {
3056
                omr = inl(DE4X5_OMR);   /* Set up half duplex for AUI        */
3057
                outl(omr & ~OMR_FDX, DE4X5_OMR);
3058
            }
3059
            irqs = 0;
3060
            irq_mask = 0;
3061
            sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3062
            if (sts < 0) {
3063
                next_tick = sts & ~TIMER_CB;
3064
            } else {
3065
                if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3066
                    lp->media = BNC;
3067
                    next_tick = dc2114x_autoconf(dev);
3068
                } else {
3069
                    lp->local_state = 1;
3070
                    de4x5_init_connection(dev);
3071
                }
3072
            }
3073
        } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3074
            lp->media = AUI_SUSPECT;
3075
            next_tick = 3000;
3076
        }
3077
        break;
3078
 
3079
    case AUI_SUSPECT:
3080
        next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3081
        break;
3082
 
3083
    case BNC:
3084
        switch (lp->local_state) {
3085
        case 0:
3086
            if (lp->timeout < 0) {
3087
                omr = inl(DE4X5_OMR);   /* Set up half duplex for BNC        */
3088
                outl(omr & ~OMR_FDX, DE4X5_OMR);
3089
            }
3090
            irqs = 0;
3091
            irq_mask = 0;
3092
            sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3093
            if (sts < 0) {
3094
                next_tick = sts & ~TIMER_CB;
3095
            } else {
3096
                lp->local_state++;      /* Ensure media connected            */
3097
                next_tick = dc2114x_autoconf(dev);
3098
            }
3099
            break;
3100
 
3101
        case 1:
3102
            if (!lp->tx_enable) {
3103
                if ((sts = ping_media(dev, 3000)) < 0) {
3104
                    next_tick = sts & ~TIMER_CB;
3105
                } else {
3106
                    if (sts) {
3107
                        lp->local_state = 0;
3108
                        lp->tcount++;
3109
                        lp->media = INIT;
3110
                    } else {
3111
                        de4x5_init_connection(dev);
3112
                    }
3113
                }
3114
            } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3115
                lp->media = BNC_SUSPECT;
3116
                next_tick = 3000;
3117
            }
3118
            break;
3119
        }
3120
        break;
3121
 
3122
    case BNC_SUSPECT:
3123
        next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3124
        break;
3125
 
3126
    case SPD_DET:                       /* Choose 10Mb/s or 100Mb/s          */
3127
          if (srom_map_media(dev) < 0) {
3128
              lp->tcount++;
3129
              lp->media = INIT;
3130
              return next_tick;
3131
          }
3132
          if (lp->media == _100Mb) {
3133
              if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3134
                  lp->media = SPD_DET;
3135
                  return  (slnk & ~TIMER_CB);
3136
              }
3137
          } else {
3138
              if (wait_for_link(dev) < 0) {
3139
                  lp->media = SPD_DET;
3140
                  return PDET_LINK_WAIT;
3141
              }
3142
          }
3143
          if (lp->media == ANS) {           /* Do MII parallel detection */
3144
              if (is_spd_100(dev)) {
3145
                  lp->media = _100Mb;
3146
              } else {
3147
                  lp->media = _10Mb;
3148
              }
3149
              next_tick = dc2114x_autoconf(dev);
3150
          } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3151
                     (((lp->media == _10Mb) || (lp->media == TP) ||
3152
                       (lp->media == BNC)   || (lp->media == AUI)) &&
3153
                      is_10_up(dev))) {
3154
              next_tick = dc2114x_autoconf(dev);
3155
          } else {
3156
              lp->tcount++;
3157
              lp->media = INIT;
3158
          }
3159
          break;
3160
 
3161
    case _10Mb:
3162
        next_tick = 3000;
3163
        if (!lp->tx_enable) {
3164
            SET_10Mb;
3165
            de4x5_init_connection(dev);
3166
        } else {
3167
            if (!lp->linkOK && (lp->autosense == AUTO)) {
3168
                if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3169
                    lp->media = INIT;
3170
                    lp->tcount++;
3171
                    next_tick = DE4X5_AUTOSENSE_MS;
3172
                }
3173
            }
3174
        }
3175
        break;
3176
 
3177
    case _100Mb:
3178
        next_tick = 3000;
3179
        if (!lp->tx_enable) {
3180
            SET_100Mb;
3181
            de4x5_init_connection(dev);
3182
        } else {
3183
            if (!lp->linkOK && (lp->autosense == AUTO)) {
3184
                if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3185
                    lp->media = INIT;
3186
                    lp->tcount++;
3187
                    next_tick = DE4X5_AUTOSENSE_MS;
3188
                }
3189
            }
3190
        }
3191
        break;
3192
 
3193
    default:
3194
        lp->tcount++;
3195
printk("Huh?: media:%02x\n", lp->media);
3196
        lp->media = INIT;
3197
        break;
3198
    }
3199
 
3200
    return next_tick;
3201
}
3202
 
3203
static int
3204
srom_autoconf(struct device *dev)
3205
{
3206
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3207
 
3208
    return lp->infoleaf_fn(dev);
3209
}
3210
 
3211
/*
3212
** This mapping keeps the original media codes and FDX flag unchanged.
3213
** While it isn't strictly necessary, it helps me for the moment...
3214
** The early return avoids a media state / SROM media space clash.
3215
*/
3216
static int
3217
srom_map_media(struct device *dev)
3218
{
3219
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3220
 
3221
    lp->fdx = 0;
3222
    if (lp->infoblock_media == lp->media)
3223
      return 0;
3224
 
3225
    switch(lp->infoblock_media) {
3226
      case SROM_10BASETF:
3227
        if (!lp->params.fdx) return -1;
3228
        lp->fdx = TRUE;
3229
      case SROM_10BASET:
3230
        if (lp->params.fdx && !lp->fdx) return -1;
3231
        if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3232
            lp->media = _10Mb;
3233
        } else {
3234
            lp->media = TP;
3235
        }
3236
        break;
3237
 
3238
      case SROM_10BASE2:
3239
        lp->media = BNC;
3240
        break;
3241
 
3242
      case SROM_10BASE5:
3243
        lp->media = AUI;
3244
        break;
3245
 
3246
      case SROM_100BASETF:
3247
        if (!lp->params.fdx) return -1;
3248
        lp->fdx = TRUE;
3249
      case SROM_100BASET:
3250
        if (lp->params.fdx && !lp->fdx) return -1;
3251
        lp->media = _100Mb;
3252
        break;
3253
 
3254
      case SROM_100BASET4:
3255
        lp->media = _100Mb;
3256
        break;
3257
 
3258
      case SROM_100BASEFF:
3259
        if (!lp->params.fdx) return -1;
3260
        lp->fdx = TRUE;
3261
      case SROM_100BASEF:
3262
        if (lp->params.fdx && !lp->fdx) return -1;
3263
        lp->media = _100Mb;
3264
        break;
3265
 
3266
      case ANS:
3267
        lp->media = ANS;
3268
        break;
3269
 
3270
      default:
3271
        printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3272
                                                          lp->infoblock_media);
3273
        return -1;
3274
        break;
3275
    }
3276
 
3277
    return 0;
3278
}
3279
 
3280
static void
3281
de4x5_init_connection(struct device *dev)
3282
{
3283
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3284
    u_long iobase = dev->base_addr;
3285
 
3286
    if (lp->media != lp->c_media) {
3287
        de4x5_dbg_media(dev);
3288
        lp->c_media = lp->media;          /* Stop scrolling media messages */
3289
    }
3290
 
3291
    cli();
3292
    de4x5_rst_desc_ring(dev);
3293
    de4x5_setup_intr(dev);
3294
    lp->tx_enable = YES;
3295
    dev->tbusy = 0;
3296
    sti();
3297
    outl(POLL_DEMAND, DE4X5_TPD);
3298
    mark_bh(NET_BH);
3299
 
3300
    return;
3301
}
3302
 
3303
/*
3304
** General PHY reset function. Some MII devices don't reset correctly
3305
** since their MII address pins can float at voltages that are dependent
3306
** on the signal pin use. Do a double reset to ensure a reset.
3307
*/
3308
static int
3309
de4x5_reset_phy(struct device *dev)
3310
{
3311
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3312
    u_long iobase = dev->base_addr;
3313
    int next_tick = 0;
3314
 
3315
    if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3316
        if (lp->timeout < 0) {
3317
            if (lp->useSROM) {
3318
                if (lp->phy[lp->active].rst) {
3319
                    srom_exec(dev, lp->phy[lp->active].rst);
3320
                    srom_exec(dev, lp->phy[lp->active].rst);
3321
                } else if (lp->rst) {          /* Type 5 infoblock reset */
3322
                    srom_exec(dev, lp->rst);
3323
                    srom_exec(dev, lp->rst);
3324
                }
3325
            } else {
3326
                PHY_HARD_RESET;
3327
            }
3328
            if (lp->useMII) {
3329
                mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3330
            }
3331
        }
3332
        if (lp->useMII) {
3333
            next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, FALSE, 500);
3334
        }
3335
    } else if (lp->chipset == DC21140) {
3336
        PHY_HARD_RESET;
3337
    }
3338
 
3339
    return next_tick;
3340
}
3341
 
3342
static int
3343
test_media(struct device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3344
{
3345
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3346
    u_long iobase = dev->base_addr;
3347
    s32 sts, csr12;
3348
 
3349
    if (lp->timeout < 0) {
3350
        lp->timeout = msec/100;
3351
        if (!lp->useSROM) {      /* Already done if by SROM, else dc2104[01] */
3352
            reset_init_sia(dev, csr13, csr14, csr15);
3353
        }
3354
 
3355
        /* set up the interrupt mask */
3356
        outl(irq_mask, DE4X5_IMR);
3357
 
3358
        /* clear all pending interrupts */
3359
        sts = inl(DE4X5_STS);
3360
        outl(sts, DE4X5_STS);
3361
 
3362
        /* clear csr12 NRA and SRA bits */
3363
        if ((lp->chipset == DC21041) || lp->useSROM) {
3364
            csr12 = inl(DE4X5_SISR);
3365
            outl(csr12, DE4X5_SISR);
3366
        }
3367
    }
3368
 
3369
    sts = inl(DE4X5_STS) & ~TIMER_CB;
3370
 
3371
    if (!(sts & irqs) && --lp->timeout) {
3372
        sts = 100 | TIMER_CB;
3373
    } else {
3374
        lp->timeout = -1;
3375
    }
3376
 
3377
    return sts;
3378
}
3379
 
3380
static int
3381
test_tp(struct device *dev, s32 msec)
3382
{
3383
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3384
    u_long iobase = dev->base_addr;
3385
    int sisr;
3386
 
3387
    if (lp->timeout < 0) {
3388
        lp->timeout = msec/100;
3389
    }
3390
 
3391
    sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3392
 
3393
    if (sisr && --lp->timeout) {
3394
        sisr = 100 | TIMER_CB;
3395
    } else {
3396
        lp->timeout = -1;
3397
    }
3398
 
3399
    return sisr;
3400
}
3401
 
3402
/*
3403
** Samples the 100Mb Link State Signal. The sample interval is important
3404
** because too fast a rate can give erroneous results and confuse the
3405
** speed sense algorithm.
3406
*/
3407
#define SAMPLE_INTERVAL 500  /* ms */
3408
#define SAMPLE_DELAY    2000 /* ms */
3409
static int
3410
test_for_100Mb(struct device *dev, int msec)
3411
{
3412
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3413
    int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3414
 
3415
    if (lp->timeout < 0) {
3416
        if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3417
        if (msec > SAMPLE_DELAY) {
3418
            lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3419
            gep = SAMPLE_DELAY | TIMER_CB;
3420
            return gep;
3421
        } else {
3422
            lp->timeout = msec/SAMPLE_INTERVAL;
3423
        }
3424
    }
3425
 
3426
    if (lp->phy[lp->active].id || lp->useSROM) {
3427
        gep = is_100_up(dev) | is_spd_100(dev);
3428
    } else {
3429
        gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3430
    }
3431
    if (!(gep & ret) && --lp->timeout) {
3432
        gep = SAMPLE_INTERVAL | TIMER_CB;
3433
    } else {
3434
        lp->timeout = -1;
3435
    }
3436
 
3437
    return gep;
3438
}
3439
 
3440
static int
3441
wait_for_link(struct device *dev)
3442
{
3443
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3444
 
3445
    if (lp->timeout < 0) {
3446
        lp->timeout = 1;
3447
    }
3448
 
3449
    if (lp->timeout--) {
3450
        return TIMER_CB;
3451
    } else {
3452
        lp->timeout = -1;
3453
    }
3454
 
3455
    return 0;
3456
}
3457
 
3458
/*
3459
**
3460
**
3461
*/
3462
static int
3463
test_mii_reg(struct device *dev, int reg, int mask, int pol, long msec)
3464
{
3465
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3466
    int test;
3467
    u_long iobase = dev->base_addr;
3468
 
3469
    if (lp->timeout < 0) {
3470
        lp->timeout = msec/100;
3471
    }
3472
 
3473
    if (pol) pol = ~0;
3474
    reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3475
    test = (reg ^ pol) & mask;
3476
 
3477
    if (test && --lp->timeout) {
3478
        reg = 100 | TIMER_CB;
3479
    } else {
3480
        lp->timeout = -1;
3481
    }
3482
 
3483
    return reg;
3484
}
3485
 
3486
static int
3487
is_spd_100(struct device *dev)
3488
{
3489
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3490
    u_long iobase = dev->base_addr;
3491
    int spd;
3492
 
3493
    if (lp->useMII) {
3494
        spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3495
        spd = ~(spd ^ lp->phy[lp->active].spd.value);
3496
        spd &= lp->phy[lp->active].spd.mask;
3497
    } else if (!lp->useSROM) {                      /* de500-xa */
3498
        spd = ((~gep_rd(dev)) & GEP_SLNK);
3499
    } else {
3500
        if ((lp->ibn == 2) || !lp->asBitValid)
3501
            return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3502
 
3503
        spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3504
                  (lp->linkOK & ~lp->asBitValid);
3505
    }
3506
 
3507
    return spd;
3508
}
3509
 
3510
static int
3511
is_100_up(struct device *dev)
3512
{
3513
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3514
    u_long iobase = dev->base_addr;
3515
 
3516
    if (lp->useMII) {
3517
        /* Double read for sticky bits & temporary drops */
3518
        mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3519
        return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3520
    } else if (!lp->useSROM) {                       /* de500-xa */
3521
        return ((~gep_rd(dev)) & GEP_SLNK);
3522
    } else {
3523
        if ((lp->ibn == 2) || !lp->asBitValid)
3524
            return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3525
 
3526
        return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3527
                (lp->linkOK & ~lp->asBitValid));
3528
    }
3529
}
3530
 
3531
static int
3532
is_10_up(struct device *dev)
3533
{
3534
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3535
    u_long iobase = dev->base_addr;
3536
 
3537
    if (lp->useMII) {
3538
        /* Double read for sticky bits & temporary drops */
3539
        mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3540
        return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3541
    } else if (!lp->useSROM) {                       /* de500-xa */
3542
        return ((~gep_rd(dev)) & GEP_LNP);
3543
    } else {
3544
        if ((lp->ibn == 2) || !lp->asBitValid)
3545
            return (((lp->chipset & ~0x00ff) == DC2114x) ?
3546
                    (~inl(DE4X5_SISR)&SISR_LS10):
3547
                    0);
3548
 
3549
        return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3550
                (lp->linkOK & ~lp->asBitValid));
3551
    }
3552
}
3553
 
3554
static int
3555
is_anc_capable(struct device *dev)
3556
{
3557
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3558
    u_long iobase = dev->base_addr;
3559
 
3560
    if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3561
        return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3562
    } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3563
        return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3564
    } else {
3565
        return 0;
3566
    }
3567
}
3568
 
3569
/*
3570
** Send a packet onto the media and watch for send errors that indicate the
3571
** media is bad or unconnected.
3572
*/
3573
static int
3574
ping_media(struct device *dev, int msec)
3575
{
3576
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3577
    u_long iobase = dev->base_addr;
3578
    int sisr;
3579
 
3580
    if (lp->timeout < 0) {
3581
        lp->timeout = msec/100;
3582
 
3583
        lp->tmp = lp->tx_new;                /* Remember the ring position */
3584
        load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), NULL);
3585
        lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3586
        outl(POLL_DEMAND, DE4X5_TPD);
3587
    }
3588
 
3589
    sisr = inl(DE4X5_SISR);
3590
 
3591
    if ((!(sisr & SISR_NCR)) &&
3592
        ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3593
         (--lp->timeout)) {
3594
        sisr = 100 | TIMER_CB;
3595
    } else {
3596
        if ((!(sisr & SISR_NCR)) &&
3597
            !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3598
            lp->timeout) {
3599
            sisr = 0;
3600
        } else {
3601
            sisr = 1;
3602
        }
3603
        lp->timeout = -1;
3604
    }
3605
 
3606
    return sisr;
3607
}
3608
 
3609
/*
3610
** This function does 2 things: on Intels it kmalloc's another buffer to
3611
** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3612
** into which the packet is copied.
3613
*/
3614
static struct sk_buff *
3615
de4x5_alloc_rx_buff(struct device *dev, int index, int len)
3616
{
3617
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3618
    struct sk_buff *p;
3619
 
3620
#if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
3621
    struct sk_buff *ret;
3622
    u_long i=0, tmp;
3623
 
3624
    p = dev_alloc_skb(IEEE802_3_SZ + ALIGN + 2);
3625
    if (!p) return NULL;
3626
 
3627
    p->dev = dev;
3628
    tmp = virt_to_bus(p->data);
3629
    i = ((tmp + ALIGN) & ~ALIGN) - tmp;
3630
    skb_reserve(p, i);
3631
    lp->rx_ring[index].buf = tmp + i;
3632
 
3633
    ret = lp->rx_skb[index];
3634
    lp->rx_skb[index] = p;
3635
 
3636
    if ((u_long) ret > 1) {
3637
        skb_put(ret, len);
3638
    }
3639
 
3640
    return ret;
3641
 
3642
#else
3643
    if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3644
 
3645
    p = dev_alloc_skb(len + 2);
3646
    if (!p) return NULL;
3647
 
3648
    p->dev = dev;
3649
    skb_reserve(p, 2);                                 /* Align */
3650
    if (index < lp->rx_old) {                          /* Wrapped buffer */
3651
        short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3652
        memcpy(skb_put(p,tlen),
3653
               bus_to_virt(le32_to_cpu(lp->rx_ring[lp->rx_old].buf)),tlen);
3654
        memcpy(skb_put(p,len-tlen),
3655
               bus_to_virt(le32_to_cpu(lp->rx_ring[0].buf)), len-tlen);
3656
    } else {                                           /* Linear buffer */
3657
        memcpy(skb_put(p,len),
3658
               bus_to_virt(le32_to_cpu(lp->rx_ring[lp->rx_old].buf)),len);
3659
    }
3660
 
3661
    return p;
3662
#endif
3663
}
3664
 
3665
static void
3666
de4x5_free_rx_buffs(struct device *dev)
3667
{
3668
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3669
    int i;
3670
 
3671
    for (i=0; i<lp->rxRingSize; i++) {
3672
        if ((u_long) lp->rx_skb[i] > 1) {
3673
            dev_kfree_skb(lp->rx_skb[i], FREE_WRITE);
3674
        }
3675
        lp->rx_ring[i].status = 0;
3676
        lp->rx_skb[i] = (struct sk_buff *)1;    /* Dummy entry */
3677
    }
3678
 
3679
    return;
3680
}
3681
 
3682
static void
3683
de4x5_free_tx_buffs(struct device *dev)
3684
{
3685
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3686
    int i;
3687
 
3688
    for (i=0; i<lp->txRingSize; i++) {
3689
        if (lp->tx_skb[i]) {
3690
            dev_kfree_skb(lp->tx_skb[i], FREE_WRITE);
3691
            lp->tx_skb[i] = NULL;
3692
        }
3693
        lp->tx_ring[i].status = 0;
3694
    }
3695
 
3696
    /* Unload the locally queued packets */
3697
    while (lp->cache.skb) {
3698
        dev_kfree_skb(de4x5_get_cache(dev), FREE_WRITE);
3699
    }
3700
 
3701
    return;
3702
}
3703
 
3704
/*
3705
** When a user pulls a connection, the DECchip can end up in a
3706
** 'running - waiting for end of transmission' state. This means that we
3707
** have to perform a chip soft reset to ensure that we can synchronize
3708
** the hardware and software and make any media probes using a loopback
3709
** packet meaningful.
3710
*/
3711
static void
3712
de4x5_save_skbs(struct device *dev)
3713
{
3714
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3715
    u_long iobase = dev->base_addr;
3716
    s32 omr;
3717
 
3718
    if (!lp->cache.save_cnt) {
3719
        STOP_DE4X5;
3720
        de4x5_tx(dev);                          /* Flush any sent skb's */
3721
        de4x5_free_tx_buffs(dev);
3722
        de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3723
        de4x5_sw_reset(dev);
3724
        de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3725
        lp->cache.save_cnt++;
3726
        START_DE4X5;
3727
    }
3728
 
3729
    return;
3730
}
3731
 
3732
static void
3733
de4x5_rst_desc_ring(struct device *dev)
3734
{
3735
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3736
    u_long iobase = dev->base_addr;
3737
    int i;
3738
    s32 omr;
3739
 
3740
    if (lp->cache.save_cnt) {
3741
        STOP_DE4X5;
3742
        outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
3743
        outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
3744
 
3745
        lp->rx_new = lp->rx_old = 0;
3746
        lp->tx_new = lp->tx_old = 0;
3747
 
3748
        for (i = 0; i < lp->rxRingSize; i++) {
3749
            lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3750
        }
3751
 
3752
        for (i = 0; i < lp->txRingSize; i++) {
3753
            lp->tx_ring[i].status = cpu_to_le32(0);
3754
        }
3755
 
3756
        barrier();
3757
        lp->cache.save_cnt--;
3758
        START_DE4X5;
3759
    }
3760
 
3761
    return;
3762
}
3763
 
3764
static void
3765
de4x5_cache_state(struct device *dev, int flag)
3766
{
3767
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3768
    u_long iobase = dev->base_addr;
3769
 
3770
    switch(flag) {
3771
      case DE4X5_SAVE_STATE:
3772
        lp->cache.csr0 = inl(DE4X5_BMR);
3773
        lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3774
        lp->cache.csr7 = inl(DE4X5_IMR);
3775
        break;
3776
 
3777
      case DE4X5_RESTORE_STATE:
3778
        outl(lp->cache.csr0, DE4X5_BMR);
3779
        outl(lp->cache.csr6, DE4X5_OMR);
3780
        outl(lp->cache.csr7, DE4X5_IMR);
3781
        if (lp->chipset == DC21140) {
3782
            gep_wr(lp->cache.gepc, dev);
3783
            gep_wr(lp->cache.gep, dev);
3784
        } else {
3785
            reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3786
                                                              lp->cache.csr15);
3787
        }
3788
        break;
3789
    }
3790
 
3791
    return;
3792
}
3793
 
3794
static void
3795
de4x5_put_cache(struct device *dev, struct sk_buff *skb)
3796
{
3797
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3798
    struct sk_buff *p;
3799
 
3800
    if (lp->cache.skb) {
3801
        for (p=lp->cache.skb; p->next; p=p->next);
3802
        p->next = skb;
3803
    } else {
3804
        lp->cache.skb = skb;
3805
    }
3806
    skb->next = NULL;
3807
 
3808
    return;
3809
}
3810
 
3811
static void
3812
de4x5_putb_cache(struct device *dev, struct sk_buff *skb)
3813
{
3814
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3815
    struct sk_buff *p = lp->cache.skb;
3816
 
3817
    lp->cache.skb = skb;
3818
    skb->next = p;
3819
 
3820
    return;
3821
}
3822
 
3823
static struct sk_buff *
3824
de4x5_get_cache(struct device *dev)
3825
{
3826
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3827
    struct sk_buff *p = lp->cache.skb;
3828
 
3829
    if (p) {
3830
        lp->cache.skb = p->next;
3831
        p->next = NULL;
3832
    }
3833
 
3834
    return p;
3835
}
3836
 
3837
/*
3838
** Check the Auto Negotiation State. Return OK when a link pass interrupt
3839
** is received and the auto-negotiation status is NWAY OK.
3840
*/
3841
static int
3842
test_ans(struct device *dev, s32 irqs, s32 irq_mask, s32 msec)
3843
{
3844
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3845
    u_long iobase = dev->base_addr;
3846
    s32 sts, ans;
3847
 
3848
    if (lp->timeout < 0) {
3849
        lp->timeout = msec/100;
3850
        outl(irq_mask, DE4X5_IMR);
3851
 
3852
        /* clear all pending interrupts */
3853
        sts = inl(DE4X5_STS);
3854
        outl(sts, DE4X5_STS);
3855
    }
3856
 
3857
    ans = inl(DE4X5_SISR) & SISR_ANS;
3858
    sts = inl(DE4X5_STS) & ~TIMER_CB;
3859
 
3860
    if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3861
        sts = 100 | TIMER_CB;
3862
    } else {
3863
        lp->timeout = -1;
3864
    }
3865
 
3866
    return sts;
3867
}
3868
 
3869
static void
3870
de4x5_setup_intr(struct device *dev)
3871
{
3872
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3873
    u_long iobase = dev->base_addr;
3874
    s32 imr, sts;
3875
 
3876
    if (inl(DE4X5_OMR) & OMR_SR) {   /* Only unmask if TX/RX is enabled */
3877
        imr = 0;
3878
        UNMASK_IRQs;
3879
        sts = inl(DE4X5_STS);        /* Reset any pending (stale) interrupts */
3880
        outl(sts, DE4X5_STS);
3881
        ENABLE_IRQs;
3882
    }
3883
 
3884
    return;
3885
}
3886
 
3887
/*
3888
**
3889
*/
3890
static void
3891
reset_init_sia(struct device *dev, s32 csr13, s32 csr14, s32 csr15)
3892
{
3893
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3894
    u_long iobase = dev->base_addr;
3895
 
3896
    RESET_SIA;
3897
    if (lp->useSROM) {
3898
        if (lp->ibn == 3) {
3899
            srom_exec(dev, lp->phy[lp->active].rst);
3900
            srom_exec(dev, lp->phy[lp->active].gep);
3901
            outl(1, DE4X5_SICR);
3902
            return;
3903
        } else {
3904
            csr15 = lp->cache.csr15;
3905
            csr14 = lp->cache.csr14;
3906
            csr13 = lp->cache.csr13;
3907
            outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3908
            outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3909
        }
3910
    } else {
3911
        outl(csr15, DE4X5_SIGR);
3912
    }
3913
    outl(csr14, DE4X5_STRR);
3914
    outl(csr13, DE4X5_SICR);
3915
 
3916
    de4x5_ms_delay(10);
3917
 
3918
    return;
3919
}
3920
 
3921
/*
3922
** Create a loopback ethernet packet
3923
*/
3924
static void
3925
create_packet(struct device *dev, char *frame, int len)
3926
{
3927
    int i;
3928
    char *buf = frame;
3929
 
3930
    for (i=0; i<ETH_ALEN; i++) {             /* Use this source address */
3931
        *buf++ = dev->dev_addr[i];
3932
    }
3933
    for (i=0; i<ETH_ALEN; i++) {             /* Use this destination address */
3934
        *buf++ = dev->dev_addr[i];
3935
    }
3936
 
3937
    *buf++ = 0;                              /* Packet length (2 bytes) */
3938
    *buf++ = 1;
3939
 
3940
    return;
3941
}
3942
 
3943
/*
3944
** Known delay in microseconds
3945
*/
3946
static void
3947
de4x5_us_delay(u32 usec)
3948
{
3949
    udelay(usec);
3950
 
3951
    return;
3952
}
3953
 
3954
/*
3955
** Known delay in milliseconds, in millisecond steps.
3956
*/
3957
static void
3958
de4x5_ms_delay(u32 msec)
3959
{
3960
    u_int i;
3961
 
3962
    for (i=0; i<msec; i++) {
3963
        de4x5_us_delay(1000);
3964
    }
3965
 
3966
    return;
3967
}
3968
 
3969
 
3970
/*
3971
** Look for a particular board name in the EISA configuration space
3972
*/
3973
static int
3974
EISA_signature(char *name, s32 eisa_id)
3975
{
3976
    static c_char *signatures[] = DE4X5_SIGNATURE;
3977
    char ManCode[DE4X5_STRLEN];
3978
    union {
3979
        s32 ID;
3980
        char Id[4];
3981
    } Eisa;
3982
    int i, status = 0, siglen = sizeof(signatures)/sizeof(c_char *);
3983
 
3984
    *name = '\0';
3985
    Eisa.ID = inl(eisa_id);
3986
 
3987
    ManCode[0]=(((Eisa.Id[0]>>2)&0x1f)+0x40);
3988
    ManCode[1]=(((Eisa.Id[1]&0xe0)>>5)+((Eisa.Id[0]&0x03)<<3)+0x40);
3989
    ManCode[2]=(((Eisa.Id[2]>>4)&0x0f)+0x30);
3990
    ManCode[3]=((Eisa.Id[2]&0x0f)+0x30);
3991
    ManCode[4]=(((Eisa.Id[3]>>4)&0x0f)+0x30);
3992
    ManCode[5]='\0';
3993
 
3994
    for (i=0;i<siglen;i++) {
3995
        if (strstr(ManCode, signatures[i]) != NULL) {
3996
            strcpy(name,ManCode);
3997
            status = 1;
3998
            break;
3999
        }
4000
    }
4001
 
4002
    return status;                         /* return the device name string */
4003
}
4004
 
4005
/*
4006
** Look for a particular board name in the PCI configuration space
4007
*/
4008
static int
4009
PCI_signature(char *name, struct bus_type *lp)
4010
{
4011
    static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
4012
    int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
4013
 
4014
    if (lp->chipset == DC21040) {
4015
        strcpy(name, "DE434/5");
4016
        return status;
4017
    } else {                           /* Search for a DEC name in the SROM */
4018
        int i = *((char *)&lp->srom + 19) * 3;
4019
        strncpy(name, (char *)&lp->srom + 26 + i, 8);
4020
    }
4021
    name[8] = '\0';
4022
    for (i=0; i<siglen; i++) {
4023
        if (strstr(name,de4x5_signatures[i])!=NULL) break;
4024
    }
4025
    if (i == siglen) {
4026
        if (dec_only) {
4027
            *name = '\0';
4028
        } else {                        /* Use chip name to avoid confusion */
4029
            strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
4030
                           ((lp->chipset == DC21041) ? "DC21041" :
4031
                            ((lp->chipset == DC21140) ? "DC21140" :
4032
                             ((lp->chipset == DC21142) ? "DC21142" :
4033
                              ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
4034
                             )))))));
4035
        }
4036
        if (lp->chipset != DC21041) {
4037
            useSROM = TRUE;             /* card is not recognisably DEC */
4038
        }
4039
    } else if ((lp->chipset & ~0x00ff) == DC2114x) {
4040
        useSROM = TRUE;
4041
    }
4042
 
4043
    return status;
4044
}
4045
 
4046
/*
4047
** Set up the Ethernet PROM counter to the start of the Ethernet address on
4048
** the DC21040, else  read the SROM for the other chips.
4049
** The SROM may not be present in a multi-MAC card, so first read the
4050
** MAC address and check for a bad address. If there is a bad one then exit
4051
** immediately with the prior srom contents intact (the h/w address will
4052
** be fixed up later).
4053
*/
4054
static void
4055
DevicePresent(u_long aprom_addr)
4056
{
4057
    int i, j=0;
4058
    struct bus_type *lp = &bus;
4059
 
4060
    if (lp->chipset == DC21040) {
4061
        if (lp->bus == EISA) {
4062
            enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
4063
        } else {
4064
            outl(0, aprom_addr);       /* Reset Ethernet Address ROM Pointer */
4065
        }
4066
    } else {                           /* Read new srom */
4067
        u_short tmp, *p = (short *)((char *)&lp->srom + SROM_HWADD);
4068
        for (i=0; i<(ETH_ALEN>>1); i++) {
4069
            tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
4070
            *p = le16_to_cpu(tmp);
4071
            j += *p++;
4072
        }
4073
        if ((j == 0) || (j == 0x2fffd)) {
4074
            return;
4075
        }
4076
 
4077
        p=(short *)&lp->srom;
4078
        for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4079
            tmp = srom_rd(aprom_addr, i);
4080
            *p++ = le16_to_cpu(tmp);
4081
        }
4082
        de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4083
    }
4084
 
4085
    return;
4086
}
4087
 
4088
/*
4089
** Since the write on the Enet PROM register doesn't seem to reset the PROM
4090
** pointer correctly (at least on my DE425 EISA card), this routine should do
4091
** it...from depca.c.
4092
*/
4093
static void
4094
enet_addr_rst(u_long aprom_addr)
4095
{
4096
    union {
4097
        struct {
4098
            u32 a;
4099
            u32 b;
4100
        } llsig;
4101
        char Sig[sizeof(u32) << 1];
4102
    } dev;
4103
    short sigLength=0;
4104
    s8 data;
4105
    int i, j;
4106
 
4107
    dev.llsig.a = ETH_PROM_SIG;
4108
    dev.llsig.b = ETH_PROM_SIG;
4109
    sigLength = sizeof(u32) << 1;
4110
 
4111
    for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4112
        data = inb(aprom_addr);
4113
        if (dev.Sig[j] == data) {    /* track signature */
4114
            j++;
4115
        } else {                     /* lost signature; begin search again */
4116
            if (data == dev.Sig[0]) {  /* rare case.... */
4117
                j=1;
4118
            } else {
4119
                j=0;
4120
            }
4121
        }
4122
    }
4123
 
4124
    return;
4125
}
4126
 
4127
/*
4128
** For the bad status case and no SROM, then add one to the previous
4129
** address. However, need to add one backwards in case we have 0xff
4130
** as one or more of the bytes. Only the last 3 bytes should be checked
4131
** as the first three are invariant - assigned to an organisation.
4132
*/
4133
static int
4134
get_hw_addr(struct device *dev)
4135
{
4136
    u_long iobase = dev->base_addr;
4137
    int broken, i, k, tmp, status = 0;
4138
    u_short j,chksum;
4139
    struct bus_type *lp = &bus;
4140
 
4141
    broken = de4x5_bad_srom(lp);
4142
 
4143
    for (i=0,k=0,j=0;j<3;j++) {
4144
        k <<= 1;
4145
        if (k > 0xffff) k-=0xffff;
4146
 
4147
        if (lp->bus == PCI) {
4148
            if (lp->chipset == DC21040) {
4149
                while ((tmp = inl(DE4X5_APROM)) < 0);
4150
                k += (u_char) tmp;
4151
                dev->dev_addr[i++] = (u_char) tmp;
4152
                while ((tmp = inl(DE4X5_APROM)) < 0);
4153
                k += (u_short) (tmp << 8);
4154
                dev->dev_addr[i++] = (u_char) tmp;
4155
            } else if (!broken) {
4156
                dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4157
                dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4158
            } else if ((broken == SMC) || (broken == ACCTON)) {
4159
                dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4160
                dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4161
            }
4162
        } else {
4163
            k += (u_char) (tmp = inb(EISA_APROM));
4164
            dev->dev_addr[i++] = (u_char) tmp;
4165
            k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4166
            dev->dev_addr[i++] = (u_char) tmp;
4167
        }
4168
 
4169
        if (k > 0xffff) k-=0xffff;
4170
    }
4171
    if (k == 0xffff) k=0;
4172
 
4173
    if (lp->bus == PCI) {
4174
        if (lp->chipset == DC21040) {
4175
            while ((tmp = inl(DE4X5_APROM)) < 0);
4176
            chksum = (u_char) tmp;
4177
            while ((tmp = inl(DE4X5_APROM)) < 0);
4178
            chksum |= (u_short) (tmp << 8);
4179
            if ((k != chksum) && (dec_only)) status = -1;
4180
        }
4181
    } else {
4182
        chksum = (u_char) inb(EISA_APROM);
4183
        chksum |= (u_short) (inb(EISA_APROM) << 8);
4184
        if ((k != chksum) && (dec_only)) status = -1;
4185
    }
4186
 
4187
    /* If possible, try to fix a broken card - SMC only so far */
4188
    srom_repair(dev, broken);
4189
 
4190
#ifdef CONFIG_PMAC
4191
    /*
4192
    ** If the address starts with 00 a0, we have to bit-reverse
4193
    ** each byte of the address.
4194
    */
4195
    if (dev->dev_addr[0] == 0 && dev->dev_addr[1] == 0xa0) {
4196
        for (i = 0; i < ETH_ALEN; ++i) {
4197
            int x = dev->dev_addr[i];
4198
            x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4199
            x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4200
            dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4201
        }
4202
    }
4203
#endif /* CONFIG_PMAC */
4204
 
4205
    /* Test for a bad enet address */
4206
    status = test_bad_enet(dev, status);
4207
 
4208
    return status;
4209
}
4210
 
4211
/*
4212
** Test for enet addresses in the first 32 bytes. The built-in strncmp
4213
** didn't seem to work here...?
4214
*/
4215
static int
4216
de4x5_bad_srom(struct bus_type *lp)
4217
{
4218
    int i, status = 0;
4219
 
4220
    for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) {
4221
        if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4222
            !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4223
            if (i == 0) {
4224
                status = SMC;
4225
            } else if (i == 1) {
4226
                status = ACCTON;
4227
            }
4228
            break;
4229
        }
4230
    }
4231
 
4232
    return status;
4233
}
4234
 
4235
static int
4236
de4x5_strncmp(char *a, char *b, int n)
4237
{
4238
    int ret=0;
4239
 
4240
    for (;n && !ret;n--) {
4241
        ret = *a++ - *b++;
4242
    }
4243
 
4244
    return ret;
4245
}
4246
 
4247
static void
4248
srom_repair(struct device *dev, int card)
4249
{
4250
    struct bus_type *lp = &bus;
4251
 
4252
    switch(card) {
4253
      case SMC:
4254
        memset((char *)&bus.srom, 0, sizeof(struct de4x5_srom));
4255
        memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4256
        memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4257
        useSROM = TRUE;
4258
        break;
4259
    }
4260
 
4261
    return;
4262
}
4263
 
4264
/*
4265
** Assume that the irq's do not follow the PCI spec - this is seems
4266
** to be true so far (2 for 2).
4267
*/
4268
static int
4269
test_bad_enet(struct device *dev, int status)
4270
{
4271
    struct bus_type *lp = &bus;
4272
    int i, tmp;
4273
 
4274
    for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4275
    if ((tmp == 0) || (tmp == 0x5fa)) {
4276
        if ((lp->chipset == last.chipset) &&
4277
            (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4278
            for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4279
            for (i=ETH_ALEN-1; i>2; --i) {
4280
                dev->dev_addr[i] += 1;
4281
                if (dev->dev_addr[i] != 0) break;
4282
            }
4283
            for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4284
            if (!an_exception(lp)) {
4285
                dev->irq = last.irq;
4286
            }
4287
 
4288
            status = 0;
4289
        }
4290
    } else if (!status) {
4291
        last.chipset = lp->chipset;
4292
        last.bus = lp->bus_num;
4293
        last.irq = dev->irq;
4294
        for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4295
    }
4296
 
4297
    return status;
4298
}
4299
 
4300
/*
4301
** List of board exceptions with correctly wired IRQs
4302
*/
4303
static int
4304
an_exception(struct bus_type *lp)
4305
{
4306
    if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4307
        (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4308
        return -1;
4309
    }
4310
 
4311
    return 0;
4312
}
4313
 
4314
/*
4315
** SROM Read
4316
*/
4317
static short
4318
srom_rd(u_long addr, u_char offset)
4319
{
4320
    sendto_srom(SROM_RD | SROM_SR, addr);
4321
 
4322
    srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4323
    srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4324
    srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4325
 
4326
    return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4327
}
4328
 
4329
static void
4330
srom_latch(u_int command, u_long addr)
4331
{
4332
    sendto_srom(command, addr);
4333
    sendto_srom(command | DT_CLK, addr);
4334
    sendto_srom(command, addr);
4335
 
4336
    return;
4337
}
4338
 
4339
static void
4340
srom_command(u_int command, u_long addr)
4341
{
4342
    srom_latch(command, addr);
4343
    srom_latch(command, addr);
4344
    srom_latch((command & 0x0000ff00) | DT_CS, addr);
4345
 
4346
    return;
4347
}
4348
 
4349
static void
4350
srom_address(u_int command, u_long addr, u_char offset)
4351
{
4352
    int i;
4353
    char a;
4354
 
4355
    a = (char)(offset << 2);
4356
    for (i=0; i<6; i++, a <<= 1) {
4357
        srom_latch(command | ((a < 0) ? DT_IN : 0), addr);
4358
    }
4359
    de4x5_us_delay(1);
4360
 
4361
    i = (getfrom_srom(addr) >> 3) & 0x01;
4362
 
4363
    return;
4364
}
4365
 
4366
static short
4367
srom_data(u_int command, u_long addr)
4368
{
4369
    int i;
4370
    short word = 0;
4371
    s32 tmp;
4372
 
4373
    for (i=0; i<16; i++) {
4374
        sendto_srom(command  | DT_CLK, addr);
4375
        tmp = getfrom_srom(addr);
4376
        sendto_srom(command, addr);
4377
 
4378
        word = (word << 1) | ((tmp >> 3) & 0x01);
4379
    }
4380
 
4381
    sendto_srom(command & 0x0000ff00, addr);
4382
 
4383
    return word;
4384
}
4385
 
4386
/*
4387
static void
4388
srom_busy(u_int command, u_long addr)
4389
{
4390
   sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4391
 
4392
   while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4393
       de4x5_ms_delay(1);
4394
   }
4395
 
4396
   sendto_srom(command & 0x0000ff00, addr);
4397
 
4398
   return;
4399
}
4400
*/
4401
 
4402
static void
4403
sendto_srom(u_int command, u_long addr)
4404
{
4405
    outl(command, addr);
4406
    udelay(1);
4407
 
4408
    return;
4409
}
4410
 
4411
static int
4412
getfrom_srom(u_long addr)
4413
{
4414
    s32 tmp;
4415
 
4416
    tmp = inl(addr);
4417
    udelay(1);
4418
 
4419
    return tmp;
4420
}
4421
 
4422
static int
4423
srom_infoleaf_info(struct device *dev)
4424
{
4425
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4426
    int i, count;
4427
    u_char *p;
4428
 
4429
    /* Find the infoleaf decoder function that matches this chipset */
4430
    for (i=0; i<INFOLEAF_SIZE; i++) {
4431
        if (lp->chipset == infoleaf_array[i].chipset) break;
4432
    }
4433
    if (i == INFOLEAF_SIZE) {
4434
        lp->useSROM = FALSE;
4435
        printk("%s: Cannot find correct chipset for SROM decoding!\n",
4436
                                                                  dev->name);
4437
        return -ENXIO;
4438
    }
4439
 
4440
    lp->infoleaf_fn = infoleaf_array[i].fn;
4441
 
4442
    /* Find the information offset that this function should use */
4443
    count = *((u_char *)&lp->srom + 19);
4444
    p  = (u_char *)&lp->srom + 26;
4445
 
4446
    if (count > 1) {
4447
        for (i=count; i; --i, p+=3) {
4448
            if (lp->device == *p) break;
4449
        }
4450
        if (i == 0) {
4451
            lp->useSROM = FALSE;
4452
            printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4453
                                                       dev->name, lp->device);
4454
            return -ENXIO;
4455
        }
4456
    }
4457
 
4458
    lp->infoleaf_offset = TWIDDLE(p+1);
4459
 
4460
    return 0;
4461
}
4462
 
4463
/*
4464
** This routine loads any type 1 or 3 MII info into the mii device
4465
** struct and executes any type 5 code to reset PHY devices for this
4466
** controller.
4467
** The info for the MII devices will be valid since the index used
4468
** will follow the discovery process from MII address 1-31 then 0.
4469
*/
4470
static void
4471
srom_init(struct device *dev)
4472
{
4473
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4474
    u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4475
    u_char count;
4476
 
4477
    p+=2;
4478
    if (lp->chipset == DC21140) {
4479
        lp->cache.gepc = (*p++ | GEP_CTRL);
4480
        gep_wr(lp->cache.gepc, dev);
4481
    }
4482
 
4483
    /* Block count */
4484
    count = *p++;
4485
 
4486
    /* Jump the infoblocks to find types */
4487
    for (;count; --count) {
4488
        if (*p < 128) {
4489
            p += COMPACT_LEN;
4490
        } else if (*(p+1) == 5) {
4491
            type5_infoblock(dev, 1, p);
4492
            p += ((*p & BLOCK_LEN) + 1);
4493
        } else if (*(p+1) == 4) {
4494
            p += ((*p & BLOCK_LEN) + 1);
4495
        } else if (*(p+1) == 3) {
4496
            type3_infoblock(dev, 1, p);
4497
            p += ((*p & BLOCK_LEN) + 1);
4498
        } else if (*(p+1) == 2) {
4499
            p += ((*p & BLOCK_LEN) + 1);
4500
        } else if (*(p+1) == 1) {
4501
            type1_infoblock(dev, 1, p);
4502
            p += ((*p & BLOCK_LEN) + 1);
4503
        } else {
4504
            p += ((*p & BLOCK_LEN) + 1);
4505
        }
4506
    }
4507
 
4508
    return;
4509
}
4510
 
4511
/*
4512
** A generic routine that writes GEP control, data and reset information
4513
** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4514
*/
4515
static void
4516
srom_exec(struct device *dev, u_char *p)
4517
{
4518
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4519
    u_long iobase = dev->base_addr;
4520
    u_char count = (p ? *p++ : 0);
4521
    u_short *w = (u_short *)p;
4522
 
4523
    if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4524
 
4525
    if (lp->chipset != DC21140) RESET_SIA;
4526
 
4527
    while (count--) {
4528
        gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4529
                                                   *p++ : TWIDDLE(w++)), dev);
4530
        udelay(2000);                       /* 2ms per action */
4531
    }
4532
 
4533
    if (lp->chipset != DC21140) {
4534
        outl(lp->cache.csr14, DE4X5_STRR);
4535
        outl(lp->cache.csr13, DE4X5_SICR);
4536
    }
4537
 
4538
    return;
4539
}
4540
 
4541
/*
4542
** Basically this function is a NOP since it will never be called,
4543
** unless I implement the DC21041 SROM functions. There's no need
4544
** since the existing code will be satisfactory for all boards.
4545
*/
4546
static int
4547
dc21041_infoleaf(struct device *dev)
4548
{
4549
    return DE4X5_AUTOSENSE_MS;
4550
}
4551
 
4552
static int
4553
dc21140_infoleaf(struct device *dev)
4554
{
4555
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4556
    u_char count = 0;
4557
    u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4558
    int next_tick = DE4X5_AUTOSENSE_MS;
4559
 
4560
    /* Read the connection type */
4561
    p+=2;
4562
 
4563
    /* GEP control */
4564
    lp->cache.gepc = (*p++ | GEP_CTRL);
4565
 
4566
    /* Block count */
4567
    count = *p++;
4568
 
4569
    /* Recursively figure out the info blocks */
4570
    if (*p < 128) {
4571
        next_tick = dc_infoblock[COMPACT](dev, count, p);
4572
    } else {
4573
        next_tick = dc_infoblock[*(p+1)](dev, count, p);
4574
    }
4575
 
4576
    if (lp->tcount == count) {
4577
        lp->media = NC;
4578
        if (lp->media != lp->c_media) {
4579
            de4x5_dbg_media(dev);
4580
            lp->c_media = lp->media;
4581
        }
4582
        lp->media = INIT;
4583
        lp->tcount = 0;
4584
        lp->tx_enable = FALSE;
4585
    }
4586
 
4587
    return next_tick & ~TIMER_CB;
4588
}
4589
 
4590
static int
4591
dc21142_infoleaf(struct device *dev)
4592
{
4593
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4594
    u_char count = 0;
4595
    u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4596
    int next_tick = DE4X5_AUTOSENSE_MS;
4597
 
4598
    /* Read the connection type */
4599
    p+=2;
4600
 
4601
    /* Block count */
4602
    count = *p++;
4603
 
4604
    /* Recursively figure out the info blocks */
4605
    if (*p < 128) {
4606
        next_tick = dc_infoblock[COMPACT](dev, count, p);
4607
    } else {
4608
        next_tick = dc_infoblock[*(p+1)](dev, count, p);
4609
    }
4610
 
4611
    if (lp->tcount == count) {
4612
        lp->media = NC;
4613
        if (lp->media != lp->c_media) {
4614
            de4x5_dbg_media(dev);
4615
            lp->c_media = lp->media;
4616
        }
4617
        lp->media = INIT;
4618
        lp->tcount = 0;
4619
        lp->tx_enable = FALSE;
4620
    }
4621
 
4622
    return next_tick & ~TIMER_CB;
4623
}
4624
 
4625
static int
4626
dc21143_infoleaf(struct device *dev)
4627
{
4628
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4629
    u_char count = 0;
4630
    u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4631
    int next_tick = DE4X5_AUTOSENSE_MS;
4632
 
4633
    /* Read the connection type */
4634
    p+=2;
4635
 
4636
    /* Block count */
4637
    count = *p++;
4638
 
4639
    /* Recursively figure out the info blocks */
4640
    if (*p < 128) {
4641
        next_tick = dc_infoblock[COMPACT](dev, count, p);
4642
    } else {
4643
        next_tick = dc_infoblock[*(p+1)](dev, count, p);
4644
    }
4645
    if (lp->tcount == count) {
4646
        lp->media = NC;
4647
        if (lp->media != lp->c_media) {
4648
            de4x5_dbg_media(dev);
4649
            lp->c_media = lp->media;
4650
        }
4651
        lp->media = INIT;
4652
        lp->tcount = 0;
4653
        lp->tx_enable = FALSE;
4654
    }
4655
 
4656
    return next_tick & ~TIMER_CB;
4657
}
4658
 
4659
/*
4660
** The compact infoblock is only designed for DC21140[A] chips, so
4661
** we'll reuse the dc21140m_autoconf function. Non MII media only.
4662
*/
4663
static int
4664
compact_infoblock(struct device *dev, u_char count, u_char *p)
4665
{
4666
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4667
    u_char flags, csr6;
4668
 
4669
    /* Recursively figure out the info blocks */
4670
    if (--count > lp->tcount) {
4671
        if (*(p+COMPACT_LEN) < 128) {
4672
            return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4673
        } else {
4674
            return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4675
        }
4676
    }
4677
 
4678
    if ((lp->media == INIT) && (lp->timeout < 0)) {
4679
        lp->ibn = COMPACT;
4680
        lp->active = 0;
4681
        gep_wr(lp->cache.gepc, dev);
4682
        lp->infoblock_media = (*p++) & COMPACT_MC;
4683
        lp->cache.gep = *p++;
4684
        csr6 = *p++;
4685
        flags = *p++;
4686
 
4687
        lp->asBitValid = (flags & 0x80) ? 0 : -1;
4688
        lp->defMedium = (flags & 0x40) ? -1 : 0;
4689
        lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4690
        lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4691
        lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4692
        lp->useMII = FALSE;
4693
 
4694
        de4x5_switch_mac_port(dev);
4695
    }
4696
 
4697
    return dc21140m_autoconf(dev);
4698
}
4699
 
4700
/*
4701
** This block describes non MII media for the DC21140[A] only.
4702
*/
4703
static int
4704
type0_infoblock(struct device *dev, u_char count, u_char *p)
4705
{
4706
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4707
    u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4708
 
4709
    /* Recursively figure out the info blocks */
4710
    if (--count > lp->tcount) {
4711
        if (*(p+len) < 128) {
4712
            return dc_infoblock[COMPACT](dev, count, p+len);
4713
        } else {
4714
            return dc_infoblock[*(p+len+1)](dev, count, p+len);
4715
        }
4716
    }
4717
 
4718
    if ((lp->media == INIT) && (lp->timeout < 0)) {
4719
        lp->ibn = 0;
4720
        lp->active = 0;
4721
        gep_wr(lp->cache.gepc, dev);
4722
        p+=2;
4723
        lp->infoblock_media = (*p++) & BLOCK0_MC;
4724
        lp->cache.gep = *p++;
4725
        csr6 = *p++;
4726
        flags = *p++;
4727
 
4728
        lp->asBitValid = (flags & 0x80) ? 0 : -1;
4729
        lp->defMedium = (flags & 0x40) ? -1 : 0;
4730
        lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4731
        lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4732
        lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4733
        lp->useMII = FALSE;
4734
 
4735
        de4x5_switch_mac_port(dev);
4736
    }
4737
 
4738
    return dc21140m_autoconf(dev);
4739
}
4740
 
4741
/* These functions are under construction! */
4742
 
4743
static int
4744
type1_infoblock(struct device *dev, u_char count, u_char *p)
4745
{
4746
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4747
    u_char len = (*p & BLOCK_LEN)+1;
4748
 
4749
    /* Recursively figure out the info blocks */
4750
    if (--count > lp->tcount) {
4751
        if (*(p+len) < 128) {
4752
            return dc_infoblock[COMPACT](dev, count, p+len);
4753
        } else {
4754
            return dc_infoblock[*(p+len+1)](dev, count, p+len);
4755
        }
4756
    }
4757
 
4758
    p += 2;
4759
    if (lp->state == INITIALISED) {
4760
        lp->ibn = 1;
4761
        lp->active = *p++;
4762
        lp->phy[lp->active].gep = (*p ? p : 0); p += (*p + 1);
4763
        lp->phy[lp->active].rst = (*p ? p : 0); p += (*p + 1);
4764
        lp->phy[lp->active].mc  = TWIDDLE(p); p += 2;
4765
        lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4766
        lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4767
        lp->phy[lp->active].ttm = TWIDDLE(p);
4768
        return 0;
4769
    } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4770
        lp->ibn = 1;
4771
        lp->active = *p;
4772
        lp->infoblock_csr6 = OMR_MII_100;
4773
        lp->useMII = TRUE;
4774
        lp->infoblock_media = ANS;
4775
 
4776
        de4x5_switch_mac_port(dev);
4777
    }
4778
 
4779
    return dc21140m_autoconf(dev);
4780
}
4781
 
4782
static int
4783
type2_infoblock(struct device *dev, u_char count, u_char *p)
4784
{
4785
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4786
    u_char len = (*p & BLOCK_LEN)+1;
4787
 
4788
    /* Recursively figure out the info blocks */
4789
    if (--count > lp->tcount) {
4790
        if (*(p+len) < 128) {
4791
            return dc_infoblock[COMPACT](dev, count, p+len);
4792
        } else {
4793
            return dc_infoblock[*(p+len+1)](dev, count, p+len);
4794
        }
4795
    }
4796
 
4797
    if ((lp->media == INIT) && (lp->timeout < 0)) {
4798
        lp->ibn = 2;
4799
        lp->active = 0;
4800
        p += 2;
4801
        lp->infoblock_media = (*p) & MEDIA_CODE;
4802
 
4803
        if ((*p++) & EXT_FIELD) {
4804
            lp->cache.csr13 = TWIDDLE(p); p += 2;
4805
            lp->cache.csr14 = TWIDDLE(p); p += 2;
4806
            lp->cache.csr15 = TWIDDLE(p); p += 2;
4807
        } else {
4808
            lp->cache.csr13 = CSR13;
4809
            lp->cache.csr14 = CSR14;
4810
            lp->cache.csr15 = CSR15;
4811
        }
4812
        lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4813
        lp->cache.gep  = ((s32)(TWIDDLE(p)) << 16);
4814
        lp->infoblock_csr6 = OMR_SIA;
4815
        lp->useMII = FALSE;
4816
 
4817
        de4x5_switch_mac_port(dev);
4818
    }
4819
 
4820
    return dc2114x_autoconf(dev);
4821
}
4822
 
4823
static int
4824
type3_infoblock(struct device *dev, u_char count, u_char *p)
4825
{
4826
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4827
    u_char len = (*p & BLOCK_LEN)+1;
4828
 
4829
    /* Recursively figure out the info blocks */
4830
    if (--count > lp->tcount) {
4831
        if (*(p+len) < 128) {
4832
            return dc_infoblock[COMPACT](dev, count, p+len);
4833
        } else {
4834
            return dc_infoblock[*(p+len+1)](dev, count, p+len);
4835
        }
4836
    }
4837
 
4838
    p += 2;
4839
    if (lp->state == INITIALISED) {
4840
        lp->ibn = 3;
4841
        lp->active = *p++;
4842
        lp->phy[lp->active].gep = (*p ? p : 0); p += (2 * (*p) + 1);
4843
        lp->phy[lp->active].rst = (*p ? p : 0); p += (2 * (*p) + 1);
4844
        lp->phy[lp->active].mc  = TWIDDLE(p); p += 2;
4845
        lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4846
        lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4847
        lp->phy[lp->active].ttm = TWIDDLE(p); p += 2;
4848
        lp->phy[lp->active].mci = *p;
4849
        return 0;
4850
    } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4851
        lp->ibn = 3;
4852
        lp->active = *p;
4853
        lp->infoblock_csr6 = OMR_MII_100;
4854
        lp->useMII = TRUE;
4855
        lp->infoblock_media = ANS;
4856
 
4857
        de4x5_switch_mac_port(dev);
4858
    }
4859
 
4860
    return dc2114x_autoconf(dev);
4861
}
4862
 
4863
static int
4864
type4_infoblock(struct device *dev, u_char count, u_char *p)
4865
{
4866
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4867
    u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4868
 
4869
    /* Recursively figure out the info blocks */
4870
    if (--count > lp->tcount) {
4871
        if (*(p+len) < 128) {
4872
            return dc_infoblock[COMPACT](dev, count, p+len);
4873
        } else {
4874
            return dc_infoblock[*(p+len+1)](dev, count, p+len);
4875
        }
4876
    }
4877
 
4878
    if ((lp->media == INIT) && (lp->timeout < 0)) {
4879
        lp->ibn = 4;
4880
        lp->active = 0;
4881
        p+=2;
4882
        lp->infoblock_media = (*p++) & MEDIA_CODE;
4883
        lp->cache.csr13 = CSR13;              /* Hard coded defaults */
4884
        lp->cache.csr14 = CSR14;
4885
        lp->cache.csr15 = CSR15;
4886
        lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4887
        lp->cache.gep  = ((s32)(TWIDDLE(p)) << 16); p += 2;
4888
        csr6 = *p++;
4889
        flags = *p++;
4890
 
4891
        lp->asBitValid = (flags & 0x80) ? 0 : -1;
4892
        lp->defMedium = (flags & 0x40) ? -1 : 0;
4893
        lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4894
        lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4895
        lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4896
        lp->useMII = FALSE;
4897
 
4898
        de4x5_switch_mac_port(dev);
4899
    }
4900
 
4901
    return dc2114x_autoconf(dev);
4902
}
4903
 
4904
/*
4905
** This block type provides information for resetting external devices
4906
** (chips) through the General Purpose Register.
4907
*/
4908
static int
4909
type5_infoblock(struct device *dev, u_char count, u_char *p)
4910
{
4911
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4912
    u_char len = (*p & BLOCK_LEN)+1;
4913
 
4914
    /* Recursively figure out the info blocks */
4915
    if (--count > lp->tcount) {
4916
        if (*(p+len) < 128) {
4917
            return dc_infoblock[COMPACT](dev, count, p+len);
4918
        } else {
4919
            return dc_infoblock[*(p+len+1)](dev, count, p+len);
4920
        }
4921
    }
4922
 
4923
    /* Must be initializing to run this code */
4924
    if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4925
        p+=2;
4926
        lp->rst = p;
4927
        srom_exec(dev, lp->rst);
4928
    }
4929
 
4930
    return DE4X5_AUTOSENSE_MS;
4931
}
4932
 
4933
/*
4934
** MII Read/Write
4935
*/
4936
 
4937
static int
4938
mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4939
{
4940
    mii_wdata(MII_PREAMBLE,  2, ioaddr);   /* Start of 34 bit preamble...    */
4941
    mii_wdata(MII_PREAMBLE, 32, ioaddr);   /* ...continued                   */
4942
    mii_wdata(MII_STRD, 4, ioaddr);        /* SFD and Read operation         */
4943
    mii_address(phyaddr, ioaddr);          /* PHY address to be accessed     */
4944
    mii_address(phyreg, ioaddr);           /* PHY Register to read           */
4945
    mii_ta(MII_STRD, ioaddr);              /* Turn around time - 2 MDC       */
4946
 
4947
    return mii_rdata(ioaddr);              /* Read data                      */
4948
}
4949
 
4950
static void
4951
mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4952
{
4953
    mii_wdata(MII_PREAMBLE,  2, ioaddr);   /* Start of 34 bit preamble...    */
4954
    mii_wdata(MII_PREAMBLE, 32, ioaddr);   /* ...continued                   */
4955
    mii_wdata(MII_STWR, 4, ioaddr);        /* SFD and Write operation        */
4956
    mii_address(phyaddr, ioaddr);          /* PHY address to be accessed     */
4957
    mii_address(phyreg, ioaddr);           /* PHY Register to write          */
4958
    mii_ta(MII_STWR, ioaddr);              /* Turn around time - 2 MDC       */
4959
    data = mii_swap(data, 16);             /* Swap data bit ordering         */
4960
    mii_wdata(data, 16, ioaddr);           /* Write data                     */
4961
 
4962
    return;
4963
}
4964
 
4965
static int
4966
mii_rdata(u_long ioaddr)
4967
{
4968
    int i;
4969
    s32 tmp = 0;
4970
 
4971
    for (i=0; i<16; i++) {
4972
        tmp <<= 1;
4973
        tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4974
    }
4975
 
4976
    return tmp;
4977
}
4978
 
4979
static void
4980
mii_wdata(int data, int len, u_long ioaddr)
4981
{
4982
    int i;
4983
 
4984
    for (i=0; i<len; i++) {
4985
        sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4986
        data >>= 1;
4987
    }
4988
 
4989
    return;
4990
}
4991
 
4992
static void
4993
mii_address(u_char addr, u_long ioaddr)
4994
{
4995
    int i;
4996
 
4997
    addr = mii_swap(addr, 5);
4998
    for (i=0; i<5; i++) {
4999
        sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
5000
        addr >>= 1;
5001
    }
5002
 
5003
    return;
5004
}
5005
 
5006
static void
5007
mii_ta(u_long rw, u_long ioaddr)
5008
{
5009
    if (rw == MII_STWR) {
5010
        sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
5011
        sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
5012
    } else {
5013
        getfrom_mii(MII_MRD | MII_RD, ioaddr);        /* Tri-state MDIO */
5014
    }
5015
 
5016
    return;
5017
}
5018
 
5019
static int
5020
mii_swap(int data, int len)
5021
{
5022
    int i, tmp = 0;
5023
 
5024
    for (i=0; i<len; i++) {
5025
        tmp <<= 1;
5026
        tmp |= (data & 1);
5027
        data >>= 1;
5028
    }
5029
 
5030
    return tmp;
5031
}
5032
 
5033
static void
5034
sendto_mii(u32 command, int data, u_long ioaddr)
5035
{
5036
    u32 j;
5037
 
5038
    j = (data & 1) << 17;
5039
    outl(command | j, ioaddr);
5040
    udelay(1);
5041
    outl(command | MII_MDC | j, ioaddr);
5042
    udelay(1);
5043
 
5044
    return;
5045
}
5046
 
5047
static int
5048
getfrom_mii(u32 command, u_long ioaddr)
5049
{
5050
    outl(command, ioaddr);
5051
    udelay(1);
5052
    outl(command | MII_MDC, ioaddr);
5053
    udelay(1);
5054
 
5055
    return ((inl(ioaddr) >> 19) & 1);
5056
}
5057
 
5058
/*
5059
** Here's 3 ways to calculate the OUI from the ID registers.
5060
*/
5061
static int
5062
mii_get_oui(u_char phyaddr, u_long ioaddr)
5063
{
5064
/*
5065
    union {
5066
        u_short reg;
5067
        u_char breg[2];
5068
    } a;
5069
    int i, r2, r3, ret=0;*/
5070
    int r2, r3;
5071
 
5072
    /* Read r2 and r3 */
5073
    r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5074
    r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5075
                                                /* SEEQ and Cypress way * /
5076
    / * Shuffle r2 and r3 * /
5077
    a.reg=0;
5078
    r3 = ((r3>>10)|(r2<<6))&0x0ff;
5079
    r2 = ((r2>>2)&0x3fff);
5080
 
5081
    / * Bit reverse r3 * /
5082
    for (i=0;i<8;i++) {
5083
        ret<<=1;
5084
        ret |= (r3&1);
5085
        r3>>=1;
5086
    }
5087
 
5088
    / * Bit reverse r2 * /
5089
    for (i=0;i<16;i++) {
5090
        a.reg<<=1;
5091
        a.reg |= (r2&1);
5092
        r2>>=1;
5093
    }
5094
 
5095
    / * Swap r2 bytes * /
5096
    i=a.breg[0];
5097
    a.breg[0]=a.breg[1];
5098
    a.breg[1]=i;
5099
 
5100
    return ((a.reg<<8)|ret); */                 /* SEEQ and Cypress way */
5101
/*    return ((r2<<6)|(u_int)(r3>>10)); */      /* NATIONAL and BROADCOM way */
5102
    return r2;                                  /* (I did it) My way */
5103
}
5104
 
5105
/*
5106
** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5107
*/
5108
static int
5109
mii_get_phy(struct device *dev)
5110
{
5111
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5112
    u_long iobase = dev->base_addr;
5113
    int i, j, k, n, limit=sizeof(phy_info)/sizeof(struct phy_table);
5114
    int id;
5115
 
5116
    lp->active = 0;
5117
    lp->useMII = TRUE;
5118
 
5119
    /* Search the MII address space for possible PHY devices */
5120
    for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(++i)%DE4X5_MAX_MII) {
5121
        lp->phy[lp->active].addr = i;
5122
        if (i==0) n++;                             /* Count cycles */
5123
        while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
5124
        id = mii_get_oui(i, DE4X5_MII);
5125
        if ((id == 0) || (id == 65535)) continue;  /* Valid ID? */
5126
        for (j=0; j<limit; j++) {                  /* Search PHY table */
5127
            if (id != phy_info[j].id) continue;    /* ID match? */
5128
            for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5129
            if (k < DE4X5_MAX_PHY) {
5130
                memcpy((char *)&lp->phy[k],
5131
                       (char *)&phy_info[j], sizeof(struct phy_table));
5132
                lp->phy[k].addr = i;
5133
                lp->mii_cnt++;
5134
                lp->active++;
5135
            } else {
5136
                goto purgatory;                    /* Stop the search */
5137
            }
5138
            break;
5139
        }
5140
        if ((j == limit) && (i < DE4X5_MAX_MII)) {
5141
            for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5142
            lp->phy[k].addr = i;
5143
            lp->phy[k].id = id;
5144
            lp->phy[k].spd.reg = GENERIC_REG;      /* ANLPA register         */
5145
            lp->phy[k].spd.mask = GENERIC_MASK;    /* 100Mb/s technologies   */
5146
            lp->phy[k].spd.value = GENERIC_VALUE;  /* TX & T4, H/F Duplex    */
5147
            lp->mii_cnt++;
5148
            lp->active++;
5149
            printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5150
            j = de4x5_debug;
5151
            de4x5_debug |= DEBUG_MII;
5152
            de4x5_dbg_mii(dev, k);
5153
            de4x5_debug = j;
5154
            printk("\n");
5155
        }
5156
    }
5157
  purgatory:
5158
    lp->active = 0;
5159
    if (lp->phy[0].id) {                           /* Reset the PHY devices */
5160
        for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/
5161
            mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5162
            while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5163
 
5164
            de4x5_dbg_mii(dev, k);
5165
        }
5166
    }
5167
    if (!lp->mii_cnt) lp->useMII = FALSE;
5168
 
5169
    return lp->mii_cnt;
5170
}
5171
 
5172
static char *
5173
build_setup_frame(struct device *dev, int mode)
5174
{
5175
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5176
    int i;
5177
    char *pa = lp->setup_frame;
5178
 
5179
    /* Initialise the setup frame */
5180
    if (mode == ALL) {
5181
        memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5182
    }
5183
 
5184
    if (lp->setup_f == HASH_PERF) {
5185
        for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5186
            *(pa + i) = dev->dev_addr[i];                 /* Host address */
5187
            if (i & 0x01) pa += 2;
5188
        }
5189
        *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5190
    } else {
5191
        for (i=0; i<ETH_ALEN; i++) { /* Host address */
5192
            *(pa + (i&1)) = dev->dev_addr[i];
5193
            if (i & 0x01) pa += 4;
5194
        }
5195
        for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5196
            *(pa + (i&1)) = (char) 0xff;
5197
            if (i & 0x01) pa += 4;
5198
        }
5199
    }
5200
 
5201
    return pa;                     /* Points to the next entry */
5202
}
5203
 
5204
static void
5205
enable_ast(struct device *dev, u32 time_out)
5206
{
5207
    timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out);
5208
 
5209
    return;
5210
}
5211
 
5212
static void
5213
disable_ast(struct device *dev)
5214
{
5215
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5216
 
5217
    del_timer(&lp->timer);
5218
 
5219
    return;
5220
}
5221
 
5222
static long
5223
de4x5_switch_mac_port(struct device *dev)
5224
{
5225
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5226
    u_long iobase = dev->base_addr;
5227
    s32 omr;
5228
 
5229
    STOP_DE4X5;
5230
 
5231
    /* Assert the OMR_PS bit in CSR6 */
5232
    omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5233
                                                                     OMR_FDX));
5234
    omr |= lp->infoblock_csr6;
5235
    if (omr & OMR_PS) omr |= OMR_HBD;
5236
    outl(omr, DE4X5_OMR);
5237
 
5238
    /* Soft Reset */
5239
    RESET_DE4X5;
5240
 
5241
    /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5242
    if (lp->chipset == DC21140) {
5243
        gep_wr(lp->cache.gepc, dev);
5244
        gep_wr(lp->cache.gep, dev);
5245
    } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5246
        reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5247
    }
5248
 
5249
    /* Restore CSR6 */
5250
    outl(omr, DE4X5_OMR);
5251
 
5252
    /* Reset CSR8 */
5253
    inl(DE4X5_MFC);
5254
 
5255
    return omr;
5256
}
5257
 
5258
static void
5259
gep_wr(s32 data, struct device *dev)
5260
{
5261
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5262
    u_long iobase = dev->base_addr;
5263
 
5264
    if (lp->chipset == DC21140) {
5265
        outl(data, DE4X5_GEP);
5266
    } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5267
        outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5268
    }
5269
 
5270
    return;
5271
}
5272
 
5273
static int
5274
gep_rd(struct device *dev)
5275
{
5276
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5277
    u_long iobase = dev->base_addr;
5278
 
5279
    if (lp->chipset == DC21140) {
5280
        return inl(DE4X5_GEP);
5281
    } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5282
        return (inl(DE4X5_SIGR) & 0x000fffff);
5283
    }
5284
 
5285
    return 0;
5286
}
5287
 
5288
static void
5289
timeout(struct device *dev, void (*fn)(u_long data), u_long data, u_long msec)
5290
{
5291
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5292
    int dt;
5293
 
5294
    /* First, cancel any pending timer events */
5295
    del_timer(&lp->timer);
5296
 
5297
    /* Convert msec to ticks */
5298
    dt = (msec * HZ) / 1000;
5299
    if (dt==0) dt=1;
5300
 
5301
    /* Set up timer */
5302
    lp->timer.expires = jiffies + dt;
5303
    lp->timer.function = fn;
5304
    lp->timer.data = data;
5305
    add_timer(&lp->timer);
5306
 
5307
    return;
5308
}
5309
 
5310
static void
5311
yawn(struct device *dev, int state)
5312
{
5313
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5314
    u_long iobase = dev->base_addr;
5315
 
5316
    if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5317
 
5318
    if(lp->bus == EISA) {
5319
        switch(state) {
5320
          case WAKEUP:
5321
            outb(WAKEUP, PCI_CFPM);
5322
            de4x5_ms_delay(10);
5323
            break;
5324
 
5325
          case SNOOZE:
5326
            outb(SNOOZE, PCI_CFPM);
5327
            break;
5328
 
5329
          case SLEEP:
5330
            outl(0, DE4X5_SICR);
5331
            outb(SLEEP, PCI_CFPM);
5332
            break;
5333
        }
5334
    } else {
5335
        switch(state) {
5336
          case WAKEUP:
5337
            pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5338
                                      PCI_CFDA_PSM, WAKEUP);
5339
            de4x5_ms_delay(10);
5340
            break;
5341
 
5342
          case SNOOZE:
5343
            pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5344
                                      PCI_CFDA_PSM, SNOOZE);
5345
            break;
5346
 
5347
          case SLEEP:
5348
            outl(0, DE4X5_SICR);
5349
            pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5350
                                      PCI_CFDA_PSM, SLEEP);
5351
            break;
5352
        }
5353
    }
5354
 
5355
    return;
5356
}
5357
 
5358
static void
5359
de4x5_parse_params(struct device *dev)
5360
{
5361
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5362
    char *p, *q, t;
5363
 
5364
    lp->params.fdx = 0;
5365
    lp->params.autosense = AUTO;
5366
 
5367
    if (args == NULL) return;
5368
 
5369
    if ((p = strstr(args, dev->name))) {
5370
        if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5371
        t = *q;
5372
        *q = '\0';
5373
 
5374
        if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5375
 
5376
        if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5377
            if (strstr(p, "TP")) {
5378
                lp->params.autosense = TP;
5379
            } else if (strstr(p, "TP_NW")) {
5380
                lp->params.autosense = TP_NW;
5381
            } else if (strstr(p, "BNC")) {
5382
                lp->params.autosense = BNC;
5383
            } else if (strstr(p, "AUI")) {
5384
                lp->params.autosense = AUI;
5385
            } else if (strstr(p, "BNC_AUI")) {
5386
                lp->params.autosense = BNC;
5387
            } else if (strstr(p, "10Mb")) {
5388
                lp->params.autosense = _10Mb;
5389
            } else if (strstr(p, "100Mb")) {
5390
                lp->params.autosense = _100Mb;
5391
            } else if (strstr(p, "AUTO")) {
5392
                lp->params.autosense = AUTO;
5393
            }
5394
        }
5395
        *q = t;
5396
    }
5397
 
5398
    return;
5399
}
5400
 
5401
static void
5402
de4x5_dbg_open(struct device *dev)
5403
{
5404
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5405
    int i;
5406
 
5407
    if (de4x5_debug & DEBUG_OPEN) {
5408
        printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5409
        printk("\tphysical address: ");
5410
        for (i=0;i<6;i++) {
5411
            printk("%2.2x:",(short)dev->dev_addr[i]);
5412
        }
5413
        printk("\n");
5414
        printk("Descriptor head addresses:\n");
5415
        printk("\t0x%8.8lx  0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5416
        printk("Descriptor addresses:\nRX: ");
5417
        for (i=0;i<lp->rxRingSize-1;i++){
5418
            if (i < 3) {
5419
                printk("0x%8.8lx  ",(u_long)&lp->rx_ring[i].status);
5420
            }
5421
        }
5422
        printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5423
        printk("TX: ");
5424
        for (i=0;i<lp->txRingSize-1;i++){
5425
            if (i < 3) {
5426
                printk("0x%8.8lx  ", (u_long)&lp->tx_ring[i].status);
5427
            }
5428
        }
5429
        printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5430
        printk("Descriptor buffers:\nRX: ");
5431
        for (i=0;i<lp->rxRingSize-1;i++){
5432
            if (i < 3) {
5433
                printk("0x%8.8x  ",le32_to_cpu(lp->rx_ring[i].buf));
5434
            }
5435
        }
5436
        printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5437
        printk("TX: ");
5438
        for (i=0;i<lp->txRingSize-1;i++){
5439
            if (i < 3) {
5440
                printk("0x%8.8x  ", le32_to_cpu(lp->tx_ring[i].buf));
5441
            }
5442
        }
5443
        printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5444
        printk("Ring size: \nRX: %d\nTX: %d\n",
5445
               (short)lp->rxRingSize,
5446
               (short)lp->txRingSize);
5447
    }
5448
 
5449
    return;
5450
}
5451
 
5452
static void
5453
de4x5_dbg_mii(struct device *dev, int k)
5454
{
5455
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5456
    u_long iobase = dev->base_addr;
5457
 
5458
    if (de4x5_debug & DEBUG_MII) {
5459
        printk("\nMII device address: %d\n", lp->phy[k].addr);
5460
        printk("MII CR:  %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5461
        printk("MII SR:  %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5462
        printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5463
        printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5464
        if (lp->phy[k].id != BROADCOM_T4) {
5465
            printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5466
            printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5467
        }
5468
        printk("MII 16:  %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5469
        if (lp->phy[k].id != BROADCOM_T4) {
5470
            printk("MII 17:  %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5471
            printk("MII 18:  %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5472
        } else {
5473
            printk("MII 20:  %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5474
        }
5475
    }
5476
 
5477
    return;
5478
}
5479
 
5480
static void
5481
de4x5_dbg_media(struct device *dev)
5482
{
5483
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5484
 
5485
    if (lp->media != lp->c_media) {
5486
        if (de4x5_debug & DEBUG_MEDIA) {
5487
            printk("%s: media is %s%s\n", dev->name,
5488
                   (lp->media == NC  ? "unconnected, link down or incompatible connection" :
5489
                    (lp->media == TP  ? "TP" :
5490
                     (lp->media == ANS ? "TP/Nway" :
5491
                      (lp->media == BNC ? "BNC" :
5492
                       (lp->media == AUI ? "AUI" :
5493
                        (lp->media == BNC_AUI ? "BNC/AUI" :
5494
                         (lp->media == EXT_SIA ? "EXT SIA" :
5495
                          (lp->media == _100Mb  ? "100Mb/s" :
5496
                           (lp->media == _10Mb   ? "10Mb/s" :
5497
                            "???"
5498
                            ))))))))), (lp->fdx?" full duplex.":"."));
5499
        }
5500
        lp->c_media = lp->media;
5501
    }
5502
 
5503
    return;
5504
}
5505
 
5506
static void
5507
de4x5_dbg_srom(struct de4x5_srom *p)
5508
{
5509
    int i;
5510
 
5511
    if (de4x5_debug & DEBUG_SROM) {
5512
        printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5513
        printk("Sub-system ID:        %04x\n", *((u_short *)p->sub_system_id));
5514
        printk("ID Block CRC:         %02x\n", (u_char)(p->id_block_crc));
5515
        printk("SROM version:         %02x\n", (u_char)(p->version));
5516
        printk("# controllers:         %02x\n", (u_char)(p->num_controllers));
5517
 
5518
        printk("Hardware Address:     ");
5519
        for (i=0;i<ETH_ALEN-1;i++) {
5520
            printk("%02x:", (u_char)*(p->ieee_addr+i));
5521
        }
5522
        printk("%02x\n", (u_char)*(p->ieee_addr+i));
5523
        printk("CRC checksum:         %04x\n", (u_short)(p->chksum));
5524
        for (i=0; i<64; i++) {
5525
            printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5526
        }
5527
    }
5528
 
5529
    return;
5530
}
5531
 
5532
static void
5533
de4x5_dbg_rx(struct sk_buff *skb, int len)
5534
{
5535
    int i, j;
5536
 
5537
    if (de4x5_debug & DEBUG_RX) {
5538
        printk("R: %02x:%02x:%02x:%02x:%02x:%02x <- %02x:%02x:%02x:%02x:%02x:%02x len/SAP:%02x%02x [%d]\n",
5539
               (u_char)skb->data[0],
5540
               (u_char)skb->data[1],
5541
               (u_char)skb->data[2],
5542
               (u_char)skb->data[3],
5543
               (u_char)skb->data[4],
5544
               (u_char)skb->data[5],
5545
               (u_char)skb->data[6],
5546
               (u_char)skb->data[7],
5547
               (u_char)skb->data[8],
5548
               (u_char)skb->data[9],
5549
               (u_char)skb->data[10],
5550
               (u_char)skb->data[11],
5551
               (u_char)skb->data[12],
5552
               (u_char)skb->data[13],
5553
               len);
5554
        if (de4x5_debug & DEBUG_RX) {
5555
            for (j=0; len>0;j+=16, len-=16) {
5556
                printk("    %03x: ",j);
5557
                for (i=0; i<16 && i<len; i++) {
5558
                    printk("%02x ",(u_char)skb->data[i+j]);
5559
                }
5560
                printk("\n");
5561
            }
5562
        }
5563
    }
5564
 
5565
    return;
5566
}
5567
 
5568
/*
5569
** Perform IOCTL call functions here. Some are privileged operations and the
5570
** effective uid is checked in those cases. In the normal course of events
5571
** this function is only used for my testing.
5572
*/
5573
static int
5574
de4x5_ioctl(struct device *dev, struct ifreq *rq, int cmd)
5575
{
5576
    struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5577
    struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_data;
5578
    u_long iobase = dev->base_addr;
5579
    int i, j, status = 0;
5580
    s32 omr;
5581
    union {
5582
        u8  addr[144];
5583
        u16 sval[72];
5584
        u32 lval[36];
5585
    } tmp;
5586
 
5587
    switch(ioc->cmd) {
5588
    case DE4X5_GET_HWADDR:           /* Get the hardware address */
5589
        ioc->len = ETH_ALEN;
5590
        status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len);
5591
        if (status)
5592
            break;
5593
        for (i=0; i<ETH_ALEN; i++) {
5594
            tmp.addr[i] = dev->dev_addr[i];
5595
        }
5596
        copy_to_user(ioc->data, tmp.addr, ioc->len);
5597
 
5598
        break;
5599
    case DE4X5_SET_HWADDR:           /* Set the hardware address */
5600
        status = verify_area(VERIFY_READ, (void *)ioc->data, ETH_ALEN);
5601
        if (status)
5602
            break;
5603
        status = -EPERM;
5604
        if (!suser())
5605
            break;
5606
        status = 0;
5607
        copy_from_user(tmp.addr, ioc->data, ETH_ALEN);
5608
        for (i=0; i<ETH_ALEN; i++) {
5609
            dev->dev_addr[i] = tmp.addr[i];
5610
        }
5611
        build_setup_frame(dev, PHYS_ADDR_ONLY);
5612
        /* Set up the descriptor and give ownership to the card */
5613
        while (test_and_set_bit(0, (void *)&dev->tbusy) != 0);
5614
        load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5615
                                                        SETUP_FRAME_LEN, NULL);
5616
        lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5617
        outl(POLL_DEMAND, DE4X5_TPD);                /* Start the TX */
5618
        dev->tbusy = 0;                              /* Unlock the TX ring */
5619
 
5620
        break;
5621
    case DE4X5_SET_PROM:             /* Set Promiscuous Mode */
5622
        if (suser()) {
5623
            omr = inl(DE4X5_OMR);
5624
            omr |= OMR_PR;
5625
            outl(omr, DE4X5_OMR);
5626
            dev->flags |= IFF_PROMISC;
5627
        } else {
5628
            status = -EPERM;
5629
        }
5630
 
5631
        break;
5632
    case DE4X5_CLR_PROM:             /* Clear Promiscuous Mode */
5633
        if (suser()) {
5634
            omr = inl(DE4X5_OMR);
5635
            omr &= ~OMR_PR;
5636
            outb(omr, DE4X5_OMR);
5637
            dev->flags &= ~IFF_PROMISC;
5638
        } else {
5639
            status = -EPERM;
5640
        }
5641
 
5642
        break;
5643
    case DE4X5_SAY_BOO:              /* Say "Boo!" to the kernel log file */
5644
        printk("%s: Boo!\n", dev->name);
5645
 
5646
        break;
5647
    case DE4X5_MCA_EN:               /* Enable pass all multicast addressing */
5648
        if (suser()) {
5649
            omr = inl(DE4X5_OMR);
5650
            omr |= OMR_PM;
5651
            outl(omr, DE4X5_OMR);
5652
        } else {
5653
            status = -EPERM;
5654
        }
5655
 
5656
        break;
5657
    case DE4X5_GET_STATS:            /* Get the driver statistics */
5658
        ioc->len = sizeof(lp->pktStats);
5659
        status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len);
5660
        if (status)
5661
            break;
5662
 
5663
        cli();
5664
        copy_to_user(ioc->data, &lp->pktStats, ioc->len);
5665
        sti();
5666
 
5667
        break;
5668
    case DE4X5_CLR_STATS:            /* Zero out the driver statistics */
5669
        if (suser()) {
5670
            cli();
5671
            memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5672
            sti();
5673
        } else {
5674
            status = -EPERM;
5675
        }
5676
 
5677
        break;
5678
    case DE4X5_GET_OMR:              /* Get the OMR Register contents */
5679
        tmp.addr[0] = inl(DE4X5_OMR);
5680
        if (!(status = verify_area(VERIFY_WRITE, (void *)ioc->data, 1))) {
5681
            copy_to_user(ioc->data, tmp.addr, 1);
5682
        }
5683
 
5684
        break;
5685
    case DE4X5_SET_OMR:              /* Set the OMR Register contents */
5686
        if (suser()) {
5687
            if (!(status = verify_area(VERIFY_READ, (void *)ioc->data, 1))) {
5688
                copy_from_user(tmp.addr, ioc->data, 1);
5689
                outl(tmp.addr[0], DE4X5_OMR);
5690
            }
5691
        } else {
5692
            status = -EPERM;
5693
        }
5694
 
5695
        break;
5696
    case DE4X5_GET_REG:              /* Get the DE4X5 Registers */
5697
        j = 0;
5698
        tmp.lval[0] = inl(DE4X5_STS); j+=4;
5699
        tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5700
        tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5701
        tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5702
        tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5703
        tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5704
        tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5705
        tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5706
        ioc->len = j;
5707
        if (!(status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len))) {
5708
            copy_to_user(ioc->data, tmp.addr, ioc->len);
5709
        }
5710
        break;
5711
 
5712
#define DE4X5_DUMP              0x0f /* Dump the DE4X5 Status */
5713
/*
5714
      case DE4X5_DUMP:
5715
        j = 0;
5716
        tmp.addr[j++] = dev->irq;
5717
        for (i=0; i<ETH_ALEN; i++) {
5718
            tmp.addr[j++] = dev->dev_addr[i];
5719
        }
5720
        tmp.addr[j++] = lp->rxRingSize;
5721
        tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5722
        tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5723
 
5724
        for (i=0;i<lp->rxRingSize-1;i++){
5725
            if (i < 3) {
5726
                tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5727
            }
5728
        }
5729
        tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5730
        for (i=0;i<lp->txRingSize-1;i++){
5731
            if (i < 3) {
5732
                tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5733
            }
5734
        }
5735
        tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5736
 
5737
        for (i=0;i<lp->rxRingSize-1;i++){
5738
            if (i < 3) {
5739
                tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5740
            }
5741
        }
5742
        tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5743
        for (i=0;i<lp->txRingSize-1;i++){
5744
            if (i < 3) {
5745
                tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5746
            }
5747
        }
5748
        tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5749
 
5750
        for (i=0;i<lp->rxRingSize;i++){
5751
            tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5752
        }
5753
        for (i=0;i<lp->txRingSize;i++){
5754
            tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5755
        }
5756
 
5757
        tmp.lval[j>>2] = inl(DE4X5_BMR);  j+=4;
5758
        tmp.lval[j>>2] = inl(DE4X5_TPD);  j+=4;
5759
        tmp.lval[j>>2] = inl(DE4X5_RPD);  j+=4;
5760
        tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5761
        tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5762
        tmp.lval[j>>2] = inl(DE4X5_STS);  j+=4;
5763
        tmp.lval[j>>2] = inl(DE4X5_OMR);  j+=4;
5764
        tmp.lval[j>>2] = inl(DE4X5_IMR);  j+=4;
5765
        tmp.lval[j>>2] = lp->chipset; j+=4;
5766
        if (lp->chipset == DC21140) {
5767
            tmp.lval[j>>2] = gep_rd(dev);  j+=4;
5768
        } else {
5769
            tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5770
            tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5771
            tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5772
            tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5773
        }
5774
        tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5775
        if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5776
            tmp.lval[j>>2] = lp->active; j+=4;
5777
            tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5778
            tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5779
            tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5780
            tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5781
            if (lp->phy[lp->active].id != BROADCOM_T4) {
5782
                tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5783
                tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5784
            }
5785
            tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5786
            if (lp->phy[lp->active].id != BROADCOM_T4) {
5787
                tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5788
                tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5789
            } else {
5790
                tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5791
            }
5792
        }
5793
 
5794
        tmp.addr[j++] = lp->txRingSize;
5795
        tmp.addr[j++] = dev->tbusy;
5796
 
5797
        ioc->len = j;
5798
        if (!(status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len))) {
5799
            copy_to_user(ioc->data, tmp.addr, ioc->len);
5800
        }
5801
 
5802
        break;
5803
*/
5804
    default:
5805
        status = -EOPNOTSUPP;
5806
    }
5807
 
5808
    return status;
5809
}
5810
 
5811
#ifdef MODULE
5812
/*
5813
** Note now that module autoprobing is allowed under EISA and PCI. The
5814
** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
5815
** to "do the right thing".
5816
*/
5817
#define LP(a) ((struct de4x5_private *)(a))
5818
static struct device *mdev = NULL;
5819
static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED        */
5820
#if LINUX_VERSION_CODE >= LinuxVersionCode(2,1,0)
5821
MODULE_PARM(io, "i");
5822
#endif /* LINUX_VERSION_CODE */
5823
 
5824
int
5825
init_module(void)
5826
{
5827
    int i, num, status = -EIO;
5828
    struct device *p;
5829
 
5830
    num = count_adapters();
5831
 
5832
    for (i=0; i<num; i++) {
5833
        if ((p = insert_device(NULL, io, de4x5_probe)) == NULL)
5834
            return -ENOMEM;
5835
 
5836
        if (!mdev) mdev = p;
5837
 
5838
        if (register_netdev(p) != 0) {
5839
            struct de4x5_private *lp = (struct de4x5_private *)p->priv;
5840
            if (lp) {
5841
                release_region(p->base_addr, (lp->bus == PCI ?
5842
                                              DE4X5_PCI_TOTAL_SIZE :
5843
                                              DE4X5_EISA_TOTAL_SIZE));
5844
            }
5845
            kfree(p);
5846
        } else {
5847
            status = 0;                 /* At least one adapter will work */
5848
            lastModule = p;
5849
        }
5850
    }
5851
 
5852
    return status;
5853
}
5854
 
5855
void
5856
cleanup_module(void)
5857
{
5858
    while (mdev != NULL) {
5859
        mdev = unlink_modules(mdev);
5860
    }
5861
 
5862
    return;
5863
}
5864
 
5865
static struct device *
5866
unlink_modules(struct device *p)
5867
{
5868
    struct device *next = NULL;
5869
 
5870
    if (p->priv) {                          /* Private areas allocated?  */
5871
        struct de4x5_private *lp = (struct de4x5_private *)p->priv;
5872
 
5873
        next = lp->next_module;
5874
        if (lp->cache.buf) {                /* MAC buffers allocated?    */
5875
            kfree(lp->cache.buf);           /* Free the MAC buffers      */
5876
        }
5877
        kfree(lp->cache.priv);              /* Free the private area     */
5878
        release_region(p->base_addr, (lp->bus == PCI ?
5879
                                      DE4X5_PCI_TOTAL_SIZE :
5880
                                      DE4X5_EISA_TOTAL_SIZE));
5881
    }
5882
    unregister_netdev(p);
5883
    kfree(p);                               /* Free the device structure */
5884
 
5885
    return next;
5886
}
5887
 
5888
static int
5889
count_adapters(void)
5890
{
5891
    int i, j=0;
5892
    u_char pb, dev_fn, dev_num;
5893
    u_short dev_id, vendor;
5894
    u_int class = DE4X5_CLASS_CODE;
5895
    u_int device;
5896
 
5897
#if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
5898
    char name[DE4X5_STRLEN];
5899
    u_long iobase = 0x1000;
5900
 
5901
    for (i=1; i<MAX_EISA_SLOTS; i++, iobase+=EISA_SLOT_INC) {
5902
        if (EISA_signature(name, EISA_ID)) j++;
5903
    }
5904
#endif
5905
    if (!pcibios_present()) return j;
5906
 
5907
    for (i=0;
5908
         (pcibios_find_class(class, i, &pb, &dev_fn)!= PCIBIOS_DEVICE_NOT_FOUND);
5909
         i++) {
5910
        dev_num = PCI_SLOT(dev_fn);
5911
        device = 0;
5912
        pcibios_read_config_word(pb, PCI_DEVICE, PCI_VENDOR_ID, &vendor);
5913
        pcibios_read_config_word(pb, PCI_DEVICE, PCI_DEVICE_ID, &dev_id);
5914
        device = dev_id;
5915
        device <<= 8;
5916
        if (is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x) j++;
5917
    }
5918
 
5919
    return j;
5920
}
5921
 
5922
/*
5923
** If at end of eth device list and can't use current entry, malloc
5924
** one up. If memory could not be allocated, print an error message.
5925
*/
5926
__initfunc(static struct device *
5927
insert_device(struct device *dev, u_long iobase, int (*init)(struct device *)))
5928
{
5929
    struct device *new;
5930
 
5931
    new = (struct device *)kmalloc(sizeof(struct device)+8, GFP_KERNEL);
5932
    if (new == NULL) {
5933
        printk("de4x5.c: Device not initialised, insufficient memory\n");
5934
        return NULL;
5935
    } else {
5936
        memset((char *)new, 0, sizeof(struct device)+8);
5937
        new->name = (char *)(new + 1);
5938
        new->base_addr = iobase;       /* assign the io address */
5939
        new->init = init;              /* initialisation routine */
5940
    }
5941
 
5942
    return new;
5943
}
5944
 
5945
#endif /* MODULE */
5946
 
5947
 
5948
/*
5949
 * Local variables:
5950
 *  compile-command: "gcc -D__KERNEL__ -I/linux/include -Wall -Wstrict-prototypes -fomit-frame-pointer -fno-strength-reduce -malign-loops=2 -malign-jumps=2 -malign-functions=2 -O2 -m486 -c de4x5.c"
5951
 *
5952
 *  compile-command: "gcc -D__KERNEL__ -DMODULE -I/linux/include -Wall -Wstrict-prototypes -fomit-frame-pointer -fno-strength-reduce -malign-loops=2 -malign-jumps=2 -malign-functions=2 -O2 -m486 -c de4x5.c"
5953
 * End:
5954
 */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.