URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [drivers/] [net/] [sk_g16.h] - Blame information for rev 1772

Go to most recent revision | Details | Compare with Previous | View Log


/*-
 *
 * This software may be used and distributed according to the terms
 * of the GNU Public License, incorporated herein by reference.
 *
 * Module         : sk_g16.h
 * Version        : $Revision: 1.1 $
 *
 * Author         : M.Hipp (mhipp@student.uni-tuebingen.de)
 * changes by     : Patrick J.D. Weichmann
 *
 * Date Created   : 94/05/25
 *
 * Description    : In here are all necessary definitions of
 *                  the am7990 (LANCE) chip used for writing a
 *                  network device driver which uses this chip
 *
 * $Log: not supported by cvs2svn $
 * Revision 1.1.1.1  2001/09/10 07:44:25  simons
 * Initial import
 *
 * Revision 1.1.1.1  2001/07/02 17:58:22  simons
 * Initial revision
 *
-*/
 
#ifndef SK_G16_H
 
#define SK_G16_H
 
 
/*
 *      Control and Status Register 0 (CSR0) bit definitions
 *
 * (R=Readable) (W=Writeable) (S=Set on write) (C-Clear on write)
 *
 */
 
#define CSR0_ERR        0x8000  /* Error summary (R) */
#define CSR0_BABL       0x4000  /* Babble transmitter timeout error (RC) */
#define CSR0_CERR       0x2000  /* Collision Error (RC) */
#define CSR0_MISS       0x1000  /* Missed packet (RC) */
#define CSR0_MERR       0x0800  /* Memory Error  (RC) */ 
#define CSR0_RINT       0x0400  /* Receiver Interrupt (RC) */
#define CSR0_TINT       0x0200  /* Transmit Interrupt (RC) */ 
#define CSR0_IDON       0x0100  /* Initialization Done (RC) */
#define CSR0_INTR       0x0080  /* Interrupt Flag (R) */
#define CSR0_INEA       0x0040  /* Interrupt Enable (RW) */
#define CSR0_RXON       0x0020  /* Receiver on (R) */
#define CSR0_TXON       0x0010  /* Transmitter on (R) */
#define CSR0_TDMD       0x0008  /* Transmit Demand (RS) */
#define CSR0_STOP       0x0004  /* Stop (RS) */
#define CSR0_STRT       0x0002  /* Start (RS) */
#define CSR0_INIT       0x0001  /* Initialize (RS) */
 
#define CSR0_CLRALL     0x7f00  /* mask for all clearable bits */
 
/*
 *    Control and Status Register 3 (CSR3) bit definitions
 *
 */
 
#define CSR3_BSWAP      0x0004  /* Byte Swap (RW) */
#define CSR3_ACON       0x0002  /* ALE Control (RW) */
#define CSR3_BCON       0x0001  /* Byte Control (RW) */
 
/*
 *      Initialization Block Mode operation Bit Definitions.
 */
 
#define MODE_PROM       0x8000  /* Promiscuous Mode */
#define MODE_INTL       0x0040  /* Internal Loopback */
#define MODE_DRTY       0x0020  /* Disable Retry */ 
#define MODE_COLL       0x0010  /* Force Collision */
#define MODE_DTCR       0x0008  /* Disable Transmit CRC) */
#define MODE_LOOP       0x0004  /* Loopback */
#define MODE_DTX        0x0002  /* Disable the Transmitter */ 
#define MODE_DRX        0x0001  /* Disable the Receiver */
 
#define MODE_NORMAL     0x0000  /* Normal operation mode */
 
/*
 *      Receive message descriptor status bit definitions.
 */
 
#define RX_OWN          0x80    /* Owner bit 0 = host, 1 = lance */
#define RX_ERR          0x40    /* Error Summary */
#define RX_FRAM         0x20    /* Framing Error */
#define RX_OFLO         0x10    /* Overflow Error */
#define RX_CRC          0x08    /* CRC Error */ 
#define RX_BUFF         0x04    /* Buffer Error */
#define RX_STP          0x02    /* Start of Packet */
#define RX_ENP          0x01    /* End of Packet */
 
 
/*
 *      Transmit message descriptor status bit definitions.
 */
 
#define TX_OWN          0x80    /* Owner bit 0 = host, 1 = lance */
#define TX_ERR          0x40    /* Error Summary */
#define TX_MORE         0x10    /* More the 1 retry needed to Xmit */
#define TX_ONE          0x08    /* One retry needed to Xmit */
#define TX_DEF          0x04    /* Deferred */
#define TX_STP          0x02    /* Start of Packet */
#define TX_ENP          0x01    /* End of Packet */
 
/*
 *      Transmit status (2) (valid if TX_ERR == 1)
 */
 
#define TX_BUFF         0x8000  /* Buffering error (no ENP) */
#define TX_UFLO         0x4000  /* Underflow (late memory) */
#define TX_LCOL         0x1000  /* Late collision */
#define TX_LCAR         0x0400  /* Loss of Carrier */
#define TX_RTRY         0x0200  /* Failed after 16 retransmissions  */
#define TX_TDR          0x003f  /* Time-domain-reflectometer-value */
 
 
/*
 * Structures used for Communication with the LANCE
 */
 
/* LANCE Initialize Block */
 
struct init_block
{
  unsigned short mode;     /* Mode Register */
  unsigned char  paddr[6]; /* Physical Address (MAC) */
  unsigned char  laddr[8]; /* Logical Filter Address (not used) */
  unsigned int   rdrp;     /* Receive Descriptor Ring pointer */
  unsigned int   tdrp;     /* Transmit Descriptor Ring pointer */
};
 
 
/* Receive Message Descriptor Entry */
 
struct rmd
{
  union
  {
    unsigned long buffer;     /* Address of buffer */
    struct
    {
      unsigned char unused[3];
      unsigned volatile char status;   /* Status Bits */
    } s;
  } u;
  volatile short blen;        /* Buffer Length (two's complement) */
  unsigned short mlen;        /* Message Byte Count */
};
 
 
/* Transmit Message Descriptor Entry */
 
struct tmd
{
  union
  {
    unsigned long  buffer;    /* Address of buffer */
    struct
    {
      unsigned char unused[3];
      unsigned volatile char status;   /* Status Bits */
    } s;
  } u;
  unsigned short blen;             /* Buffer Length (two's complement) */
  unsigned volatile short status2; /* Error Status Bits */
};
 
#endif /* End of SK_G16_H */

Line No.	Rev	Author	Line
1	1626	jcastillo	`/*-`
2			`*`
3			`* This software may be used and distributed according to the terms`
4			`* of the GNU Public License, incorporated herein by reference.`
5			`*`
6			`* Module : sk_g16.h`
7			`* Version : $Revision: 1.1 $`
8			`*`
9			`* Author : M.Hipp (mhipp@student.uni-tuebingen.de)`
10			`* changes by : Patrick J.D. Weichmann`
11			`*`
12			`* Date Created : 94/05/25`
13			`*`
14			`* Description : In here are all necessary definitions of`
15			`* the am7990 (LANCE) chip used for writing a`
16			`* network device driver which uses this chip`
17			`*`
18			`* $Log: not supported by cvs2svn $`
19			`* Revision 1.1.1.1 2001/09/10 07:44:25 simons`
20			`* Initial import`
21			`*`
22			`* Revision 1.1.1.1 2001/07/02 17:58:22 simons`
23			`* Initial revision`
24			`*`
25			`-*/`
26
27			`#ifndef SK_G16_H`
28
29			`#define SK_G16_H`
30
31
32			`/*`
33			`* Control and Status Register 0 (CSR0) bit definitions`
34			`*`
35			`* (R=Readable) (W=Writeable) (S=Set on write) (C-Clear on write)`
36			`*`
37			`*/`
38
39			`#define CSR0_ERR 0x8000 /* Error summary (R) */`
40			`#define CSR0_BABL 0x4000 /* Babble transmitter timeout error (RC) */`
41			`#define CSR0_CERR 0x2000 /* Collision Error (RC) */`
42			`#define CSR0_MISS 0x1000 /* Missed packet (RC) */`
43			`#define CSR0_MERR 0x0800 /* Memory Error (RC) */`
44			`#define CSR0_RINT 0x0400 /* Receiver Interrupt (RC) */`
45			`#define CSR0_TINT 0x0200 /* Transmit Interrupt (RC) */`
46			`#define CSR0_IDON 0x0100 /* Initialization Done (RC) */`
47			`#define CSR0_INTR 0x0080 /* Interrupt Flag (R) */`
48			`#define CSR0_INEA 0x0040 /* Interrupt Enable (RW) */`
49			`#define CSR0_RXON 0x0020 /* Receiver on (R) */`
50			`#define CSR0_TXON 0x0010 /* Transmitter on (R) */`
51			`#define CSR0_TDMD 0x0008 /* Transmit Demand (RS) */`
52			`#define CSR0_STOP 0x0004 /* Stop (RS) */`
53			`#define CSR0_STRT 0x0002 /* Start (RS) */`
54			`#define CSR0_INIT 0x0001 /* Initialize (RS) */`
55
56			`#define CSR0_CLRALL 0x7f00 /* mask for all clearable bits */`
57
58			`/*`
59			`* Control and Status Register 3 (CSR3) bit definitions`
60			`*`
61			`*/`
62
63			`#define CSR3_BSWAP 0x0004 /* Byte Swap (RW) */`
64			`#define CSR3_ACON 0x0002 /* ALE Control (RW) */`
65			`#define CSR3_BCON 0x0001 /* Byte Control (RW) */`
66
67			`/*`
68			`* Initialization Block Mode operation Bit Definitions.`
69			`*/`
70
71			`#define MODE_PROM 0x8000 /* Promiscuous Mode */`
72			`#define MODE_INTL 0x0040 /* Internal Loopback */`
73			`#define MODE_DRTY 0x0020 /* Disable Retry */`
74			`#define MODE_COLL 0x0010 /* Force Collision */`
75			`#define MODE_DTCR 0x0008 /* Disable Transmit CRC) */`
76			`#define MODE_LOOP 0x0004 /* Loopback */`
77			`#define MODE_DTX 0x0002 /* Disable the Transmitter */`
78			`#define MODE_DRX 0x0001 /* Disable the Receiver */`
79
80			`#define MODE_NORMAL 0x0000 /* Normal operation mode */`
81
82			`/*`
83			`* Receive message descriptor status bit definitions.`
84			`*/`
85
86			`#define RX_OWN 0x80 /* Owner bit 0 = host, 1 = lance */`
87			`#define RX_ERR 0x40 /* Error Summary */`
88			`#define RX_FRAM 0x20 /* Framing Error */`
89			`#define RX_OFLO 0x10 /* Overflow Error */`
90			`#define RX_CRC 0x08 /* CRC Error */`
91			`#define RX_BUFF 0x04 /* Buffer Error */`
92			`#define RX_STP 0x02 /* Start of Packet */`
93			`#define RX_ENP 0x01 /* End of Packet */`
94
95
96			`/*`
97			`* Transmit message descriptor status bit definitions.`
98			`*/`
99
100			`#define TX_OWN 0x80 /* Owner bit 0 = host, 1 = lance */`
101			`#define TX_ERR 0x40 /* Error Summary */`
102			`#define TX_MORE 0x10 /* More the 1 retry needed to Xmit */`
103			`#define TX_ONE 0x08 /* One retry needed to Xmit */`
104			`#define TX_DEF 0x04 /* Deferred */`
105			`#define TX_STP 0x02 /* Start of Packet */`
106			`#define TX_ENP 0x01 /* End of Packet */`
107
108			`/*`
109			`* Transmit status (2) (valid if TX_ERR == 1)`
110			`*/`
111
112			`#define TX_BUFF 0x8000 /* Buffering error (no ENP) */`
113			`#define TX_UFLO 0x4000 /* Underflow (late memory) */`
114			`#define TX_LCOL 0x1000 /* Late collision */`
115			`#define TX_LCAR 0x0400 /* Loss of Carrier */`
116			`#define TX_RTRY 0x0200 /* Failed after 16 retransmissions */`
117			`#define TX_TDR 0x003f /* Time-domain-reflectometer-value */`
118
119
120			`/*`
121			`* Structures used for Communication with the LANCE`
122			`*/`
123
124			`/* LANCE Initialize Block */`
125
126			`struct init_block`
127			`{`
128			`unsigned short mode; /* Mode Register */`
129			`unsigned char paddr[6]; /* Physical Address (MAC) */`
130			`unsigned char laddr[8]; /* Logical Filter Address (not used) */`
131			`unsigned int rdrp; /* Receive Descriptor Ring pointer */`
132			`unsigned int tdrp; /* Transmit Descriptor Ring pointer */`
133			`};`
134
135
136			`/* Receive Message Descriptor Entry */`
137
138			`struct rmd`
139			`{`
140			`union`
141			`{`
142			`unsigned long buffer; /* Address of buffer */`
143			`struct`
144			`{`
145			`unsigned char unused[3];`
146			`unsigned volatile char status; /* Status Bits */`
147			`} s;`
148			`} u;`
149			`volatile short blen; /* Buffer Length (two's complement) */`
150			`unsigned short mlen; /* Message Byte Count */`
151			`};`
152
153
154			`/* Transmit Message Descriptor Entry */`
155
156			`struct tmd`
157			`{`
158			`union`
159			`{`
160			`unsigned long buffer; /* Address of buffer */`
161			`struct`
162			`{`
163			`unsigned char unused[3];`
164			`unsigned volatile char status; /* Status Bits */`
165			`} s;`
166			`} u;`
167			`unsigned short blen; /* Buffer Length (two's complement) */`
168			`unsigned volatile short status2; /* Error Status Bits */`
169			`};`
170
171			`#endif /* End of SK_G16_H */`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [drivers/] [net/] [sk_g16.h] - Blame information for rev 1772