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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [drivers/] [net/] [smc91111.c] - Blame information for rev 1772

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1 1626 jcastillo
/*------------------------------------------------------------------------
2
 . smc91111.c
3
 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
4
 .
5
 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
6
 .       Developed by Simple Network Magic Corporation (SNMC)
7
 . Copyright (C) 1996 by Erik Stahlman (ES)
8
 .
9
 . This program is free software; you can redistribute it and/or modify
10
 . it under the terms of the GNU General Public License as published by
11
 . the Free Software Foundation; either version 2 of the License, or
12
 . (at your option) any later version.
13
 .
14
 . This program is distributed in the hope that it will be useful,
15
 . but WITHOUT ANY WARRANTY; without even the implied warranty of
16
 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
 . GNU General Public License for more details.
18
 .
19
 . You should have received a copy of the GNU General Public License
20
 . along with this program; if not, write to the Free Software
21
 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
22
 .
23
 . Information contained in this file was obtained from the LAN91C111
24
 . manual from SMC.  To get a copy, if you really want one, you can find
25
 . information under www.smsc.com.
26
 .
27
 .
28
 . "Features" of the SMC chip:
29
 .   Integrated PHY/MAC for 10/100BaseT Operation
30
 .   Supports internal and external MII
31
 .   Integrated 8K packet memory
32
 .   EEPROM interface for configuration
33
 .
34
 . Arguments:
35
 .      io      = for the base address
36
 .      irq     = for the IRQ
37
 .      nowait  = 0 for normal wait states, 1 eliminates additional wait states
38
 .
39
 . author:
40
 .      Erik Stahlman                           ( erik@vt.edu )
41
 .      Daris A Nevil                           ( dnevil@snmc.com )
42
 .      Kendrick Hamilton                       ( hamilton@sedsystems.ca )
43
 .
44
 .
45
 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
46
 .
47
 . Sources:
48
 .    o   SMSC LAN91C111 databook (www.smsc.com)
49
 .    o   smc9194.c by Erik Stahlman
50
 .    o   skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
51
 .
52
 . History:
53
 .      04/25/01  Daris A Nevil  Initial public release through SMSC
54
 .      03/16/01  Daris A Nevil  Modified smc9194.c for use with LAN91C111
55
 .      03/06/02  Greg Ungerer   Code to support ColdFire (M5249C3 board)
56
 ----------------------------------------------------------------------------*/
57
 
58
// Use power-down feature of the chip
59
#define POWER_DOWN   0
60
#define NO_AUTOPROBE 1
61
 
62
//Should be part of the automatic configuration
63
#define CONFIG_SMC91C111_EXTRA_DELAY 1
64
// Do you want to use 32 bit xfers?  This should work on all chips, as
65
// the chipset is designed to accommodate them.
66
 
67
/*OpenRISC 1200 uses 16 bits*/
68
#undef CONFIG_SMC91C111_32_BIT 
69
 
70
#if defined(CONFIG_SMC91C111_EXTRA_DELAY)
71
#define SMC91C111_EXTRA_DELAY 20
72
#endif
73
 
74
static const char version[] =
75
    "smc91111.c:v1.2 01/29/02 by ???\n";
76
 
77
 
78
#include <linux/kernel.h>
79
#include <linux/sched.h>
80
#include <linux/types.h>
81
#include <linux/fcntl.h>
82
#include <linux/interrupt.h>
83
#include <linux/ptrace.h>
84
#include <linux/ioport.h>
85
#include <linux/in.h>
86
#include <linux/malloc.h>
87
#include <linux/string.h>
88
#include <asm/bitops.h>
89
 
90
#include <asm/io.h>
91
 
92
#include <asm/irq.h>
93
 
94
#include <linux/errno.h>
95
#include <linux/delay.h>
96
 
97
#include <linux/netdevice.h>
98
#include <linux/etherdevice.h>
99
#include <linux/skbuff.h>
100
 
101
//#define CONFIG_SYSCTL 1
102
 
103
#ifdef SMC_DEBUG
104
#undef SMC_DEBUG
105
#endif
106
 
107
#ifdef CONFIG_SYSCTL
108
#include <linux/proc_fs.h>
109
#include <linux/sysctl.h>
110
#endif
111
 
112
#include "smc91111.h"
113
 
114
//------------------------------------------------------------------------
115
//
116
// Configuration options, for the experienced user to change.
117
//
118
//------------------------------------------------------------------------
119
 
120
 
121
/*
122
 .the LAN91C111 can be at any of the following port addresses.  To change,
123
 .for a slightly different card, you can add it to the array.  Keep in
124
 .mind that the array must end in zero.
125
*/
126
 
127
static unsigned long int smc_portlist[] =
128
   { 0x92000000, 0};
129
 
130
#define SWAP16(x)  ((((x) & 0x00ff) << 8) | ( (x) >> 8))
131
 
132
/*
133
 . Wait time for memory to be free.  This probably shouldn't be
134
 . tuned that much, as waiting for this means nothing else happens
135
 . in the system
136
*/
137
#define MEMORY_WAIT_TIME 16
138
 
139
/*
140
 . DEBUGGING LEVELS
141
 .
142
 . 0 for normal operation
143
 . 1 for slightly more details
144
 . >2 for various levels of increasingly useless information
145
 .    2 for interrupt tracking, status flags
146
 .    3 for packet info
147
 .    4 for complete packet dumps
148
*/
149
#define SMC_DEBUG 0 // Must be defined in makefile
150
 
151
#if (SMC_DEBUG > 2 )
152
#define PRINTK3(args...) printk(args)
153
#else
154
#define PRINTK3(args...)
155
#endif
156
 
157
#if SMC_DEBUG > 1
158
#define PRINTK2(args...) printk(args)
159
#else
160
#define PRINTK2(args...)
161
#endif
162
 
163
#ifdef SMC_DEBUG
164
#define PRINTK(args...) printk(args)
165
#else
166
#define PRINTK(args...)
167
#endif
168
 
169
 
170
/*------------------------------------------------------------------------
171
 .
172
 . The internal workings of the driver.  If you are changing anything
173
 . here with the SMC stuff, you should have the datasheet and know
174
 . what you are doing.
175
 .
176
 -------------------------------------------------------------------------*/
177
#define CARDNAME "LAN91C111"
178
 
179
// Memory sizing constant
180
#define LAN91C111_MEMORY_MULTIPLIER     (1024*2)
181
 
182
/* store this information for the driver.. */
183
struct smc_local {
184
 
185
        // these are things that the kernel wants me to keep, so users
186
        // can find out semi-useless statistics of how well the card is
187
        // performing
188
        //struct net_device_stats stats;
189
        struct enet_statistics stats;
190
 
191
        // If I have to wait until memory is available to send
192
        // a packet, I will store the skbuff here, until I get the
193
        // desired memory.  Then, I'll send it out and free it.
194
        struct sk_buff * saved_skb;
195
 
196
        // This keeps track of how many packets that I have
197
        // sent out.  When an TX_EMPTY interrupt comes, I know
198
        // that all of these have been sent.
199
        int     packets_waiting;
200
 
201
        // Set to true during the auto-negotiation sequence
202
        int     autoneg_active;
203
 
204
        // Address of our PHY port
205
        word    phyaddr;
206
 
207
        // Type of PHY
208
        word    phytype;
209
 
210
        // Last contents of PHY Register 18
211
        word    lastPhy18;
212
 
213
        // Contains the current active transmission mode
214
        word    tcr_cur_mode;
215
 
216
        // Contains the current active receive mode
217
        word    rcr_cur_mode;
218
 
219
        // Contains the current active receive/phy mode
220
        word    rpc_cur_mode;
221
 
222
 
223
#ifdef CONFIG_SYSCTL
224
 
225
        // Root directory /proc/sys/dev
226
        // Second entry must be null to terminate the table
227
        ctl_table root_table[2];
228
 
229
        // Directory for this device /proc/sys/dev/ethX
230
        // Again the second entry must be zero to terminate
231
        ctl_table eth_table[2];
232
 
233
        // This is the parameters (file) table
234
        ctl_table param_table[CTL_SMC_LAST_ENTRY];
235
 
236
        // Saves the sysctl header returned by register_sysctl_table()
237
        // we send this to unregister_sysctl_table()
238
        struct ctl_table_header *sysctl_header;
239
 
240
        // Parameter variables (files) go here
241
        char ctl_info[1024];
242
        int ctl_swfdup;
243
        int ctl_ephloop;
244
        int ctl_miiop;
245
        int ctl_autoneg;
246
        int ctl_rfduplx;
247
        int ctl_rspeed;
248
        int ctl_afduplx;
249
        int ctl_aspeed;
250
        int ctl_lnkfail;
251
        int ctl_forcol;
252
        int ctl_filtcar;
253
        int ctl_freemem;
254
        int ctl_totmem;
255
        int ctl_leda;
256
        int ctl_ledb;
257
        int ctl_chiprev;
258
#ifdef SMC_DEBUG
259
        int ctl_reg_bsr;
260
        int ctl_reg_tcr;
261
        int ctl_reg_esr;
262
        int ctl_reg_rcr;
263
        int ctl_reg_ctrr;
264
        int ctl_reg_mir;
265
        int ctl_reg_rpcr;
266
        int ctl_reg_cfgr;
267
        int ctl_reg_bar;
268
        int ctl_reg_iar0;
269
        int ctl_reg_iar1;
270
        int ctl_reg_iar2;
271
        int ctl_reg_gpr;
272
        int ctl_reg_ctlr;
273
        int ctl_reg_mcr;
274
        int ctl_reg_pnr;
275
        int ctl_reg_fpr;
276
        int ctl_reg_ptr;
277
        int ctl_reg_dr;
278
        int ctl_reg_isr;
279
        int ctl_reg_mtr1;
280
        int ctl_reg_mtr2;
281
        int ctl_reg_mtr3;
282
        int ctl_reg_mtr4;
283
        int ctl_reg_miir;
284
        int ctl_reg_revr;
285
        int ctl_reg_ercvr;
286
        int ctl_reg_extr;
287
        int ctl_phy_ctrl;
288
        int ctl_phy_stat;
289
        int ctl_phy_id1;
290
        int ctl_phy_id2;
291
        int ctl_phy_adc;
292
        int ctl_phy_remc;
293
        int ctl_phy_cfg1;
294
        int ctl_phy_cfg2;
295
        int ctl_phy_int;
296
        int ctl_phy_mask;
297
#endif // SMC_DEBUG
298
 
299
 
300
#endif // CONFIG_SYSCTL
301
 
302
};
303
 
304
 
305
/*-----------------------------------------------------------------
306
 .
307
 .  The driver can be entered at any of the following entry points.
308
 .
309
 .------------------------------------------------------------------  */
310
 
311
/*
312
 . This is called by  register_netdev().  It is responsible for
313
 . checking the portlist for the SMC9000 series chipset.  If it finds
314
 . one, then it will initialize the device, find the hardware information,
315
 . and sets up the appropriate device parameters.
316
 . NOTE: Interrupts are *OFF* when this procedure is called.
317
 .
318
 . NB:This shouldn't be static since it is referred to externally.
319
*/
320
int smc_init_91C111(struct device *dev);
321
 
322
/*
323
 . This is called by  unregister_netdev().  It is responsible for
324
 . cleaning up before the driver is finally unregistered and discarded.
325
*/
326
void smc_91C111_destructor(struct device *dev);
327
 
328
/*
329
 . The kernel calls this function when someone wants to use the device,
330
 . typically 'ifconfig ethX up'.
331
*/
332
static int smc_open(struct device *dev);
333
 
334
/*
335
 . This is called by the kernel to send a packet out into the net.  it's
336
 . responsible for doing a best-effort send, but if it's simply not possible
337
 . to send it, the packet gets dropped.
338
*/
339
static int smc_send_packet(struct sk_buff *skb, struct device *dev);
340
 
341
/*
342
 . This is called by the kernel in response to 'ifconfig ethX down'.  It
343
 . is responsible for cleaning up everything that the open routine
344
 . does, and maybe putting the card into a powerdown state.
345
*/
346
static int smc_close(struct device *dev);
347
 
348
/*
349
 . This routine allows the proc file system to query the driver's
350
 . statistics.
351
*/
352
static struct enet_statistics * smc_query_statistics( struct device *dev);
353
 
354
/*
355
 . Finally, a call to set promiscuous mode ( for TCPDUMP and related
356
 . programs ) and multicast modes.
357
*/
358
static void smc_set_multicast_list(struct device *dev);
359
 
360
/*
361
 . Configures the PHY through the MII Management interface
362
*/
363
static void smc_phy_configure(struct device* dev);
364
 
365
void smc_register_dump(const struct device *dev);
366
 
367
/*---------------------------------------------------------------
368
 .
369
 . Interrupt level calls..
370
 .
371
 ----------------------------------------------------------------*/
372
 
373
/*
374
 . Handles the actual interrupt
375
*/
376
static void smc_interrupt(int irq, void *, struct pt_regs *regs);
377
/*
378
 . This is a separate procedure to handle the receipt of a packet, to
379
 . leave the interrupt code looking slightly cleaner
380
*/
381
inline static void smc_rcv( struct device *dev );
382
/*
383
 . This handles a TX interrupt, which is only called when an error
384
 . relating to a packet is sent.
385
*/
386
inline static void smc_tx( struct device * dev );
387
 
388
/*
389
 . This handles interrupts generated from PHY register 18
390
*/
391
static void smc_phy_interrupt(struct device* dev);
392
 
393
/*
394
 ------------------------------------------------------------
395
 .
396
 . Internal routines
397
 .
398
 ------------------------------------------------------------
399
*/
400
 
401
/*
402
 . Test if a given location contains a chip, trying to cause as
403
 . little damage as possible if it's not a SMC chip.
404
*/
405
static int smc_probe( unsigned long ioaddr );
406
 
407
/*
408
 . this routine initializes the cards hardware, prints out the configuration
409
 . to the system log as well as the vanity message, and handles the setup
410
 . of a device parameter.
411
 . It will give an error if it can't initialize the card.
412
*/
413
static int smc_initcard( struct device *, unsigned long ioaddr );
414
static void smc_wait_ms(unsigned int ms);
415
 
416
/*
417
 . A rather simple routine to print out a packet for debugging purposes.
418
*/
419
#if SMC_DEBUG > 2
420
static void print_packet( byte *, int );
421
#endif
422
 
423
#define tx_done(dev) 1
424
 
425
/* this is called to actually send the packet to the chip */
426
static void smc_hardware_send_packet( struct device * dev );
427
 
428
/* Since I am not sure if I will have enough room in the chip's ram
429
 . to store the packet, I call this routine, which either sends it
430
 . now, or generates an interrupt when the card is ready for the
431
 . packet */
432
static int  smc_wait_to_send_packet( struct sk_buff * skb, struct device *dev );
433
 
434
/* this does a soft reset on the device */
435
static void smc_reset( struct device* dev );
436
 
437
/* Enable Interrupts, Receive, and Transmit */
438
static void smc_enable( struct device *dev );
439
 
440
/* this puts the device in an inactive state */
441
static void smc_shutdown( unsigned long ioaddr );
442
 
443
#ifndef NO_AUTOPROBE
444
/* This routine will find the IRQ of the driver if one is not
445
 . specified in the input to the device.  */
446
static int smc_findirq( unsigned long ioaddr );
447
#endif
448
 
449
/*
450
  this routine will set the hardware multicast table to the specified
451
  values given it by the higher level routines
452
*/
453
static void smc_setmulticast( unsigned long ioaddr, int count,
454
        struct dev_mc_list *  );
455
static int crc32( char *, int );
456
 
457
/* Routines to Read and Write the PHY Registers across the
458
   MII Management Interface
459
*/
460
 
461
static word smc_read_phy_register(unsigned long ioaddr, byte phyaddr,
462
        byte phyreg);
463
static void smc_write_phy_register(unsigned long ioaddr,
464
        byte phyaddr, byte phyreg, word phydata);
465
#if 0
466
//Interpret the read data, only understands some registers, more need to be
467
// added.
468
static word smc_interpret_phy_register(const struct device *dev,
469
        byte phyreg, word status);
470
#endif
471
 
472
/*
473
  Initilizes our device's sysctl proc filesystem
474
*/
475
 
476
#ifdef CONFIG_SYSCTL
477
static void smc_sysctl_register(struct device *dev);
478
static void smc_sysctl_unregister(struct device *dev);
479
#endif /* CONFIG_SYSCTL */ 
480
 
481
/*
482
 . Function: smc_reset( struct device* dev )
483
 . Purpose:
484
 .      This sets the SMC91111 chip to its normal state, hopefully from whatever
485
 .      mess that any other DOS driver has put it in.
486
 .
487
 . Maybe I should reset more registers to defaults in here?  SOFTRST  should
488
 . do that for me.
489
 .
490
 . Method:
491
 .      1.  send a SOFT RESET
492
 .      2.  wait for it to finish
493
 .      3.  enable autorelease mode
494
 .      4.  reset the memory management unit
495
 .      5.  clear all interrupts
496
 .
497
*/
498
static void smc_reset( struct device* dev )
499
{
500
        //struct smc_local *lp  = (struct smc_local *)dev->priv;
501
        unsigned long   ioaddr = dev->base_addr;
502
 
503
        PRINTK2("%s:smc_reset\n", dev->name);
504
 
505
        /* This resets the registers mostly to defaults, but doesn't
506
           affect EEPROM.  That seems unnecessary */
507
        SMC_SELECT_BANK( 0 );
508
        outw( RCR_SOFTRST, ioaddr + RCR_REG );
509
 
510
        /* Setup the Configuration Register */
511
        /* This is necessary because the CONFIG_REG is not affected */
512
        /* by a soft reset */
513
 
514
        SMC_SELECT_BANK( 1 );
515
        outw( CONFIG_DEFAULT, ioaddr + CONFIG_REG);
516
 
517
        /* Setup for fast accesses if requested */
518
        /* If the card/system can't handle it then there will */
519
        /* be no recovery except for a hard reset or power cycle */
520
 
521
        if (dev->dma)
522
                outw( inw( ioaddr + CONFIG_REG ) | CONFIG_NO_WAIT,
523
                        ioaddr + CONFIG_REG );
524
 
525
 
526
        SMC_SELECT_BANK( 0 );
527
 
528
        /* this should pause enough for the chip to be happy */
529
        mdelay(10);
530
 
531
        /* Disable transmit and receive functionality */
532
        outw( RCR_CLEAR, ioaddr + RCR_REG );
533
        outw( TCR_CLEAR, ioaddr + TCR_REG );
534
 
535
        /* set the control register to automatically
536
           release successfully transmitted packets, to make the best
537
           use out of our limited memory */
538
        SMC_SELECT_BANK( 1 );
539
        outw( inw( ioaddr + CTL_REG ) | CTL_AUTO_RELEASE , ioaddr + CTL_REG );
540
 
541
        /* Reset the MMU */
542
        SMC_SELECT_BANK( 2 );
543
        outw( MC_RESET, ioaddr + MMU_CMD_REG );
544
 
545
        /* Note:  It doesn't seem that waiting for the MMU busy is needed here,
546
           but this is a place where future chipsets _COULD_ break.  Be wary
547
           of issuing another MMU command right after this */
548
 
549
        /* Disable all interrupts */
550
        outb( 0, ioaddr + IM_REG );
551
 
552
}
553
 
554
/*
555
 . Function: smc_enable
556
 . Purpose: let the chip talk to the outside work
557
 . Method:
558
 .      1.  Enable the transmitter
559
 .      2.  Enable the receiver
560
 .      3.  Enable interrupts
561
*/
562
static void smc_enable( struct device *dev )
563
{
564
        unsigned long ioaddr    = dev->base_addr;
565
        struct smc_local *lp    = (struct smc_local *)dev->priv;
566
 
567
        PRINTK2("%s:smc_enable\n", dev->name);
568
 
569
        SMC_SELECT_BANK( 0 );
570
        /* see the header file for options in TCR/RCR DEFAULT*/
571
        outw( lp->tcr_cur_mode, ioaddr + TCR_REG );
572
        outw( lp->rcr_cur_mode, ioaddr + RCR_REG );
573
 
574
        /* now, enable interrupts */
575
        SMC_SELECT_BANK( 2 );
576
 
577
        outb( SMC_INTERRUPT_MASK, ioaddr + IM_REG );
578
 
579
}
580
 
581
/*
582
 . Function: smc_shutdown
583
 . Purpose:  closes down the SMC91xxx chip.
584
 . Method:
585
 .      1. zero the interrupt mask
586
 .      2. clear the enable receive flag
587
 .      3. clear the enable xmit flags
588
 .
589
 . TODO:
590
 .   (1) maybe utilize power down mode.
591
 .      Why not yet?  Because while the chip will go into power down mode,
592
 .      the manual says that it will wake up in response to any I/O requests
593
 .      in the register space.   Empirical results do not show this working.
594
*/
595
static void smc_shutdown( unsigned long ioaddr )
596
{
597
        PRINTK2(CARDNAME":smc_shutdown\n");
598
 
599
        /* no more interrupts for me */
600
        SMC_SELECT_BANK( 2 );
601
        outb( 0, ioaddr + IM_REG );
602
 
603
        /* and tell the card to stay away from that nasty outside world */
604
        SMC_SELECT_BANK( 0 );
605
        outb( RCR_CLEAR, ioaddr + RCR_REG );
606
        outb( TCR_CLEAR, ioaddr + TCR_REG );
607
 
608
#ifdef POWER_DOWN
609
        /* finally, shut the chip down */
610
        SMC_SELECT_BANK( 1 );
611
        outw( inw( ioaddr + CONFIG_REG ) & ~CONFIG_EPH_POWER_EN,
612
                ioaddr + CONFIG_REG  );
613
#endif
614
}
615
 
616
 
617
/*
618
 . Function: smc_setmulticast( int ioaddr, int count, dev_mc_list * adds )
619
 . Purpose:
620
 .    This sets the internal hardware table to filter out unwanted multicast
621
 .    packets before they take up memory.
622
 .
623
 .    The SMC chip uses a hash table where the high 6 bits of the CRC of
624
 .    address are the offset into the table.  If that bit is 1, then the
625
 .    multicast packet is accepted.  Otherwise, it's dropped silently.
626
 .
627
 .    To use the 6 bits as an offset into the table, the high 3 bits are the
628
 .    number of the 8 bit register, while the low 3 bits are the bit within
629
 .    that register.
630
 .
631
 . This routine is based very heavily on the one provided by Peter Cammaert.
632
*/
633
 
634
 
635
static void smc_setmulticast( unsigned long ioaddr, int count,
636
        struct dev_mc_list * addrs )
637
{
638
        int                     i;
639
        unsigned char           multicast_table[ 8 ];
640
        struct dev_mc_list      * cur_addr;
641
        /* table for flipping the order of 3 bits */
642
        unsigned char invert3[] = { 0, 4, 2, 6, 1, 5, 3, 7 };
643
 
644
        PRINTK2(CARDNAME":smc_setmulticast\n");
645
 
646
        /* start with a table of all zeros: reject all */
647
        memset( multicast_table, 0, sizeof( multicast_table ) );
648
 
649
        cur_addr = addrs;
650
        for ( i = 0; i < count ; i ++, cur_addr = cur_addr->next  ) {
651
                int position;
652
 
653
                /* do we have a pointer here? */
654
                if ( !cur_addr )
655
                        break;
656
                /* make sure this is a multicast address - shouldn't this
657
                   be a given if we have it here ? */
658
                if ( !( *cur_addr->dmi_addr & 1 ) )
659
                        continue;
660
 
661
                /* only use the low order bits */
662
                position = crc32( cur_addr->dmi_addr, 6 ) & 0x3f;
663
 
664
                /* do some messy swapping to put the bit in the right spot */
665
                multicast_table[invert3[position&7]] |=
666
                                        (1<<invert3[(position>>3)&7]);
667
 
668
        }
669
        /* now, the table can be loaded into the chipset */
670
        SMC_SELECT_BANK( 3 );
671
 
672
        for ( i = 0; i < 8 ; i++ ) {
673
                outb( multicast_table[i], ioaddr + MCAST_REG1 + i );
674
        }
675
 
676
}
677
 
678
/*
679
  Finds the CRC32 of a set of bytes.
680
  Again, from Peter Cammaert's code.
681
*/
682
static int crc32( char * s, int length ) {
683
        /* indices */
684
        int perByte;
685
        int perBit;
686
        /* crc polynomial for Ethernet */
687
        const unsigned long poly = 0xedb88320;
688
        /* crc value - preinitialized to all 1's */
689
        unsigned long crc_value = 0xffffffff;
690
 
691
        for ( perByte = 0; perByte < length; perByte ++ ) {
692
                unsigned char   c;
693
 
694
                c = *(s++);
695
                for ( perBit = 0; perBit < 8; perBit++ ) {
696
                        crc_value = (crc_value>>1)^
697
                                (((crc_value^c)&0x01)?poly:0);
698
                        c >>= 1;
699
                }
700
        }
701
        return  crc_value;
702
}
703
 
704
 
705
/*
706
 . Function: smc_wait_to_send_packet( struct sk_buff * skb, struct device * )
707
 . Purpose:
708
 .    Attempt to allocate memory for a packet, if chip-memory is not
709
 .    available, then tell the card to generate an interrupt when it
710
 .    is available.
711
 .
712
 . Algorithm:
713
 .
714
 . o    if the saved_skb is not currently null, then drop this packet
715
 .      on the floor.  This should never happen, because of TBUSY.
716
 . o    if the saved_skb is null, then replace it with the current packet,
717
 . o    See if I can sending it now.
718
 . o    (NO): Enable interrupts and let the interrupt handler deal with it.
719
 . o    (YES):Send it now.
720
*/
721
static int smc_wait_to_send_packet( struct sk_buff * skb, struct device * dev )
722
{
723
    struct          smc_local *lp   = (struct smc_local *)dev->priv;
724
    unsigned long   ioaddr          = dev->base_addr;
725
    word            length;
726
    unsigned short  numPages;
727
    word            time_out;
728
    word            status;
729
 
730
    PRINTK3("%s:smc_wait_to_send_packet\n", dev->name);
731
 
732
    if (lp->saved_skb)
733
    {
734
        // THIS SHOULD NEVER HAPPEN.
735
        lp->stats.tx_aborted_errors++;
736
        printk("%s: Bad Craziness - sent packet while busy.\n", dev->name);
737
        return 1;
738
    }
739
    lp->saved_skb = skb;
740
 
741
    length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
742
 
743
 
744
    //
745
    // The MMU wants the number of pages to be the number of 256 bytes
746
    // 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
747
    //
748
    // The 91C111 ignores the size bits, but the code is left intact
749
    // for backwards and future compatibility.
750
    //
751
    // Pkt size for allocating is data length +6 (for additional status
752
    // words, length and ctl!)
753
    //
754
    // If odd size then last byte is included in this header.
755
    //
756
    numPages =   ((length & 0xfffe) + 6);
757
    numPages >>= 8; // Divide by 256
758
 
759
    if (numPages > 7 )
760
    {
761
        printk("%s: Far too big packet error. \n", dev->name);
762
        // freeing the packet is a good thing here... but should
763
        // . any packets of this size get down here?
764
        dev_kfree_skb (skb,FREE_WRITE);
765
        lp->saved_skb = NULL;
766
        // this IS an error, but, i don't want the skb saved
767
        return 0;
768
    }
769
        // either way, a packet is waiting now
770
    lp->packets_waiting++;
771
 
772
    // now, try to allocate the memory
773
    SMC_SELECT_BANK( 2 );
774
    outw( MC_ALLOC | numPages, ioaddr + MMU_CMD_REG );
775
    //
776
    // Performance Hack
777
    //
778
    // wait a short amount of time.. if I can send a packet now, I send
779
    // it now.  Otherwise, I enable an interrupt and wait for one to be
780
    // available.
781
    //
782
    // I could have handled this a slightly different way, by checking to
783
    // see if any memory was available in the FREE MEMORY register.  However,
784
    // either way, I need to generate an allocation, and the allocation works
785
    // no matter what, so I saw no point in checking free memory.
786
    //
787
    time_out = MEMORY_WAIT_TIME;
788
    do
789
    {
790
        status = inb( ioaddr + INT_REG );
791
        time_out = time_out - 1;
792
    } while ((time_out > 0) && ((status & IM_ALLOC_INT) == 0));
793
 
794
    //If interrupt, acknowledge interrupt
795
    if(status & IM_ALLOC_INT)
796
    {
797
        outb( IM_ALLOC_INT, ioaddr + INT_REG );
798
    }
799
    else
800
    {
801
        // oh well, wait until the chip finds memory later
802
        SMC_ENABLE_INT( IM_ALLOC_INT );
803
        // Check the status bit one more time just in case
804
        // it snuk in between the time we last checked it
805
        // and when we set the interrupt bit
806
        status = inb( ioaddr + INT_REG );
807
        if ( !(status & IM_ALLOC_INT) )
808
        {
809
            PRINTK2("%s: memory allocation deferred. \n", dev->name);
810
            smc_register_dump(dev);
811
            // it's deferred, but I'll handle it later
812
            return 0;
813
        }
814
 
815
        // Looks like it did sneak in, so disable the interrupt
816
        SMC_DISABLE_INT( IM_ALLOC_INT );
817
    }
818
    // or YES! I can send the packet now.
819
    smc_hardware_send_packet(dev);
820
 
821
    return 0;
822
}
823
 
824
/*
825
 . Function:  smc_hardware_send_packet(struct device * )
826
 . Purpose:
827
 .      This sends the actual packet to the SMC9xxx chip.
828
 .
829
 . Algorithm:
830
 .      First, see if a saved_skb is available.
831
 .              ( this should NOT be called if there is no 'saved_skb'
832
 .      Now, find the packet number that the chip allocated
833
 .      Point the data pointers at it in memory
834
 .      Set the length word in the chip's memory
835
 .      Dump the packet to chip memory
836
 .      Check if a last byte is needed ( odd length packet )
837
 .              if so, set the control flag right
838
 .      Tell the card to send it
839
 .      Enable the transmit interrupt, so I know if it failed
840
 .      Free the kernel data if I actually sent it.
841
*/
842
static void smc_hardware_send_packet( struct device * dev )
843
{
844
        struct smc_local *lp = (struct smc_local *)dev->priv;
845
        byte                    packet_no;
846
        struct sk_buff *        skb = lp->saved_skb;
847
        word                    length;
848
        unsigned long           ioaddr;
849
        byte                    * buf;
850
        byte                    *bufb;
851
        word                    lengtht;
852
 
853
        PRINTK3("%s:smc_hardware_send_packet\n", dev->name);
854
 
855
        ioaddr = dev->base_addr;
856
        PRINTK3("%s:smc io address is 0x%08lx\n", dev->name, ioaddr);
857
 
858
        if ( !skb )
859
        {
860
                PRINTK("%s: In XMIT with no packet to send \n", dev->name);
861
                return;
862
        }
863
        length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
864
        buf = skb->data;
865
 
866
        /* I can send the packet now.. */
867
 
868
        bufb = (byte *) buf;
869
 
870
        /* If I get here, I _know_ there is a packet slot waiting for me */
871
        packet_no = REG8( ioaddr+AR_REG);
872
        if (packet_no & AR_FAILED) {
873
                /* or isn't there?  BAD CHIP! */
874
                printk ("Memory allocation failed. \n");
875
                return;
876
        }
877
 
878
        /* we have a packet address, so tell the card to use it */
879
        REG8( ioaddr+PN_REG)=packet_no;
880
 
881
        /* point to the beginning of the packet */
882
        REG16( ioaddr+PTR_REG)=PTR_AUTOINC;
883
 
884
 
885
        /* send the packet length ( +6 for status, length and ctl byte )
886
           and the status word ( set to zeros ) */
887
        REG16(ioaddr+DATA_REG)=0;
888
        /* send the packet length ( +6 for status words, length, and ctl */
889
        REG16(ioaddr+DATA_REG)=length + 6;
890
 
891
 
892
        /* send the actual data */
893
        lengtht=length>>1;
894
        while(lengtht-->0){
895
          REG16(ioaddr+DATA_REG)=SWAP16(*((word*)bufb));
896
          bufb+=sizeof(word);
897
        }
898
 
899
 
900
        /* Send the last byte, if there is one.   */
901
        if ((length & 1) == 0) {
902
                REG16(ioaddr+DATA_REG)=0;
903
        } else {
904
                REG16(ioaddr+DATA_REG)=bufb[length - 1] | 0x2000;
905
        }
906
 
907
        /* and let the chipset deal with it */
908
        REG16(ioaddr+MMU_CMD_REG)=MC_ENQUEUE;
909
 
910
 
911
        PRINTK2("%s: Sent packet of length %d \n", dev->name, length);
912
 
913
        lp->saved_skb = NULL;
914
        dev_kfree_skb (skb,FREE_WRITE);
915
 
916
        dev->trans_start = jiffies;
917
 
918
        /* we can send another packet */
919
        dev->tbusy = 0;
920
 
921
 
922
        return;
923
}
924
 
925
/*-------------------------------------------------------------------------
926
 |
927
 | smc_init( struct device * dev )
928
 |   Input parameters:
929
 |      dev->base_addr == 0, try to find all possible locations
930
 |      dev->base_addr == 1, return failure code
931
 |      dev->base_addr == 2, always allocate space,  and return success
932
 |      dev->base_addr == <anything else>   this is the address to check
933
 |
934
 |   Output:
935
 |      0 --> there is a device
936
 |      anything else, error
937
 |
938
 ---------------------------------------------------------------------------
939
*/
940
int smc_init_91C111(struct device *dev)
941
{
942
        int i;
943
        int base_addr = dev ? dev->base_addr : 0;
944
 
945
        PRINTK2(CARDNAME":smc_init_91C111\n");
946
        printk(CARDNAME":smc_init_91C111\n");
947
 
948
        /*  try a specific location */
949
        if (base_addr > 0x1ff)
950
        {
951
                int     error;
952
                error = smc_probe(base_addr);
953
                if ( 0 == error )
954
                {
955
                        return smc_initcard( dev, base_addr );
956
                }
957
                return error;
958
        }
959
        else
960
        {
961
                if ( 0 != base_addr )
962
                {
963
                        return -ENXIO;
964
                }
965
        }
966
 
967
        /* check every ethernet address */
968
        for (i = 0; smc_portlist[i]; i++)
969
        {
970
                int ioaddr = smc_portlist[i];
971
 
972
                // check if the area is available & check this specific address
973
                if(check_region(ioaddr , SMC_IO_EXTENT) == 0)
974
                {
975
                        if(smc_probe(ioaddr) == 0)
976
                                return smc_initcard(dev, ioaddr);
977
                        else
978
                                printk("<1>Error during smc probe.\n");
979
                }
980
        }
981
 
982
        // couldn't find anything
983
        return -ENODEV;
984
}
985
 
986
 
987
/*-------------------------------------------------------------------------
988
 |
989
 | smc_destructor( struct device * dev )
990
 |   Input parameters:
991
 |      dev, pointer to the device structure
992
 |
993
 |   Output:
994
 |      None.
995
 |
996
 ---------------------------------------------------------------------------
997
*/
998
void smc_91C111_destructor(struct device *dev)
999
{
1000
        PRINTK2(CARDNAME":smc_91C111_destructor\n");
1001
}
1002
 
1003
 
1004
 
1005
/*----------------------------------------------------------------------
1006
 . Function: smc_probe( unsigned int ioaddr )
1007
 .
1008
 . Purpose:
1009
 .      Tests to see if a given ioaddr points to an SMC91111 chip.
1010
 .      Returns a 0 on success
1011
 .
1012
 . Algorithm:
1013
 .      (1) see if the high byte of BANK_SELECT is 0x33
1014
 .      (2) compare the ioaddr with the base register's address
1015
 .      (3) see if I recognize the chip ID in the appropriate register
1016
 .
1017
 .---------------------------------------------------------------------
1018
 */
1019
 
1020
static int smc_probe( unsigned long ioaddr )
1021
{
1022
        unsigned int    bank;
1023
        word    revision_register;
1024
        word  base_address_register;
1025
 
1026
        PRINTK2(CARDNAME":smc_probe\n");
1027
 
1028
        SMC_SELECT_BANK(0);
1029
 
1030
        /* First, see if the high byte is 0x33 */
1031
        bank = inw( ioaddr + BANK_SELECT );
1032
        if ( (bank & 0xFF00) != 0x3300 )
1033
        {
1034
                printk("<1>Smc probe bank check 1 failed. %X %X\n",bank,ioaddr);
1035
                return -ENODEV;
1036
        }
1037
        /* The above MIGHT indicate a device, but I need to write to further
1038
           test this.  */
1039
        outw( 0x0, ioaddr + BANK_SELECT );
1040
        bank = inw( ioaddr + BANK_SELECT );
1041
        if ( (bank & 0xFF00 ) != 0x3300 )
1042
        {
1043
                printk("<1>Smc probe bank check 2 failed.\n");
1044
                return -ENODEV;
1045
        }
1046
#if SMC_DEBUG > 3
1047
        PRINTK3(CARDNAME":Bank read as a 16 bit value:0x%04x\n",
1048
                        inw(ioaddr + BANK_SELECT));
1049
        PRINTK3(CARDNAME":Bank read as an 8 bit value:0x%02x\n",
1050
                        inb(ioaddr + BANK_SELECT));
1051
        PRINTK3(CARDNAME":Bank + 1 read as an 8 bit value:0x%02x\n",
1052
                        inb(ioaddr + BANK_SELECT + 1));
1053
#endif
1054
 
1055
        /*  check if the revision register is something that I recognize.
1056
            These might need to be added to later, as future revisions
1057
            could be added.  */
1058
        SMC_SELECT_BANK(3);
1059
        revision_register  = inw( ioaddr + REV_REG );
1060
        if ( !chip_ids[ ( revision_register  >> 4 ) & 0xF  ] )
1061
        {
1062
                /* I don't recognize this chip, so... */
1063
                printk(CARDNAME": IO %lx: Unrecognized revision register:"
1064
                                " %x, Contact author. \n",
1065
                                ioaddr, revision_register );
1066
 
1067
                return -ENODEV;
1068
        }
1069
 
1070
        /* at this point I'll assume that the chip is an SMC9xxx. It might be
1071
           prudent to check a listing of MAC addresses against the hardware
1072
           address, or do some other tests. */
1073
        return 0;
1074
}
1075
 
1076
/*---------------------------------------------------------------
1077
 . Here I do typical initialization tasks.
1078
 .
1079
 . o  Initialize the structure if needed
1080
 . o  print out my vanity message if not done so already
1081
 . o  print out what type of hardware is detected
1082
 . o  print out the ethernet address
1083
 . o  find the IRQ
1084
 . o  set up my private data
1085
 . o  configure the dev structure with my subroutines
1086
 . o  actually GRAB the irq.
1087
 . o  GRAB the region
1088
 .-----------------------------------------------------------------
1089
*/
1090
static int  smc_initcard(struct device *dev, unsigned long ioaddr)
1091
{
1092
        int i;
1093
 
1094
        static unsigned version_printed = 0;
1095
 
1096
        /* registers */
1097
        word    revision_register;
1098
        word    memory_info_register;
1099
 
1100
        const char *    version_string;
1101
        int     memory;
1102
 
1103
        int   irqval;
1104
 
1105
        PRINTK2("%s:smc_initcard\n", dev->name);
1106
 
1107
        /* see if I need to initialize the ethernet card structure */
1108
        if (dev == NULL)
1109
        {
1110
                dev = init_etherdev(0, 0);
1111
                if (dev == NULL)
1112
                        return -ENOMEM;
1113
        }
1114
 
1115
        if (version_printed++ == 0)
1116
                printk("%s", version);
1117
 
1118
        /* fill in some of the fields */
1119
        dev->base_addr = ioaddr;
1120
 
1121
        /* . Get the MAC address ( bank 1, regs 4 - 9 ) */
1122
        dev->dev_addr[0]=0x12;
1123
        dev->dev_addr[1]=0x34;
1124
        dev->dev_addr[2]=0x56;
1125
        dev->dev_addr[3]=0x78;
1126
        dev->dev_addr[4]=0xAC;
1127
        dev->dev_addr[5]=0xCD;
1128
 
1129
        /* get the memory information */
1130
 
1131
        SMC_SELECT_BANK( 0 );
1132
        memory_info_register = inw( ioaddr + MIR_REG );
1133
        memory = memory_info_register & (word)0x00ff;
1134
        memory *= LAN91C111_MEMORY_MULTIPLIER;
1135
 
1136
        /*
1137
           Now, I want to find out more about the chip.  This is sort of
1138
           redundant, but it's cleaner to have it in both, rather than having
1139
           one VERY long probe procedure.
1140
         */
1141
        SMC_SELECT_BANK(3);
1142
        revision_register  = inw( ioaddr + REV_REG );
1143
        version_string = chip_ids[ ( revision_register  >> 4 ) & 0xF  ];
1144
        if ( !version_string )
1145
        {
1146
                /* I shouldn't get here because this call was done before.... */
1147
                return -ENODEV;
1148
        }
1149
 
1150
        /* now, reset the chip, and put it into a known state */
1151
        smc_reset( dev );
1152
 
1153
        /*
1154
           . If dev->irq is 0, then the device has to be banged on to see
1155
           . what the IRQ is.
1156
           .
1157
           . This banging doesn't always detect the IRQ, for unknown reasons.
1158
           . a workaround is to reset the chip and try again.
1159
           .
1160
           . Interestingly, the DOS packet driver *SETS* the IRQ on the card to
1161
           . be what is requested on the command line. I don't do that, mostly
1162
           . because the card that I have uses a non-standard method of
1163
           . accessing the IRQs, and because this _should_ work in most
1164
           .  configurations.
1165
           . Specifying an IRQ is done with the assumption that the user knows
1166
           . what (s)he is doing.  No checking is done!!!!
1167
         .
1168
        */
1169
 
1170
        /*OpenRISC ETH IRQ*/
1171
        dev->irq=4;
1172
 
1173
        /* now, print out the card info, in a short format.. */
1174
 
1175
        printk("%s: %s(rev:%d) at %#3lx IRQ:%d MEMSIZE:%db NOWAIT:%d ",
1176
                dev->name,
1177
                version_string, revision_register & 0xF, ioaddr, dev->irq,
1178
                memory, dev->dma);
1179
        /*
1180
         . Print the Ethernet address
1181
        */
1182
        printk("\n\tADDR: ");
1183
        for (i = 0; i < 5; i++)
1184
                printk("%2.2x:", dev->dev_addr[i] );
1185
        printk("%2.2x \n", dev->dev_addr[5] );
1186
 
1187
 
1188
        // Initialize the private structure.
1189
        if (dev->priv == NULL)
1190
        {
1191
                PRINTK3("%s:Requesting memory for private data\n", dev->name);
1192
                dev->priv = kmalloc(sizeof(struct smc_local), GFP_KERNEL);
1193
                if (dev->priv == NULL)
1194
                        return -ENOMEM;
1195
        }
1196
        else
1197
        {
1198
                PRINTK3("%s:Memory already allocated for private data at 0x%08lx\n",
1199
                        dev->name, (unsigned long)dev->priv);
1200
        }
1201
        /* set the private data to zero by default */
1202
        memset(dev->priv, 0, sizeof(struct smc_local));
1203
 
1204
        /* Fill in the fields of the device structure with ethernet values. */
1205
        ether_setup(dev);
1206
 
1207
        /* Grab the IRQ */
1208
        irqval = request_irq(dev->irq, smc_interrupt, 0, dev->name, dev);
1209
        if (irqval) {
1210
          printk("%s: unable to get IRQ %d (irqval=%d).\n",
1211
                dev->name, dev->irq, irqval);
1212
          return -EAGAIN;
1213
        }
1214
        irq2dev_map[dev->irq] =dev;
1215
        /* Grab the region so that no one else tries to probe our ioports. */
1216
        request_region(ioaddr, SMC_IO_EXTENT, dev->name);
1217
 
1218
        dev->open                       = smc_open;
1219
        dev->stop                       = smc_close;
1220
        dev->hard_start_xmit            = smc_send_packet;
1221
        dev->get_stats                  = smc_query_statistics;
1222
#ifdef  HAVE_MULTICAST
1223
        dev->set_multicast_list         = &smc_set_multicast_list;
1224
#endif
1225
 
1226
        return 0;
1227
}
1228
 
1229
#if SMC_DEBUG > 2
1230
static void print_packet( byte * buf, int length )
1231
{
1232
#if SMC_DEBUG > 3
1233
        int i;
1234
        int remainder;
1235
        int lines;
1236
#endif
1237
 
1238
        printk("Packet of length %d \n", length );
1239
 
1240
#if SMC_DEBUG > 3
1241
        lines = length / 16;
1242
        remainder = length % 16;
1243
 
1244
        for ( i = 0; i < lines ; i ++ ) {
1245
                int cur;
1246
 
1247
                for ( cur = 0; cur < 8; cur ++ ) {
1248
                        byte a, b;
1249
 
1250
                        a = *(buf ++ );
1251
                        b = *(buf ++ );
1252
                        printk("%02x%02x ", a, b );
1253
                }
1254
                printk("\n");
1255
        }
1256
        for ( i = 0; i < remainder/2 ; i++ ) {
1257
                byte a, b;
1258
 
1259
                a = *(buf ++ );
1260
                b = *(buf ++ );
1261
                printk("%02x%02x ", a, b );
1262
        }
1263
        printk("\n");
1264
#endif
1265
}
1266
#endif
1267
 
1268
 
1269
/*
1270
 * Open and Initialize the board
1271
 *
1272
 * Set up everything, reset the card, etc ..
1273
 *
1274
 */
1275
static int smc_open(struct device *dev)
1276
{
1277
        struct smc_local *lp    = (struct smc_local *)dev->priv;
1278
        unsigned long   ioaddr = dev->base_addr;
1279
        int     i;      /* used to set hw ethernet address */
1280
 
1281
        PRINTK2("%s:smc_open\n", dev->name);
1282
 
1283
        /* clear out all the junk that was put here before... */
1284
        memset(dev->priv, 0, sizeof(struct smc_local));
1285
 
1286
        dev->tbusy      = 0;
1287
        dev->interrupt  = 0;
1288
        dev->start      = 1;
1289
 
1290
        // Setup the default Register Modes
1291
        lp->tcr_cur_mode = TCR_DEFAULT;
1292
        lp->rcr_cur_mode = RCR_DEFAULT;
1293
        lp->rpc_cur_mode = RPC_DEFAULT;
1294
 
1295
#ifdef CONFIG_SYSCTL
1296
        // Set default parameters (files)
1297
        lp->ctl_swfdup = 0;
1298
        lp->ctl_ephloop = 0;
1299
        lp->ctl_miiop = 0;
1300
        lp->ctl_autoneg = 1;
1301
        lp->ctl_rfduplx = 1;
1302
        lp->ctl_rspeed = 100;
1303
        lp->ctl_afduplx = 1;
1304
        lp->ctl_aspeed = 100;
1305
        lp->ctl_lnkfail = 1;
1306
        lp->ctl_forcol = 0;
1307
        lp->ctl_filtcar = 0;
1308
#endif
1309
        /* reset the hardware */
1310
 
1311
        smc_reset( dev );
1312
        smc_enable( dev );
1313
 
1314
        /* Configure the PHY */
1315
        smc_phy_configure(dev);
1316
 
1317
        /*
1318
                According to Becker, I have to set the hardware address
1319
                at this point, because the (l)user can set it with an
1320
                ioctl.  Easily done...
1321
        */
1322
        SMC_SELECT_BANK( 1 );
1323
 
1324
        for ( i = 0; i < 6; i += 2 ) {
1325
                word    address;
1326
 
1327
                address = dev->dev_addr[ i + 1 ] << 8 ;
1328
                address  |= dev->dev_addr[ i ];
1329
                outw( address, ioaddr + ADDR0_REG + i );
1330
        }
1331
 
1332
 
1333
#ifdef CONFIG_SYSCTL
1334
        smc_sysctl_register(dev);
1335
#endif /* CONFIG_SYSCTL */ 
1336
 
1337
        return 0;
1338
}
1339
 
1340
/*--------------------------------------------------------
1341
 . Called by the kernel to send a packet out into the void
1342
 . of the net.  This routine is largely based on
1343
 . skeleton.c, from Becker.
1344
 .--------------------------------------------------------
1345
*/
1346
static int smc_send_packet(struct sk_buff *skb, struct device *dev)
1347
{
1348
 
1349
        PRINTK3("%s:smc_send_packet\n", dev->name);
1350
 
1351
        if (dev->tbusy) {
1352
                /* If we get here, some higher level has decided we are broken.
1353
                   There should really be a "kick me" function call instead. */
1354
                int tickssofar = jiffies - dev->trans_start;
1355
                if (tickssofar < 5)
1356
                        return 1;
1357
                printk(KERN_WARNING "%s: transmit timed out, %s?\n",
1358
                        dev->name, tx_done(dev) ? "IRQ conflict" :
1359
                        "network cable problem");
1360
                /* "kick" the adaptor */
1361
                smc_reset( dev );
1362
                smc_enable( dev );
1363
 
1364
                /* Reconfigure the PHY */
1365
                smc_phy_configure(dev);
1366
 
1367
 
1368
                dev->tbusy = 0;
1369
                dev->trans_start = jiffies;
1370
                /* clear anything saved */
1371
                ((struct smc_local *)dev->priv)->saved_skb = NULL;
1372
        }
1373
 
1374
        /* Block a timer-based transmit from overlapping.  This could better be
1375
           done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */
1376
        if (test_and_set_bit(0, (void*)&dev->tbusy) != 0) {
1377
                printk(KERN_WARNING "%s: Transmitter access conflict.\n",
1378
                        dev->name);
1379
                dev_kfree_skb (skb,FREE_WRITE);
1380
        } else {
1381
                /* Well, I want to send the packet.. but I don't know
1382
                   if I can send it right now...  */
1383
                return smc_wait_to_send_packet( skb, dev );
1384
        }
1385
        return 0;
1386
}
1387
 
1388
/*--------------------------------------------------------------------
1389
 .
1390
 . This is the main routine of the driver, to handle the device when
1391
 . it needs some attention.
1392
 .
1393
 . So:
1394
 .   first, save state of the chipset
1395
 .   branch off into routines to handle each case, and acknowledge
1396
 .          each to the interrupt register
1397
 .   and finally restore state.
1398
 .
1399
 ---------------------------------------------------------------------*/
1400
static void smc_interrupt(int irq, void * dev_id,  struct pt_regs * regs)
1401
{
1402
        struct device *dev      = dev_id;
1403
        //Don't initializes these until after testing that the pointer is not NULL
1404
        unsigned long ioaddr;
1405
        struct smc_local *lp;
1406
 
1407
        byte    status;
1408
        word    card_stats;
1409
        byte    mask;
1410
        int     timeout;
1411
        /* state registers */
1412
        word    saved_bank;
1413
        word    saved_pointer;
1414
 
1415
        PRINTK3("%s: SMC interrupt started ---------------------\n", dev->name);
1416
 
1417
        if (dev == NULL) {
1418
                printk(KERN_WARNING "irq %d for unknown device.\n", irq);
1419
                return;
1420
        }
1421
        ioaddr = dev->base_addr;
1422
        lp = (struct smc_local *)dev->priv;
1423
 
1424
        /* will Linux let this happen ??  If not, this costs some speed */
1425
        if ( dev->interrupt ) {
1426
                printk(KERN_WARNING "%s: interrupt inside interrupt.\n",
1427
                        dev->name);
1428
                return;
1429
        }
1430
 
1431
        dev->interrupt = 1;
1432
        smc_register_dump(dev);
1433
 
1434
        saved_bank = inw( ioaddr + BANK_SELECT );
1435
 
1436
        SMC_SELECT_BANK(2);
1437
        saved_pointer = inw( ioaddr + PTR_REG );
1438
 
1439
        /* read the interrupt status register */
1440
        mask = inb( ioaddr + IM_REG );
1441
 
1442
        /* disable all interrupts */
1443
        outb( 0, ioaddr + IM_REG );
1444
 
1445
        /* set a timeout value, so I don't stay here forever */
1446
        timeout = 4;
1447
 
1448
        PRINTK2(KERN_WARNING "%s: MASK IS %x \n", dev->name, mask);
1449
        do
1450
    {
1451
        /* read the status flag, and mask it */
1452
        status = inb( ioaddr + INT_REG ) & mask;
1453
        if (!status )
1454
            break;
1455
 
1456
        PRINTK3(KERN_WARNING "%s: Handling interrupt status %x \n",
1457
                dev->name, status);
1458
 
1459
        if (status & IM_RCV_INT)
1460
        {
1461
            /* Got a packet(s). */
1462
            PRINTK2(KERN_WARNING"%s: Receive Interrupt\n", dev->name);
1463
            smc_rcv(dev);
1464
        }
1465
        else
1466
            if (status & IM_TX_INT )
1467
            {
1468
                PRINTK2(KERN_WARNING "%s: TX ERROR handled\n", dev->name);
1469
                smc_tx(dev);
1470
                // Acknowledge the interrupt
1471
                outb(IM_TX_INT, ioaddr + INT_REG );
1472
            }
1473
            else
1474
                if (status & IM_TX_EMPTY_INT )
1475
                {
1476
                    /* update stats */
1477
                    SMC_SELECT_BANK( 0 );
1478
                    card_stats = inw( ioaddr + COUNTER_REG );
1479
                    /* single collisions */
1480
                    lp->stats.collisions += card_stats & 0xF;
1481
                    card_stats >>= 4;
1482
                    /* multiple collisions */
1483
                    lp->stats.collisions += card_stats & 0xF;
1484
                    /* these are for when linux supports these statistics */
1485
 
1486
                    SMC_SELECT_BANK( 2 );
1487
                    PRINTK2(KERN_WARNING "%s: TX_BUFFER_EMPTY handled\n",
1488
                            dev->name);
1489
                    // Acknowledge the interrupt
1490
 
1491
                    outb( IM_TX_EMPTY_INT, ioaddr + INT_REG );
1492
 
1493
                    mask &= ~IM_TX_EMPTY_INT;
1494
                    lp->stats.tx_packets += lp->packets_waiting;
1495
                    lp->packets_waiting = 0;
1496
                }
1497
                else
1498
                    if (status & IM_ALLOC_INT )
1499
                    {
1500
                        PRINTK2(KERN_DEBUG "%s: Allocation interrupt \n",
1501
                                dev->name);
1502
                        /* clear this interrupt so it doesn't happen again */
1503
                        mask &= ~IM_ALLOC_INT;
1504
 
1505
                        smc_hardware_send_packet( dev );
1506
 
1507
                        /* enable xmit interrupts based on this */
1508
                        mask |= ( IM_TX_EMPTY_INT | IM_TX_INT );
1509
 
1510
                        /* and let the card send more packets to me */
1511
                        mark_bh( NET_BH );
1512
 
1513
                        PRINTK2("%s: Handoff done successfully.\n", dev->name);
1514
                    }
1515
                    else
1516
                        if (status & IM_RX_OVRN_INT )
1517
                        {
1518
                            lp->stats.rx_errors++;
1519
                            lp->stats.rx_fifo_errors++;
1520
                            // Acknowledge the interrupt
1521
 
1522
                            outb( IM_RX_OVRN_INT, ioaddr + INT_REG );
1523
                        }
1524
                        else
1525
                            if (status & IM_EPH_INT )
1526
                            {
1527
                                PRINTK("%s: UNSUPPORTED: EPH INTERRUPT \n",
1528
                                        dev->name);
1529
                            }
1530
                            else
1531
                                if (status & IM_MDINT )
1532
                                {
1533
                                    smc_phy_interrupt(dev);
1534
                                    // Acknowledge the interrupt
1535
 
1536
                                    outb(IM_MDINT, ioaddr + INT_REG );
1537
                                }
1538
                                else
1539
                                    if (status & IM_ERCV_INT )
1540
                                    {
1541
                                        PRINTK("%s: UNSUPPORTED: ERCV INTERRUPT"
1542
                                               " \n", dev->name);
1543
                                        // Acknowledge the interrupt
1544
                                        outb( IM_ERCV_INT, ioaddr + INT_REG );
1545
                                    }
1546
    } while ( timeout -- );
1547
 
1548
 
1549
        /* restore register states */
1550
        SMC_SELECT_BANK( 2 );
1551
 
1552
        outb( mask, ioaddr + IM_REG );
1553
 
1554
        PRINTK3( KERN_WARNING "%s: MASK is now %x \n", dev->name, mask);
1555
        outw( saved_pointer, ioaddr + PTR_REG );
1556
 
1557
        SMC_SELECT_BANK( saved_bank );
1558
 
1559
        dev->interrupt = 0;
1560
        PRINTK3("%s: Interrupt done\n", dev->name);
1561
        return;
1562
}
1563
 
1564
/*-------------------------------------------------------------
1565
 .
1566
 . smc_rcv -  receive a packet from the card
1567
 .
1568
 . There is ( at least ) a packet waiting to be read from
1569
 . chip-memory.
1570
 .
1571
 . o Read the status
1572
 . o If an error, record it
1573
 . o otherwise, read in the packet
1574
 --------------------------------------------------------------
1575
*/
1576
static void smc_rcv(struct device *dev)
1577
{
1578
    struct smc_local *lp = (struct smc_local *)dev->priv;
1579
    unsigned long ioaddr = dev->base_addr;
1580
    int         packet_number;
1581
    word        status;
1582
    word        packet_length;
1583
    word        packet_length_loop;
1584
    word        word_readed;
1585
    byte        *datab;
1586
 
1587
    PRINTK3("%s:smc_rcv\n", dev->name);
1588
 
1589
    // assume bank 2 -valid since this is called from ISR
1590
 
1591
    packet_number = inw( ioaddr + RXFIFO_REG );
1592
 
1593
    if ( packet_number & RXFIFO_REMPTY )
1594
    {
1595
        // we got called , but nothing was on the FIFO
1596
        PRINTK("%s: WARNING: smc_rcv with nothing on FIFO. \n", dev->name);
1597
        // don't need to restore anything
1598
        return;
1599
    }
1600
 
1601
        // start reading from the start of the packet
1602
    outw( PTR_READ | PTR_RCV | PTR_AUTOINC, ioaddr + PTR_REG );
1603
 
1604
    status          = inw( ioaddr + DATA_REG );
1605
    packet_length   = inw( ioaddr + DATA_REG );
1606
 
1607
    // Handle odd number of bytes bug, problems with reading data register,...
1608
    packet_length = (packet_length & 0xfffc) + 4;
1609
    packet_length &= 0x07ff;  // mask off top bits
1610
 
1611
    PRINTK2("%s:receive  status 0x%04x length field 0x%04x length 0x%04x\n",
1612
            dev->name, status, packet_length, (packet_length&0x07ff));
1613
 
1614
    if ( !(status & RS_ERRORS ))
1615
    {
1616
        // do stuff to make a new packet
1617
        struct sk_buff  * skb;
1618
        byte            * data;
1619
        PRINTK3("%s:No errors on receive\n", dev->name);
1620
        if(packet_length == 0)
1621
            panic("Zero lengthed packet receieved.");
1622
 
1623
        // set multicast stats
1624
        if ( status & RS_MULTICAST )
1625
            lp->stats.multicast++;
1626
 
1627
        // Allocate enough memory for entire receive frame, to be safe
1628
        skb = dev_alloc_skb( packet_length );
1629
 
1630
                // Adjust for having already read the first two words
1631
        packet_length -= 4;
1632
 
1633
            if ( skb == NULL )
1634
        {
1635
            printk(KERN_NOTICE "%s: Low memory, packet dropped.\n", dev->name);
1636
            lp->stats.rx_dropped++;
1637
        }
1638
 
1639
                /*
1640
                 ! This should work without alignment, but it could be
1641
                 ! in the worse case
1642
                */
1643
                /* TODO: Should I use 32bit alignment here ? */
1644
                skb_reserve( skb, 2 );   /* 16 bit alignment */
1645
 
1646
                skb->dev = dev;
1647
 
1648
                // set odd length for bug in LAN91C111,
1649
                // which never sets RS_ODDFRAME
1650
                // Instead, just round up to the next dword size
1651
                //data = skb_put( skb, packet_length + 1 );
1652
                data = skb_put( skb, packet_length);
1653
 
1654
                PRINTK3(" Reading %d words and %d byte(s) \n",
1655
                        (packet_length >> 1 ), packet_length & 1 );
1656
 
1657
                packet_length_loop=packet_length>>1;
1658
 
1659
                //insw(ioaddr + DATA_REG , data, packet_length >> 1);
1660
 
1661
                datab=(byte*)data;
1662
                while(packet_length_loop-->0){
1663
                  word_readed=REG16(ioaddr+DATA_REG);
1664
                  *((word*)datab)=SWAP16(word_readed);
1665
                  datab+=sizeof(word);
1666
                }
1667
 
1668
#if SMC_DEBUG > 2
1669
                printk("Receiving Packet\n");
1670
                print_packet( data, packet_length );
1671
#endif
1672
 
1673
                skb->protocol = eth_type_trans(skb, dev );
1674
                netif_rx(skb);
1675
                lp->stats.rx_packets++;
1676
        } else {
1677
                /* error ... */
1678
                lp->stats.rx_errors++;
1679
 
1680
                if ( status & RS_ALGNERR )  lp->stats.rx_frame_errors++;
1681
                if ( status & (RS_TOOSHORT | RS_TOOLONG ) )
1682
                        lp->stats.rx_length_errors++;
1683
                if ( status & RS_BADCRC)        lp->stats.rx_crc_errors++;
1684
        }
1685
 
1686
        while ( inw( ioaddr + MMU_CMD_REG ) & MC_BUSY )
1687
                udelay(1); // Wait until not busy
1688
 
1689
        /*  error or good, tell the card to get rid of this packet */
1690
        outw( MC_RELEASE, ioaddr + MMU_CMD_REG );
1691
 
1692
 
1693
        return;
1694
}
1695
 
1696
 
1697
/*************************************************************************
1698
 . smc_tx
1699
 .
1700
 . Purpose:  Handle a transmit error message.   This will only be called
1701
 .   when an error, because of the AUTO_RELEASE mode.
1702
 .
1703
 . Algorithm:
1704
 .      Save pointer and packet no
1705
 .      Get the packet no from the top of the queue
1706
 .      check if it's valid ( if not, is this an error??? )
1707
 .      read the status word
1708
 .      record the error
1709
 .      ( resend?  Not really, since we don't want old packets around )
1710
 .      Restore saved values
1711
 ************************************************************************/
1712
static void smc_tx( struct device * dev )
1713
{
1714
        unsigned long ioaddr = dev->base_addr;
1715
        struct smc_local *lp = (struct smc_local *)dev->priv;
1716
        byte saved_packet;
1717
        byte packet_no;
1718
        word tx_status;
1719
 
1720
 
1721
        PRINTK3("%s:smc_tx\n", dev->name);
1722
 
1723
        /* assume bank 2  */
1724
 
1725
        saved_packet = inb( ioaddr + PN_REG );
1726
        packet_no = inw( ioaddr + RXFIFO_REG );
1727
        packet_no &= 0x7F;
1728
 
1729
        /* If the TX FIFO is empty then nothing to do */
1730
        if ( packet_no & TXFIFO_TEMPTY ) {
1731
                return;
1732
        }
1733
 
1734
        /* select this as the packet to read from */
1735
        outb( packet_no, ioaddr + PN_REG );
1736
 
1737
        /* read the first word (status word) from this packet */
1738
        outw( PTR_AUTOINC | PTR_READ, ioaddr + PTR_REG );
1739
 
1740
        tx_status = inw( ioaddr + DATA_REG );
1741
        PRINTK3("%s: TX DONE STATUS: %4x \n", dev->name, tx_status);
1742
 
1743
        lp->stats.tx_errors++;
1744
        if ( tx_status & TS_LOSTCAR ) lp->stats.tx_carrier_errors++;
1745
        if ( tx_status & TS_LATCOL  ) {
1746
                printk(KERN_DEBUG
1747
                        "%s: Late collision occurred on last xmit.\n",
1748
                        dev->name);
1749
                lp->stats.tx_window_errors++;
1750
#ifdef CONFIG_SYSCTL
1751
                lp->ctl_forcol = 0; // Reset forced collsion
1752
#endif
1753
    }
1754
 
1755
        if ( tx_status & TS_SUCCESS ) {
1756
                printk("%s: Successful packet caused interrupt \n", dev->name);
1757
        }
1758
        /* re-enable transmit */
1759
        SMC_SELECT_BANK( 0 );
1760
        outw( inw( ioaddr + TCR_REG ) | TCR_ENABLE, ioaddr + TCR_REG );
1761
 
1762
        /* kill the packet */
1763
        SMC_SELECT_BANK( 2 );
1764
        outw( MC_FREEPKT, ioaddr + MMU_CMD_REG );
1765
 
1766
        /* one less packet waiting for me */
1767
        lp->packets_waiting--;
1768
 
1769
        /* Don't change Packet Number Reg until busy bit is cleared */
1770
        /* Per LAN91C111 Spec, Page 50 */
1771
        while ( inw( ioaddr + MMU_CMD_REG ) & MC_BUSY );
1772
 
1773
        outb( saved_packet, ioaddr + PN_REG );
1774
        return;
1775
}
1776
 
1777
 
1778
/*----------------------------------------------------
1779
 . smc_close
1780
 .
1781
 . this makes the board clean up everything that it can
1782
 . and not talk to the outside world.   Caused by
1783
 . an 'ifconfig ethX down'
1784
 .
1785
 -----------------------------------------------------*/
1786
static int smc_close(struct device *dev)
1787
{
1788
        dev->tbusy = 1;
1789
        dev->start = 0;
1790
 
1791
        PRINTK2("%s:smc_close\n", dev->name);
1792
 
1793
#ifdef CONFIG_SYSCTL
1794
        smc_sysctl_unregister(dev);
1795
#endif /* CONFIG_SYSCTL */ 
1796
 
1797
        /* clear everything */
1798
        smc_shutdown( dev->base_addr );
1799
 
1800
        /* Update the statistics here. */
1801
 
1802
        return 0;
1803
}
1804
 
1805
/*------------------------------------------------------------
1806
 . Get the current statistics.
1807
 . This may be called with the card open or closed.
1808
 .-------------------------------------------------------------*/
1809
static struct enet_statistics* smc_query_statistics(struct device *dev) {
1810
        struct smc_local *lp = (struct smc_local *)dev->priv;
1811
 
1812
        PRINTK2("%s:smc_query_statistics\n", dev->name);
1813
 
1814
        return &lp->stats;
1815
}
1816
 
1817
/*-----------------------------------------------------------
1818
 . smc_set_multicast_list
1819
 .
1820
 . This routine will, depending on the values passed to it,
1821
 . either make it accept multicast packets, go into
1822
 . promiscuous mode ( for TCPDUMP and cousins ) or accept
1823
 . a select set of multicast packets
1824
*/
1825
static void smc_set_multicast_list(struct device *dev)
1826
{
1827
        unsigned long ioaddr = dev->base_addr;
1828
 
1829
        PRINTK2("%s:smc_set_multicast_list\n", dev->name);
1830
 
1831
        SMC_SELECT_BANK(0);
1832
        if ( dev->flags & IFF_PROMISC )
1833
                {
1834
                PRINTK2("%s:smc_set_multicast_list:RCR_PRMS\n", dev->name);
1835
                outw( inw(ioaddr + RCR_REG ) | RCR_PRMS, ioaddr + RCR_REG );
1836
                }
1837
 
1838
/* BUG?  I never disable promiscuous mode if multicasting was turned on.
1839
   Now, I turn off promiscuous mode, but I don't do anything to multicasting
1840
   when promiscuous mode is turned on.
1841
*/
1842
 
1843
        /* Here, I am setting this to accept all multicast packets.
1844
           I don't need to zero the multicast table, because the flag is
1845
           checked before the table is
1846
        */
1847
        else if (dev->flags & IFF_ALLMULTI)
1848
                {
1849
                outw( inw(ioaddr + RCR_REG ) | RCR_ALMUL, ioaddr + RCR_REG );
1850
                PRINTK2("%s:smc_set_multicast_list:RCR_ALMUL\n", dev->name);
1851
                }
1852
 
1853
        /* We just get all multicast packets even if we only want them
1854
         . from one source.  This will be changed at some future
1855
         . point. */
1856
        else if (dev->mc_count )  {
1857
                /* support hardware multicasting */
1858
 
1859
                /* be sure I get rid of flags I might have set */
1860
                outw( inw( ioaddr + RCR_REG ) & ~(RCR_PRMS | RCR_ALMUL),
1861
                        ioaddr + RCR_REG );
1862
                /* NOTE: this has to set the bank, so make sure it is the
1863
                   last thing called.  The bank is set to zero at the top */
1864
                smc_setmulticast( ioaddr, dev->mc_count, dev->mc_list );
1865
        } else  {
1866
                PRINTK2("%s:smc_set_multicast_list:~(RCR_PRMS|RCR_ALMUL)\n",
1867
                        dev->name);
1868
                outw( inw( ioaddr + RCR_REG ) & ~(RCR_PRMS | RCR_ALMUL),
1869
                        ioaddr + RCR_REG );
1870
 
1871
                /*
1872
                  since I'm disabling all multicast entirely, I need to
1873
                  clear the multicast list
1874
                */
1875
                SMC_SELECT_BANK( 3 );
1876
                outw( 0, ioaddr + MCAST_REG1 );
1877
                outw( 0, ioaddr + MCAST_REG2 );
1878
                outw( 0, ioaddr + MCAST_REG3 );
1879
                outw( 0, ioaddr + MCAST_REG4 );
1880
        }
1881
}
1882
 
1883
#ifdef MODULE
1884
 
1885
static char devicename[9] = { 0, };
1886
static struct device devSMC91111 = {
1887
        devicename, /* device name is inserted by linux/drivers/net/net_init.c */
1888
        0, 0, 0, 0,
1889
        0, 0,  /* I/O address, IRQ */
1890
        0, 0, 0, NULL, smc_init_91C111, smc_91C111_destructor};
1891
 
1892
int io = 0;
1893
int irq = 0;
1894
int nowait = 0;
1895
 
1896
MODULE_PARM(io, "i");
1897
MODULE_PARM(irq, "i");
1898
MODULE_PARM(nowait, "i");
1899
 
1900
/*------------------------------------------------------------
1901
 . Module initialization function
1902
 .-------------------------------------------------------------*/
1903
int init_module(void)
1904
{
1905
        int result;
1906
 
1907
        PRINTK2(CARDNAME":init_module\n");
1908
 
1909
        if (io == 0)
1910
                printk(KERN_WARNING
1911
                CARDNAME": You shouldn't use auto-probing with insmod!\n" );
1912
 
1913
        /* copy the parameters from insmod into the device structure */
1914
        devSMC91111.base_addr   = io;
1915
        devSMC91111.irq         = irq;
1916
        devSMC91111.dma         = nowait; // Use DMA field for nowait
1917
        if ((result = register_netdev(&devSMC91111)) != 0)
1918
                return result;
1919
 
1920
        return 0;
1921
}
1922
 
1923
/*------------------------------------------------------------
1924
 . Cleanup when module is removed with rmmod
1925
 .-------------------------------------------------------------*/
1926
void cleanup_module(void)
1927
{
1928
        /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
1929
        unregister_netdev(&devSMC91111);
1930
 
1931
        free_irq(devSMC91111.irq, &devSMC91111);
1932
        release_region(devSMC91111.base_addr, SMC_IO_EXTENT);
1933
 
1934
        if (devSMC91111.priv)
1935
                kfree_s(devSMC91111.priv, sizeof(struct smc_local));
1936
}
1937
 
1938
#endif /* MODULE */
1939
 
1940
 
1941
#ifdef CONFIG_SYSCTL
1942
 
1943
 
1944
/*------------------------------------------------------------
1945
 . Modify a bit in the LAN91C111 register set
1946
 .-------------------------------------------------------------*/
1947
static word smc_modify_regbit(int bank, unsigned long ioaddr, int reg,
1948
        unsigned int bit, int val)
1949
{
1950
        word regval;
1951
 
1952
        SMC_SELECT_BANK( bank );
1953
 
1954
        regval = inw( ioaddr+reg );
1955
        if (val)
1956
                regval |= bit;
1957
        else
1958
                regval &= ~bit;
1959
 
1960
        outw( regval, ioaddr );
1961
        return(regval);
1962
}
1963
 
1964
 
1965
/*------------------------------------------------------------
1966
 . Retrieve a bit in the LAN91C111 register set
1967
 .-------------------------------------------------------------*/
1968
static int smc_get_regbit(int bank, unsigned long ioaddr, int reg,
1969
        unsigned int bit)
1970
{
1971
        SMC_SELECT_BANK( bank );
1972
        if ( inw( ioaddr+reg ) & bit)
1973
                return(1);
1974
        else
1975
                return(0);
1976
}
1977
 
1978
 
1979
/*------------------------------------------------------------
1980
 . Modify a LAN91C111 register (word access only)
1981
 .-------------------------------------------------------------*/
1982
static void smc_modify_reg(int bank, unsigned long ioaddr, int reg, word val)
1983
{
1984
        SMC_SELECT_BANK( bank );
1985
        outw( val, ioaddr+reg );
1986
}
1987
 
1988
 
1989
/*------------------------------------------------------------
1990
 . Retrieve a LAN91C111 register (word access only)
1991
 .-------------------------------------------------------------*/
1992
static int smc_get_reg(int bank, unsigned long ioaddr, int reg)
1993
{
1994
        SMC_SELECT_BANK( bank );
1995
        return(inw( ioaddr+reg ));
1996
}
1997
 
1998
 
1999
static const char smc_info_string[] =
2000
"\n"
2001
"info           Provides this information blurb\n"
2002
"swver          Prints the software version information of this driver\n"
2003
"autoneg        Auto-negotiate Mode = 1\n"
2004
"rspeed         Requested Speed, 100=100Mbps, 10=10Mpbs\n"
2005
"rfduplx        Requested Full Duplex Operation\n"
2006
"aspeed         Actual Speed, 100=100Mbps, 10=10Mpbs\n"
2007
"afduplx        Actual Full Duplex Operation\n"
2008
"lnkfail        PHY Link Failure when 1\n"
2009
"miiop          External MII when 1, Internal PHY when 0\n"
2010
"swfdup         Switched Full Duplex Mode (allowed only in MII operation)\n"
2011
"ephloop        EPH Block Loopback\n"
2012
"forcol         Force a collision\n"
2013
"filtcar        Filter leading edge of carrier sense for 12 bit times\n"
2014
"freemem        Free buffer memory in bytes\n"
2015
"totmem         Total buffer memory in bytes\n"
2016
"leda           Output of LED-A (green)\n"
2017
"ledb           Output of LED-B (yellow)\n"
2018
"chiprev        Revision ID of the LAN91C111 chip\n"
2019
"";
2020
 
2021
/*------------------------------------------------------------
2022
 . Sysctl handler for all integer parameters
2023
 .-------------------------------------------------------------*/
2024
static int smc_sysctl_handler(ctl_table *ctl, int write, struct file * filp,
2025
                                void *buffer, size_t *lenp)
2026
{
2027
        struct device *dev = (struct device*)ctl->extra1;
2028
        struct smc_local *lp = (struct smc_local *)ctl->extra2;
2029
        unsigned long ioaddr = dev->base_addr;
2030
        int *valp = ctl->data;
2031
        int val;
2032
        int ret;
2033
 
2034
        // Update parameters from the real registers
2035
        switch (ctl->ctl_name)
2036
        {
2037
        case CTL_SMC_FORCOL:
2038
                *valp = smc_get_regbit(0, ioaddr, TCR_REG, TCR_FORCOL);
2039
                break;
2040
 
2041
        case CTL_SMC_FREEMEM:
2042
                *valp = ( (word)smc_get_reg(0, ioaddr, MIR_REG) >> 8 )
2043
                        * LAN91C111_MEMORY_MULTIPLIER;
2044
                break;
2045
 
2046
 
2047
        case CTL_SMC_TOTMEM:
2048
                *valp = ( smc_get_reg(0, ioaddr, MIR_REG) & (word)0x00ff )
2049
                        * LAN91C111_MEMORY_MULTIPLIER;
2050
                break;
2051
 
2052
        case CTL_SMC_CHIPREV:
2053
                *valp = smc_get_reg(3, ioaddr, REV_REG);
2054
                break;
2055
 
2056
        case CTL_SMC_AFDUPLX:
2057
                *valp = (lp->lastPhy18 & PHY_INT_DPLXDET) ? 1 : 0;
2058
                break;
2059
 
2060
        case CTL_SMC_ASPEED:
2061
                *valp = (lp->lastPhy18 & PHY_INT_SPDDET) ? 100 : 10;
2062
                break;
2063
 
2064
        case CTL_SMC_LNKFAIL:
2065
                *valp = (lp->lastPhy18 & PHY_INT_LNKFAIL) ? 1 : 0;
2066
                break;
2067
 
2068
        case CTL_SMC_LEDA:
2069
                *valp = (lp->rpc_cur_mode >> RPC_LSXA_SHFT) & (word)0x0007;
2070
                break;
2071
 
2072
        case CTL_SMC_LEDB:
2073
                *valp = (lp->rpc_cur_mode >> RPC_LSXB_SHFT) & (word)0x0007;
2074
                break;
2075
 
2076
        case CTL_SMC_MIIOP:
2077
                *valp = smc_get_regbit(1, ioaddr, CONFIG_REG, CONFIG_EXT_PHY);
2078
                break;
2079
 
2080
#ifdef SMC_DEBUG
2081
        case CTL_SMC_REG_BSR:   // Bank Select
2082
                *valp = smc_get_reg(0, ioaddr, BSR_REG);
2083
                break;
2084
 
2085
        case CTL_SMC_REG_TCR:   // Transmit Control
2086
                *valp = smc_get_reg(0, ioaddr, TCR_REG);
2087
                break;
2088
 
2089
        case CTL_SMC_REG_ESR:   // EPH Status
2090
                *valp = smc_get_reg(0, ioaddr, EPH_STATUS_REG);
2091
                break;
2092
 
2093
        case CTL_SMC_REG_RCR:   // Receive Control
2094
                *valp = smc_get_reg(0, ioaddr, RCR_REG);
2095
                break;
2096
 
2097
        case CTL_SMC_REG_CTRR:  // Counter
2098
                *valp = smc_get_reg(0, ioaddr, COUNTER_REG);
2099
                break;
2100
 
2101
        case CTL_SMC_REG_MIR:   // Memory Information
2102
                *valp = smc_get_reg(0, ioaddr, MIR_REG);
2103
                break;
2104
 
2105
        case CTL_SMC_REG_RPCR:  // Receive/Phy Control
2106
                *valp = smc_get_reg(0, ioaddr, RPC_REG);
2107
                break;
2108
 
2109
        case CTL_SMC_REG_CFGR:  // Configuration
2110
                *valp = smc_get_reg(1, ioaddr, CONFIG_REG);
2111
                break;
2112
 
2113
        case CTL_SMC_REG_BAR:   // Base Address
2114
                *valp = smc_get_reg(1, ioaddr, BASE_REG);
2115
                break;
2116
 
2117
        case CTL_SMC_REG_IAR0:  // Individual Address
2118
                *valp = smc_get_reg(1, ioaddr, ADDR0_REG);
2119
                break;
2120
 
2121
        case CTL_SMC_REG_IAR1:  // Individual Address
2122
                *valp = smc_get_reg(1, ioaddr, ADDR1_REG);
2123
                break;
2124
 
2125
        case CTL_SMC_REG_IAR2:  // Individual Address
2126
                *valp = smc_get_reg(1, ioaddr, ADDR2_REG);
2127
                break;
2128
 
2129
        case CTL_SMC_REG_GPR:   // General Purpose
2130
                *valp = smc_get_reg(1, ioaddr, GP_REG);
2131
                break;
2132
 
2133
        case CTL_SMC_REG_CTLR:  // Control
2134
                *valp = smc_get_reg(1, ioaddr, CTL_REG);
2135
                break;
2136
 
2137
        case CTL_SMC_REG_MCR:   // MMU Command
2138
                *valp = smc_get_reg(2, ioaddr, MMU_CMD_REG);
2139
                break;
2140
 
2141
        case CTL_SMC_REG_PNR:   // Packet Number
2142
                *valp = smc_get_reg(2, ioaddr, PN_REG);
2143
                break;
2144
 
2145
        case CTL_SMC_REG_FPR:   // Allocation Result/FIFO Ports
2146
                *valp = smc_get_reg(2, ioaddr, RXFIFO_REG);
2147
                break;
2148
 
2149
        case CTL_SMC_REG_PTR:   // Pointer
2150
                *valp = smc_get_reg(2, ioaddr, PTR_REG);
2151
                break;
2152
 
2153
        case CTL_SMC_REG_DR:    // Data 
2154
                *valp = smc_get_reg(2, ioaddr, DATA_REG);
2155
                break;
2156
 
2157
        case CTL_SMC_REG_ISR:   // Interrupt Status/Mask
2158
                *valp = smc_get_reg(2, ioaddr, INT_REG);
2159
                break;
2160
 
2161
        case CTL_SMC_REG_MTR1:  // Multicast Table Entry 1
2162
                *valp = smc_get_reg(3, ioaddr, MCAST_REG1);
2163
                break;
2164
 
2165
        case CTL_SMC_REG_MTR2:  // Multicast Table Entry 2
2166
                *valp = smc_get_reg(3, ioaddr, MCAST_REG2);
2167
                break;
2168
 
2169
        case CTL_SMC_REG_MTR3:  // Multicast Table Entry 3
2170
                *valp = smc_get_reg(3, ioaddr, MCAST_REG3);
2171
                break;
2172
 
2173
        case CTL_SMC_REG_MTR4:  // Multicast Table Entry 4
2174
                *valp = smc_get_reg(3, ioaddr, MCAST_REG4);
2175
                break;
2176
 
2177
        case CTL_SMC_REG_MIIR:  // Management Interface
2178
                *valp = smc_get_reg(3, ioaddr, MII_REG);
2179
                break;
2180
 
2181
        case CTL_SMC_REG_REVR:  // Revision
2182
                *valp = smc_get_reg(3, ioaddr, REV_REG);
2183
                break;
2184
 
2185
        case CTL_SMC_REG_ERCVR: // Early RCV
2186
                *valp = smc_get_reg(3, ioaddr, ERCV_REG);
2187
                break;
2188
 
2189
        case CTL_SMC_REG_EXTR:  // External
2190
                *valp = smc_get_reg(7, ioaddr, EXT_REG);
2191
                break;
2192
 
2193
        case CTL_SMC_PHY_CTRL:
2194
                *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2195
                        PHY_CNTL_REG);
2196
                break;
2197
 
2198
        case CTL_SMC_PHY_STAT:
2199
                *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2200
                        PHY_STAT_REG);
2201
                break;
2202
 
2203
        case CTL_SMC_PHY_ID1:
2204
                *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2205
                        PHY_ID1_REG);
2206
                break;
2207
 
2208
        case CTL_SMC_PHY_ID2:
2209
                *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2210
                        PHY_ID2_REG);
2211
                break;
2212
 
2213
        case CTL_SMC_PHY_ADC:
2214
                *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2215
                        PHY_AD_REG);
2216
                break;
2217
 
2218
        case CTL_SMC_PHY_REMC:
2219
                *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2220
                        PHY_RMT_REG);
2221
                break;
2222
 
2223
        case CTL_SMC_PHY_CFG1:
2224
                *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2225
                        PHY_CFG1_REG);
2226
                break;
2227
 
2228
        case CTL_SMC_PHY_CFG2:
2229
                *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2230
                        PHY_CFG2_REG);
2231
                break;
2232
 
2233
        case CTL_SMC_PHY_INT:
2234
                *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2235
                        PHY_INT_REG);
2236
                break;
2237
 
2238
        case CTL_SMC_PHY_MASK:
2239
                *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2240
                        PHY_MASK_REG);
2241
                break;
2242
 
2243
#endif // SMC_DEBUG
2244
 
2245
        default:
2246
                // Just ignore unsupported parameters
2247
                break;
2248
        }
2249
 
2250
        // Save old state
2251
        val = *valp;
2252
 
2253
        // Perform the generic integer operation        
2254
        if ((ret = proc_dointvec(ctl, write, filp, buffer, lenp)) != 0)
2255
                return(ret);
2256
 
2257
        // Write changes out to the registers
2258
        if (write && *valp != val) {
2259
 
2260
                val = *valp;
2261
                switch (ctl->ctl_name) {
2262
 
2263
                case CTL_SMC_SWFDUP:
2264
                        if (val)
2265
                                lp->tcr_cur_mode |= TCR_SWFDUP;
2266
                        else
2267
                                lp->tcr_cur_mode &= ~TCR_SWFDUP;
2268
 
2269
                        smc_modify_regbit(0, ioaddr, TCR_REG, TCR_SWFDUP, val);
2270
                        break;
2271
 
2272
                case CTL_SMC_EPHLOOP:
2273
                        if (val)
2274
                                lp->tcr_cur_mode |= TCR_EPH_LOOP;
2275
                        else
2276
                                lp->tcr_cur_mode &= ~TCR_EPH_LOOP;
2277
 
2278
                        smc_modify_regbit(0, ioaddr, TCR_REG, TCR_EPH_LOOP, val);
2279
                        break;
2280
 
2281
                case CTL_SMC_FORCOL:
2282
                        if (val)
2283
                                lp->tcr_cur_mode |= TCR_FORCOL;
2284
                        else
2285
                                lp->tcr_cur_mode &= ~TCR_FORCOL;
2286
 
2287
                        // Update the EPH block
2288
                        smc_modify_regbit(0, ioaddr, TCR_REG, TCR_FORCOL, val);
2289
                        break;
2290
 
2291
                case CTL_SMC_FILTCAR:
2292
                        if (val)
2293
                                lp->rcr_cur_mode |= RCR_FILT_CAR;
2294
                        else
2295
                                lp->rcr_cur_mode &= ~RCR_FILT_CAR;
2296
 
2297
                        // Update the EPH block
2298
                        smc_modify_regbit(0, ioaddr, RCR_REG, RCR_FILT_CAR, val);
2299
                        break;
2300
 
2301
                case CTL_SMC_RFDUPLX:
2302
                        // Disallow changes if in auto-negotiation mode
2303
                        if (lp->ctl_autoneg)
2304
                                break;
2305
 
2306
                        if (val)
2307
                                {
2308
                                lp->rpc_cur_mode |= RPC_DPLX;
2309
                                }
2310
                        else
2311
                                {
2312
                                lp->rpc_cur_mode &= ~RPC_DPLX;
2313
                                }
2314
 
2315
                        // Reconfigure the PHY
2316
                        smc_phy_configure(dev);
2317
 
2318
                        break;
2319
 
2320
                case CTL_SMC_RSPEED:
2321
                        // Disallow changes if in auto-negotiation mode
2322
                        if (lp->ctl_autoneg)
2323
                                break;
2324
 
2325
                        if (val > 10)
2326
                                lp->rpc_cur_mode |= RPC_SPEED;
2327
                        else
2328
                                lp->rpc_cur_mode &= ~RPC_SPEED;
2329
 
2330
                        // Reconfigure the PHY
2331
                        smc_phy_configure(dev);
2332
 
2333
                        break;
2334
 
2335
                case CTL_SMC_AUTONEG:
2336
                        if (val)
2337
                                lp->rpc_cur_mode |= RPC_ANEG;
2338
                        else
2339
                                lp->rpc_cur_mode &= ~RPC_ANEG;
2340
 
2341
                        // Reconfigure the PHY
2342
                        smc_phy_configure(dev);
2343
 
2344
                        break;
2345
 
2346
                case CTL_SMC_LEDA:
2347
                        val &= 0x07; // Restrict to 3 ls bits
2348
                        lp->rpc_cur_mode &= ~(word)(0x07<<RPC_LSXA_SHFT);
2349
                        lp->rpc_cur_mode |= (word)(val<<RPC_LSXA_SHFT);
2350
 
2351
                        // Update the Internal PHY block
2352
                        smc_modify_reg(0, ioaddr, RPC_REG, lp->rpc_cur_mode);
2353
                        break;
2354
 
2355
                case CTL_SMC_LEDB:
2356
                        val &= 0x07; // Restrict to 3 ls bits
2357
                        lp->rpc_cur_mode &= ~(word)(0x07<<RPC_LSXB_SHFT);
2358
                        lp->rpc_cur_mode |= (word)(val<<RPC_LSXB_SHFT);
2359
 
2360
                        // Update the Internal PHY block
2361
                        smc_modify_reg(0, ioaddr, RPC_REG, lp->rpc_cur_mode);
2362
                        break;
2363
 
2364
                case CTL_SMC_MIIOP:
2365
                        // Update the Internal PHY block
2366
                        smc_modify_regbit(1, ioaddr, CONFIG_REG,
2367
                                CONFIG_EXT_PHY, val);
2368
                        break;
2369
 
2370
#ifdef SMC_DEBUG
2371
                case CTL_SMC_REG_BSR:   // Bank Select
2372
                        smc_modify_reg(0, ioaddr, BSR_REG, val);
2373
                        break;
2374
 
2375
                case CTL_SMC_REG_TCR:   // Transmit Control
2376
                        smc_modify_reg(0, ioaddr, TCR_REG, val);
2377
                        break;
2378
 
2379
                case CTL_SMC_REG_ESR:   // EPH Status
2380
                        smc_modify_reg(0, ioaddr, EPH_STATUS_REG, val);
2381
                        break;
2382
 
2383
                case CTL_SMC_REG_RCR:   // Receive Control
2384
                        smc_modify_reg(0, ioaddr, RCR_REG, val);
2385
                        break;
2386
 
2387
                case CTL_SMC_REG_CTRR:  // Counter
2388
                        smc_modify_reg(0, ioaddr, COUNTER_REG, val);
2389
                        break;
2390
 
2391
                case CTL_SMC_REG_MIR:   // Memory Information
2392
                        smc_modify_reg(0, ioaddr, MIR_REG, val);
2393
                        break;
2394
 
2395
                case CTL_SMC_REG_RPCR:  // Receive/Phy Control
2396
                        smc_modify_reg(0, ioaddr, RPC_REG, val);
2397
                        break;
2398
 
2399
                case CTL_SMC_REG_CFGR:  // Configuration
2400
                        smc_modify_reg(1, ioaddr, CONFIG_REG, val);
2401
                        break;
2402
 
2403
                case CTL_SMC_REG_BAR:   // Base Address
2404
                        smc_modify_reg(1, ioaddr, BASE_REG, val);
2405
                        break;
2406
 
2407
                case CTL_SMC_REG_IAR0:  // Individual Address
2408
                        smc_modify_reg(1, ioaddr, ADDR0_REG, val);
2409
                        break;
2410
 
2411
                case CTL_SMC_REG_IAR1:  // Individual Address
2412
                        smc_modify_reg(1, ioaddr, ADDR1_REG, val);
2413
                        break;
2414
 
2415
                case CTL_SMC_REG_IAR2:  // Individual Address
2416
                        smc_modify_reg(1, ioaddr, ADDR2_REG, val);
2417
                        break;
2418
 
2419
                case CTL_SMC_REG_GPR:   // General Purpose
2420
                        smc_modify_reg(1, ioaddr, GP_REG, val);
2421
                        break;
2422
 
2423
                case CTL_SMC_REG_CTLR:  // Control
2424
                        smc_modify_reg(1, ioaddr, CTL_REG, val);
2425
                        break;
2426
 
2427
                case CTL_SMC_REG_MCR:   // MMU Command
2428
                        smc_modify_reg(2, ioaddr, MMU_CMD_REG, val);
2429
                        break;
2430
 
2431
                case CTL_SMC_REG_PNR:   // Packet Number
2432
                        smc_modify_reg(2, ioaddr, PN_REG, val);
2433
                        break;
2434
 
2435
                case CTL_SMC_REG_FPR:   // Allocation Result/FIFO Ports
2436
                        smc_modify_reg(2, ioaddr, RXFIFO_REG, val);
2437
                        break;
2438
 
2439
                case CTL_SMC_REG_PTR:   // Pointer
2440
                        smc_modify_reg(2, ioaddr, PTR_REG, val);
2441
                        break;
2442
 
2443
                case CTL_SMC_REG_DR:    // Data 
2444
                        smc_modify_reg(2, ioaddr, DATA_REG, val);
2445
                        break;
2446
 
2447
                case CTL_SMC_REG_ISR:   // Interrupt Status/Mask
2448
                        smc_modify_reg(2, ioaddr, INT_REG, val);
2449
                        break;
2450
 
2451
                case CTL_SMC_REG_MTR1:  // Multicast Table Entry 1
2452
                        smc_modify_reg(3, ioaddr, MCAST_REG1, val);
2453
                        break;
2454
 
2455
                case CTL_SMC_REG_MTR2:  // Multicast Table Entry 2
2456
                        smc_modify_reg(3, ioaddr, MCAST_REG2, val);
2457
                        break;
2458
 
2459
                case CTL_SMC_REG_MTR3:  // Multicast Table Entry 3
2460
                        smc_modify_reg(3, ioaddr, MCAST_REG3, val);
2461
                        break;
2462
 
2463
                case CTL_SMC_REG_MTR4:  // Multicast Table Entry 4
2464
                        smc_modify_reg(3, ioaddr, MCAST_REG4, val);
2465
                        break;
2466
 
2467
                case CTL_SMC_REG_MIIR:  // Management Interface
2468
                        smc_modify_reg(3, ioaddr, MII_REG, val);
2469
                        break;
2470
 
2471
                case CTL_SMC_REG_REVR:  // Revision
2472
                        smc_modify_reg(3, ioaddr, REV_REG, val);
2473
                        break;
2474
 
2475
                case CTL_SMC_REG_ERCVR: // Early RCV
2476
                        smc_modify_reg(3, ioaddr, ERCV_REG, val);
2477
                        break;
2478
 
2479
                case CTL_SMC_REG_EXTR:  // External
2480
                        smc_modify_reg(7, ioaddr, EXT_REG, val);
2481
                        break;
2482
 
2483
                case CTL_SMC_PHY_CTRL:
2484
                        smc_write_phy_register(ioaddr, lp->phyaddr,
2485
                                PHY_CNTL_REG, val);
2486
                        break;
2487
 
2488
                case CTL_SMC_PHY_STAT:
2489
                        smc_write_phy_register(ioaddr, lp->phyaddr,
2490
                                PHY_STAT_REG, val);
2491
                        break;
2492
 
2493
                case CTL_SMC_PHY_ID1:
2494
                        smc_write_phy_register(ioaddr, lp->phyaddr,
2495
                                PHY_ID1_REG, val);
2496
                        break;
2497
 
2498
                case CTL_SMC_PHY_ID2:
2499
                        smc_write_phy_register(ioaddr, lp->phyaddr,
2500
                                PHY_ID2_REG, val);
2501
                        break;
2502
 
2503
                case CTL_SMC_PHY_ADC:
2504
                        smc_write_phy_register(ioaddr, lp->phyaddr,
2505
                                PHY_AD_REG, val);
2506
                        break;
2507
 
2508
                case CTL_SMC_PHY_REMC:
2509
                        smc_write_phy_register(ioaddr, lp->phyaddr,
2510
                                PHY_RMT_REG, val);
2511
                        break;
2512
 
2513
                case CTL_SMC_PHY_CFG1:
2514
                        smc_write_phy_register(ioaddr, lp->phyaddr,
2515
                                PHY_CFG1_REG, val);
2516
                        break;
2517
 
2518
                case CTL_SMC_PHY_CFG2:
2519
                        smc_write_phy_register(ioaddr, lp->phyaddr,
2520
                                PHY_CFG2_REG, val);
2521
                        break;
2522
 
2523
                case CTL_SMC_PHY_INT:
2524
                        smc_write_phy_register(ioaddr, lp->phyaddr,
2525
                                PHY_INT_REG, val);
2526
                        break;
2527
 
2528
                case CTL_SMC_PHY_MASK:
2529
                        smc_write_phy_register(ioaddr, lp->phyaddr,
2530
                                PHY_MASK_REG, val);
2531
                        break;
2532
 
2533
#endif // SMC_DEBUG
2534
 
2535
                default:
2536
                        // Just ignore unsupported parameters
2537
                        break;
2538
                } // end switch
2539
 
2540
        } // end if
2541
 
2542
        return ret;
2543
}
2544
 
2545
 
2546
#ifdef MODULE
2547
/*
2548
 * This is called as the fill_inode function when an inode
2549
 * is going into (fill = 1) or out of service (fill = 0).
2550
 * We use it here to manage the module use counts.
2551
 *
2552
 * Note: only the top-level directory needs to do this; if
2553
 * a lower level is referenced, the parent will be as well.
2554
 */
2555
static void smc_procfs_modcount(struct inode *inode, int fill)
2556
{
2557
        if (fill) {
2558
                MOD_INC_USE_COUNT;
2559
        } else {
2560
                MOD_DEC_USE_COUNT;
2561
        }
2562
}
2563
#endif // MODULE
2564
 
2565
/*------------------------------------------------------------
2566
 . Sysctl registration function for all parameters (files)
2567
 .-------------------------------------------------------------*/
2568
static void smc_sysctl_register(struct device *dev)
2569
{
2570
        struct smc_local *lp = (struct smc_local *)dev->priv;
2571
        //static int ctl_name = CTL_SMC;
2572
        static int ctl_name = "SMC91111";
2573
        ctl_table* ct;
2574
        int i;
2575
 
2576
        // Make sure the ctl_tables start out as all zeros
2577
        memset(lp->root_table, 0, sizeof lp->root_table);
2578
        memset(lp->eth_table, 0, sizeof lp->eth_table);
2579
        memset(lp->param_table, 0, sizeof lp->param_table);
2580
 
2581
        // Initialize the root table
2582
        ct = lp->root_table;
2583
        ct->ctl_name = CTL_DEV;
2584
        ct->procname = "dev";
2585
        ct->maxlen = 0;
2586
        ct->mode = 0555;
2587
        ct->child = lp->eth_table;
2588
        // remaining fields are zero
2589
 
2590
        // Initialize the ethX table (this device's table)
2591
        ct = lp->eth_table;
2592
        ct->ctl_name = ctl_name++; // Must be unique
2593
        ct->procname = dev->name;
2594
        ct->maxlen = 0;
2595
        ct->mode = 0555;
2596
        ct->child = lp->param_table;
2597
        // remaining fields are zero
2598
 
2599
        // Initialize the parameter (files) table
2600
        // Make sure the last entry remains null
2601
        ct = lp->param_table;
2602
        for (i = 0; i < (CTL_SMC_LAST_ENTRY-1); ++i)
2603
                {
2604
                // Initialize fields common to all table entries
2605
                ct[i].proc_handler = smc_sysctl_handler;
2606
                ct[i].extra1 = (void*)dev; // Save our device pointer
2607
                ct[i].extra2 = (void*)lp;  // Save our smc_local data pointer
2608
                }
2609
 
2610
        // INFO - this is our only string parameter
2611
        i = 0;
2612
        ct[i].proc_handler = proc_dostring; // use default handler
2613
        ct[i].ctl_name = CTL_SMC_INFO;
2614
        ct[i].procname = "info";
2615
        ct[i].data = (void*)smc_info_string;
2616
        ct[i].maxlen = sizeof smc_info_string;
2617
        ct[i].mode = 0444; // Read only
2618
 
2619
        // SWVER
2620
        ++i;
2621
        ct[i].proc_handler = proc_dostring; // use default handler
2622
        ct[i].ctl_name = CTL_SMC_SWVER;
2623
        ct[i].procname = "swver";
2624
        ct[i].data = (void*)version;
2625
        ct[i].maxlen = sizeof version;
2626
        ct[i].mode = 0444; // Read only
2627
 
2628
        // SWFDUP
2629
        ++i;
2630
        ct[i].ctl_name = CTL_SMC_SWFDUP;
2631
        ct[i].procname = "swfdup";
2632
        ct[i].data = (void*)&(lp->ctl_swfdup);
2633
        ct[i].maxlen = sizeof lp->ctl_swfdup;
2634
        ct[i].mode = 0644; // Read by all, write by root
2635
 
2636
        // EPHLOOP
2637
        ++i;
2638
        ct[i].ctl_name = CTL_SMC_EPHLOOP;
2639
        ct[i].procname = "ephloop";
2640
        ct[i].data = (void*)&(lp->ctl_ephloop);
2641
        ct[i].maxlen = sizeof lp->ctl_ephloop;
2642
        ct[i].mode = 0644; // Read by all, write by root
2643
 
2644
        // MIIOP
2645
        ++i;
2646
        ct[i].ctl_name = CTL_SMC_MIIOP;
2647
        ct[i].procname = "miiop";
2648
        ct[i].data = (void*)&(lp->ctl_miiop);
2649
        ct[i].maxlen = sizeof lp->ctl_miiop;
2650
        ct[i].mode = 0644; // Read by all, write by root
2651
 
2652
        // AUTONEG
2653
        ++i;
2654
        ct[i].ctl_name = CTL_SMC_AUTONEG;
2655
        ct[i].procname = "autoneg";
2656
        ct[i].data = (void*)&(lp->ctl_autoneg);
2657
        ct[i].maxlen = sizeof lp->ctl_autoneg;
2658
        ct[i].mode = 0644; // Read by all, write by root
2659
 
2660
        // RFDUPLX
2661
        ++i;
2662
        ct[i].ctl_name = CTL_SMC_RFDUPLX;
2663
        ct[i].procname = "rfduplx";
2664
        ct[i].data = (void*)&(lp->ctl_rfduplx);
2665
        ct[i].maxlen = sizeof lp->ctl_rfduplx;
2666
        ct[i].mode = 0644; // Read by all, write by root
2667
 
2668
        // RSPEED
2669
        ++i;
2670
        ct[i].ctl_name = CTL_SMC_RSPEED;
2671
        ct[i].procname = "rspeed";
2672
        ct[i].data = (void*)&(lp->ctl_rspeed);
2673
        ct[i].maxlen = sizeof lp->ctl_rspeed;
2674
        ct[i].mode = 0644; // Read by all, write by root
2675
 
2676
        // AFDUPLX
2677
        ++i;
2678
        ct[i].ctl_name = CTL_SMC_AFDUPLX;
2679
        ct[i].procname = "afduplx";
2680
        ct[i].data = (void*)&(lp->ctl_afduplx);
2681
        ct[i].maxlen = sizeof lp->ctl_afduplx;
2682
        ct[i].mode = 0444; // Read only
2683
 
2684
        // ASPEED
2685
        ++i;
2686
        ct[i].ctl_name = CTL_SMC_ASPEED;
2687
        ct[i].procname = "aspeed";
2688
        ct[i].data = (void*)&(lp->ctl_aspeed);
2689
        ct[i].maxlen = sizeof lp->ctl_aspeed;
2690
        ct[i].mode = 0444; // Read only
2691
 
2692
        // LNKFAIL
2693
        ++i;
2694
        ct[i].ctl_name = CTL_SMC_LNKFAIL;
2695
        ct[i].procname = "lnkfail";
2696
        ct[i].data = (void*)&(lp->ctl_lnkfail);
2697
        ct[i].maxlen = sizeof lp->ctl_lnkfail;
2698
        ct[i].mode = 0444; // Read only
2699
 
2700
        // FORCOL
2701
        ++i;
2702
        ct[i].ctl_name = CTL_SMC_FORCOL;
2703
        ct[i].procname = "forcol";
2704
        ct[i].data = (void*)&(lp->ctl_forcol);
2705
        ct[i].maxlen = sizeof lp->ctl_forcol;
2706
        ct[i].mode = 0644; // Read by all, write by root
2707
 
2708
        // FILTCAR
2709
        ++i;
2710
        ct[i].ctl_name = CTL_SMC_FILTCAR;
2711
        ct[i].procname = "filtcar";
2712
        ct[i].data = (void*)&(lp->ctl_filtcar);
2713
        ct[i].maxlen = sizeof lp->ctl_filtcar;
2714
        ct[i].mode = 0644; // Read by all, write by root
2715
 
2716
        // FREEMEM
2717
        ++i;
2718
        ct[i].ctl_name = CTL_SMC_FREEMEM;
2719
        ct[i].procname = "freemem";
2720
        ct[i].data = (void*)&(lp->ctl_freemem);
2721
        ct[i].maxlen = sizeof lp->ctl_freemem;
2722
        ct[i].mode = 0444; // Read only
2723
 
2724
        // TOTMEM
2725
        ++i;
2726
        ct[i].ctl_name = CTL_SMC_TOTMEM;
2727
        ct[i].procname = "totmem";
2728
        ct[i].data = (void*)&(lp->ctl_totmem);
2729
        ct[i].maxlen = sizeof lp->ctl_totmem;
2730
        ct[i].mode = 0444; // Read only
2731
 
2732
        // LEDA
2733
        ++i;
2734
        ct[i].ctl_name = CTL_SMC_LEDA;
2735
        ct[i].procname = "leda";
2736
        ct[i].data = (void*)&(lp->ctl_leda);
2737
        ct[i].maxlen = sizeof lp->ctl_leda;
2738
        ct[i].mode = 0644; // Read by all, write by root
2739
 
2740
        // LEDB
2741
        ++i;
2742
        ct[i].ctl_name = CTL_SMC_LEDB;
2743
        ct[i].procname = "ledb";
2744
        ct[i].data = (void*)&(lp->ctl_ledb);
2745
        ct[i].maxlen = sizeof lp->ctl_ledb;
2746
        ct[i].mode = 0644; // Read by all, write by root
2747
 
2748
        // CHIPREV
2749
        ++i;
2750
        ct[i].ctl_name = CTL_SMC_CHIPREV;
2751
        ct[i].procname = "chiprev";
2752
        ct[i].data = (void*)&(lp->ctl_chiprev);
2753
        ct[i].maxlen = sizeof lp->ctl_chiprev;
2754
        ct[i].mode = 0444; // Read only
2755
 
2756
#ifdef SMC_DEBUG
2757
        // REG_BSR
2758
        ++i;
2759
        ct[i].ctl_name = CTL_SMC_REG_BSR;
2760
        ct[i].procname = "reg_bsr";
2761
        ct[i].data = (void*)&(lp->ctl_reg_bsr);
2762
        ct[i].maxlen = sizeof lp->ctl_reg_bsr;
2763
        ct[i].mode = 0644; // Read by all, write by root
2764
 
2765
        // REG_TCR
2766
        ++i;
2767
        ct[i].ctl_name = CTL_SMC_REG_TCR;
2768
        ct[i].procname = "reg_tcr";
2769
        ct[i].data = (void*)&(lp->ctl_reg_tcr);
2770
        ct[i].maxlen = sizeof lp->ctl_reg_tcr;
2771
        ct[i].mode = 0644; // Read by all, write by root
2772
 
2773
        // REG_ESR
2774
        ++i;
2775
        ct[i].ctl_name = CTL_SMC_REG_ESR;
2776
        ct[i].procname = "reg_esr";
2777
        ct[i].data = (void*)&(lp->ctl_reg_esr);
2778
        ct[i].maxlen = sizeof lp->ctl_reg_esr;
2779
        ct[i].mode = 0644; // Read by all, write by root
2780
 
2781
        // REG_RCR
2782
        ++i;
2783
        ct[i].ctl_name = CTL_SMC_REG_RCR;
2784
        ct[i].procname = "reg_rcr";
2785
        ct[i].data = (void*)&(lp->ctl_reg_rcr);
2786
        ct[i].maxlen = sizeof lp->ctl_reg_rcr;
2787
        ct[i].mode = 0644; // Read by all, write by root
2788
 
2789
        // REG_CTRR
2790
        ++i;
2791
        ct[i].ctl_name = CTL_SMC_REG_CTRR;
2792
        ct[i].procname = "reg_ctrr";
2793
        ct[i].data = (void*)&(lp->ctl_reg_ctrr);
2794
        ct[i].maxlen = sizeof lp->ctl_reg_ctrr;
2795
        ct[i].mode = 0644; // Read by all, write by root
2796
 
2797
        // REG_MIR
2798
        ++i;
2799
        ct[i].ctl_name = CTL_SMC_REG_MIR;
2800
        ct[i].procname = "reg_mir";
2801
        ct[i].data = (void*)&(lp->ctl_reg_mir);
2802
        ct[i].maxlen = sizeof lp->ctl_reg_mir;
2803
        ct[i].mode = 0644; // Read by all, write by root
2804
 
2805
        // REG_RPCR
2806
        ++i;
2807
        ct[i].ctl_name = CTL_SMC_REG_RPCR;
2808
        ct[i].procname = "reg_rpcr";
2809
        ct[i].data = (void*)&(lp->ctl_reg_rpcr);
2810
        ct[i].maxlen = sizeof lp->ctl_reg_rpcr;
2811
        ct[i].mode = 0644; // Read by all, write by root
2812
 
2813
        // REG_CFGR
2814
        ++i;
2815
        ct[i].ctl_name = CTL_SMC_REG_CFGR;
2816
        ct[i].procname = "reg_cfgr";
2817
        ct[i].data = (void*)&(lp->ctl_reg_cfgr);
2818
        ct[i].maxlen = sizeof lp->ctl_reg_cfgr;
2819
        ct[i].mode = 0644; // Read by all, write by root
2820
 
2821
        // REG_BAR
2822
        ++i;
2823
        ct[i].ctl_name = CTL_SMC_REG_BAR;
2824
        ct[i].procname = "reg_bar";
2825
        ct[i].data = (void*)&(lp->ctl_reg_bar);
2826
        ct[i].maxlen = sizeof lp->ctl_reg_bar;
2827
        ct[i].mode = 0644; // Read by all, write by root
2828
 
2829
        // REG_IAR0
2830
        ++i;
2831
        ct[i].ctl_name = CTL_SMC_REG_IAR0;
2832
        ct[i].procname = "reg_iar0";
2833
        ct[i].data = (void*)&(lp->ctl_reg_iar0);
2834
        ct[i].maxlen = sizeof lp->ctl_reg_iar0;
2835
        ct[i].mode = 0644; // Read by all, write by root
2836
 
2837
        // REG_IAR1
2838
        ++i;
2839
        ct[i].ctl_name = CTL_SMC_REG_IAR1;
2840
        ct[i].procname = "reg_iar1";
2841
        ct[i].data = (void*)&(lp->ctl_reg_iar1);
2842
        ct[i].maxlen = sizeof lp->ctl_reg_iar1;
2843
        ct[i].mode = 0644; // Read by all, write by root
2844
 
2845
        // REG_IAR2
2846
        ++i;
2847
        ct[i].ctl_name = CTL_SMC_REG_IAR2;
2848
        ct[i].procname = "reg_iar2";
2849
        ct[i].data = (void*)&(lp->ctl_reg_iar2);
2850
        ct[i].maxlen = sizeof lp->ctl_reg_iar2;
2851
        ct[i].mode = 0644; // Read by all, write by root
2852
 
2853
        // REG_GPR
2854
        ++i;
2855
        ct[i].ctl_name = CTL_SMC_REG_GPR;
2856
        ct[i].procname = "reg_gpr";
2857
        ct[i].data = (void*)&(lp->ctl_reg_gpr);
2858
        ct[i].maxlen = sizeof lp->ctl_reg_gpr;
2859
        ct[i].mode = 0644; // Read by all, write by root
2860
 
2861
        // REG_CTLR
2862
        ++i;
2863
        ct[i].ctl_name = CTL_SMC_REG_CTLR;
2864
        ct[i].procname = "reg_ctlr";
2865
        ct[i].data = (void*)&(lp->ctl_reg_ctlr);
2866
        ct[i].maxlen = sizeof lp->ctl_reg_ctlr;
2867
        ct[i].mode = 0644; // Read by all, write by root
2868
 
2869
        // REG_MCR
2870
        ++i;
2871
        ct[i].ctl_name = CTL_SMC_REG_MCR;
2872
        ct[i].procname = "reg_mcr";
2873
        ct[i].data = (void*)&(lp->ctl_reg_mcr);
2874
        ct[i].maxlen = sizeof lp->ctl_reg_mcr;
2875
        ct[i].mode = 0644; // Read by all, write by root
2876
 
2877
        // REG_PNR
2878
        ++i;
2879
        ct[i].ctl_name = CTL_SMC_REG_PNR;
2880
        ct[i].procname = "reg_pnr";
2881
        ct[i].data = (void*)&(lp->ctl_reg_pnr);
2882
        ct[i].maxlen = sizeof lp->ctl_reg_pnr;
2883
        ct[i].mode = 0644; // Read by all, write by root
2884
 
2885
        // REG_FPR
2886
        ++i;
2887
        ct[i].ctl_name = CTL_SMC_REG_FPR;
2888
        ct[i].procname = "reg_fpr";
2889
        ct[i].data = (void*)&(lp->ctl_reg_fpr);
2890
        ct[i].maxlen = sizeof lp->ctl_reg_fpr;
2891
        ct[i].mode = 0644; // Read by all, write by root
2892
 
2893
        // REG_PTR
2894
        ++i;
2895
        ct[i].ctl_name = CTL_SMC_REG_PTR;
2896
        ct[i].procname = "reg_ptr";
2897
        ct[i].data = (void*)&(lp->ctl_reg_ptr);
2898
        ct[i].maxlen = sizeof lp->ctl_reg_ptr;
2899
        ct[i].mode = 0644; // Read by all, write by root
2900
 
2901
        // REG_DR
2902
        ++i;
2903
        ct[i].ctl_name = CTL_SMC_REG_DR;
2904
        ct[i].procname = "reg_dr";
2905
        ct[i].data = (void*)&(lp->ctl_reg_dr);
2906
        ct[i].maxlen = sizeof lp->ctl_reg_dr;
2907
        ct[i].mode = 0644; // Read by all, write by root
2908
 
2909
        // REG_ISR
2910
        ++i;
2911
        ct[i].ctl_name = CTL_SMC_REG_ISR;
2912
        ct[i].procname = "reg_isr";
2913
        ct[i].data = (void*)&(lp->ctl_reg_isr);
2914
        ct[i].maxlen = sizeof lp->ctl_reg_isr;
2915
        ct[i].mode = 0644; // Read by all, write by root
2916
 
2917
        // REG_MTR1
2918
        ++i;
2919
        ct[i].ctl_name = CTL_SMC_REG_MTR1;
2920
        ct[i].procname = "reg_mtr1";
2921
        ct[i].data = (void*)&(lp->ctl_reg_mtr1);
2922
        ct[i].maxlen = sizeof lp->ctl_reg_mtr1;
2923
        ct[i].mode = 0644; // Read by all, write by root
2924
 
2925
        // REG_MTR2
2926
        ++i;
2927
        ct[i].ctl_name = CTL_SMC_REG_MTR2;
2928
        ct[i].procname = "reg_mtr2";
2929
        ct[i].data = (void*)&(lp->ctl_reg_mtr2);
2930
        ct[i].maxlen = sizeof lp->ctl_reg_mtr2;
2931
        ct[i].mode = 0644; // Read by all, write by root
2932
 
2933
        // REG_MTR3
2934
        ++i;
2935
        ct[i].ctl_name = CTL_SMC_REG_MTR3;
2936
        ct[i].procname = "reg_mtr3";
2937
        ct[i].data = (void*)&(lp->ctl_reg_mtr3);
2938
        ct[i].maxlen = sizeof lp->ctl_reg_mtr3;
2939
        ct[i].mode = 0644; // Read by all, write by root
2940
 
2941
        // REG_MTR4
2942
        ++i;
2943
        ct[i].ctl_name = CTL_SMC_REG_MTR4;
2944
        ct[i].procname = "reg_mtr4";
2945
        ct[i].data = (void*)&(lp->ctl_reg_mtr4);
2946
        ct[i].maxlen = sizeof lp->ctl_reg_mtr4;
2947
        ct[i].mode = 0644; // Read by all, write by root
2948
 
2949
        // REG_MIIR
2950
        ++i;
2951
        ct[i].ctl_name = CTL_SMC_REG_MIIR;
2952
        ct[i].procname = "reg_miir";
2953
        ct[i].data = (void*)&(lp->ctl_reg_miir);
2954
        ct[i].maxlen = sizeof lp->ctl_reg_miir;
2955
        ct[i].mode = 0644; // Read by all, write by root
2956
 
2957
        // REG_REVR
2958
        ++i;
2959
        ct[i].ctl_name = CTL_SMC_REG_REVR;
2960
        ct[i].procname = "reg_revr";
2961
        ct[i].data = (void*)&(lp->ctl_reg_revr);
2962
        ct[i].maxlen = sizeof lp->ctl_reg_revr;
2963
        ct[i].mode = 0644; // Read by all, write by root
2964
 
2965
        // REG_ERCVR
2966
        ++i;
2967
        ct[i].ctl_name = CTL_SMC_REG_ERCVR;
2968
        ct[i].procname = "reg_ercvr";
2969
        ct[i].data = (void*)&(lp->ctl_reg_ercvr);
2970
        ct[i].maxlen = sizeof lp->ctl_reg_ercvr;
2971
        ct[i].mode = 0644; // Read by all, write by root
2972
 
2973
        // REG_EXTR
2974
        ++i;
2975
        ct[i].ctl_name = CTL_SMC_REG_EXTR;
2976
        ct[i].procname = "reg_extr";
2977
        ct[i].data = (void*)&(lp->ctl_reg_extr);
2978
        ct[i].maxlen = sizeof lp->ctl_reg_extr;
2979
        ct[i].mode = 0644; // Read by all, write by root
2980
 
2981
        // PHY Control
2982
        ++i;
2983
        ct[i].ctl_name = CTL_SMC_PHY_CTRL;
2984
        ct[i].procname = "phy_ctrl";
2985
        ct[i].data = (void*)&(lp->ctl_phy_ctrl);
2986
        ct[i].maxlen = sizeof lp->ctl_phy_ctrl;
2987
        ct[i].mode = 0644; // Read by all, write by root
2988
 
2989
        // PHY Status
2990
        ++i;
2991
        ct[i].ctl_name = CTL_SMC_PHY_STAT;
2992
        ct[i].procname = "phy_stat";
2993
        ct[i].data = (void*)&(lp->ctl_phy_stat);
2994
        ct[i].maxlen = sizeof lp->ctl_phy_stat;
2995
        ct[i].mode = 0644; // Read by all, write by root
2996
 
2997
        // PHY ID1
2998
        ++i;
2999
        ct[i].ctl_name = CTL_SMC_PHY_ID1;
3000
        ct[i].procname = "phy_id1";
3001
        ct[i].data = (void*)&(lp->ctl_phy_id1);
3002
        ct[i].maxlen = sizeof lp->ctl_phy_id1;
3003
        ct[i].mode = 0644; // Read by all, write by root
3004
 
3005
        // PHY ID2
3006
        ++i;
3007
        ct[i].ctl_name = CTL_SMC_PHY_ID2;
3008
        ct[i].procname = "phy_id2";
3009
        ct[i].data = (void*)&(lp->ctl_phy_id2);
3010
        ct[i].maxlen = sizeof lp->ctl_phy_id2;
3011
        ct[i].mode = 0644; // Read by all, write by root
3012
 
3013
        // PHY Advertise Capabilities
3014
        ++i;
3015
        ct[i].ctl_name = CTL_SMC_PHY_ADC;
3016
        ct[i].procname = "phy_adc";
3017
        ct[i].data = (void*)&(lp->ctl_phy_adc);
3018
        ct[i].maxlen = sizeof lp->ctl_phy_adc;
3019
        ct[i].mode = 0644; // Read by all, write by root
3020
 
3021
        // PHY Remote Capabilities
3022
        ++i;
3023
        ct[i].ctl_name = CTL_SMC_PHY_REMC;
3024
        ct[i].procname = "phy_remc";
3025
        ct[i].data = (void*)&(lp->ctl_phy_remc);
3026
        ct[i].maxlen = sizeof lp->ctl_phy_remc;
3027
        ct[i].mode = 0644; // Read by all, write by root
3028
 
3029
        // PHY Configuration 1
3030
        ++i;
3031
        ct[i].ctl_name = CTL_SMC_PHY_CFG1;
3032
        ct[i].procname = "phy_cfg1";
3033
        ct[i].data = (void*)&(lp->ctl_phy_cfg1);
3034
        ct[i].maxlen = sizeof lp->ctl_phy_cfg1;
3035
        ct[i].mode = 0644; // Read by all, write by root
3036
 
3037
        // PHY Configuration 2
3038
        ++i;
3039
        ct[i].ctl_name = CTL_SMC_PHY_CFG2;
3040
        ct[i].procname = "phy_cfg2";
3041
        ct[i].data = (void*)&(lp->ctl_phy_cfg2);
3042
        ct[i].maxlen = sizeof lp->ctl_phy_cfg2;
3043
        ct[i].mode = 0644; // Read by all, write by root
3044
 
3045
        // PHY Interrupt/Status Output
3046
        ++i;
3047
        ct[i].ctl_name = CTL_SMC_PHY_INT;
3048
        ct[i].procname = "phy_int";
3049
        ct[i].data = (void*)&(lp->ctl_phy_int);
3050
        ct[i].maxlen = sizeof lp->ctl_phy_int;
3051
        ct[i].mode = 0644; // Read by all, write by root
3052
 
3053
        // PHY Interrupt/Status Mask
3054
        ++i;
3055
        ct[i].ctl_name = CTL_SMC_PHY_MASK;
3056
        ct[i].procname = "phy_mask";
3057
        ct[i].data = (void*)&(lp->ctl_phy_mask);
3058
        ct[i].maxlen = sizeof lp->ctl_phy_mask;
3059
        ct[i].mode = 0644; // Read by all, write by root
3060
 
3061
#endif // SMC_DEBUG
3062
 
3063
        // Register /proc/sys/dev/ethX
3064
        lp->sysctl_header = register_sysctl_table(lp->root_table, 1);
3065
 
3066
#ifdef MODULE
3067
        // Register our modcount function which adjusts the module count
3068
        lp->root_table->child->de->fill_inode = smc_procfs_modcount;
3069
#endif // MODULE
3070
 
3071
}
3072
 
3073
 
3074
/*------------------------------------------------------------
3075
 . Sysctl unregistration when driver is closed
3076
 .-------------------------------------------------------------*/
3077
static void smc_sysctl_unregister(struct device *dev)
3078
{
3079
        struct smc_local *lp = (struct smc_local *)dev->priv;
3080
 
3081
        unregister_sysctl_table(lp->sysctl_header);
3082
}
3083
 
3084
#endif /* endif CONFIG_SYSCTL */
3085
 
3086
 
3087
//---PHY CONTROL AND CONFIGURATION-----------------------------------------
3088
 
3089
 
3090
/*------------------------------------------------------------
3091
 . Debugging function for viewing MII Management serial bitstream
3092
 .-------------------------------------------------------------*/
3093
#if (SMC_DEBUG > 2 )
3094
static void smc_dump_mii_stream(byte* bits, int size)
3095
{
3096
#if (SMC_DEBUG > 3 )
3097
        int i;
3098
 
3099
        printk("BIT#:");
3100
        for (i = 0; i < size; ++i)
3101
                {
3102
                printk("%d", i%10);
3103
                }
3104
 
3105
        printk("\nMDOE:");
3106
        for (i = 0; i < size; ++i)
3107
                {
3108
                if (bits[i] & MII_MDOE)
3109
                        printk("1");
3110
                else
3111
                        printk("0");
3112
                }
3113
 
3114
        printk("\nMDO :");
3115
        for (i = 0; i < size; ++i)
3116
                {
3117
                if (bits[i] & MII_MDO)
3118
                        printk("1");
3119
                else
3120
                        printk("0");
3121
                }
3122
 
3123
        printk("\nMDI :");
3124
        for (i = 0; i < size; ++i)
3125
                {
3126
                if (bits[i] & MII_MDI)
3127
                        printk("1");
3128
                else
3129
                        printk("0");
3130
                }
3131
 
3132
        printk("\n");
3133
#endif
3134
}
3135
#endif
3136
 
3137
#if 0
3138
static word smc_interpret_phy_register(const struct device *dev,
3139
        byte phyreg, word status)
3140
{
3141
#if (SMC_DEBUG > 3)
3142
    switch(phyreg)
3143
    {
3144
        case PHY_STAT_REG:
3145
            if(status & PHY_STAT_CAP_T4)
3146
                printk("<1>%s:100 Base T4 capable\n", dev->name);
3147
            else
3148
                printk("<1>%s:100 Base T4 incapable\n", dev->name);
3149
 
3150
            if(status & PHY_STAT_CAP_TXF)
3151
                printk("<1>%s:100 Base X, Full Duplex capable\n", dev->name);
3152
            else
3153
                printk("<1>%s:100 Base X, Full Duplex incapable\n", dev->name);
3154
 
3155
            if(status & PHY_STAT_CAP_TXH)
3156
                printk("<1>%s:100 Base X, Half Duplex capable\n", dev->name);
3157
            else
3158
                printk("<1>%s:100 Base X, Half Duplex incapable\n", dev->name);
3159
 
3160
            if(status & PHY_STAT_CAP_TF)
3161
                printk("<1>%s:10 Base X, Full Duplex capable\n", dev->name);
3162
            else
3163
                printk("<1>%s:10 Base X, Full Duplex incapable\n", dev->name);
3164
 
3165
            if(status & PHY_STAT_RESERVED)
3166
                printk("<1>%s:Reserved bits set 0x%x(bad thing :-(\n",
3167
                        dev->name, status & PHY_STAT_RESERVED);
3168
            else
3169
                printk("<1>%s:Reserved bits not set(good thing :-)\n",
3170
                        dev->name);
3171
 
3172
            if(status & PHY_STAT_CAP_SUPR)
3173
                printk("<1>%s:MI Preamble suppression capable\n", dev->name);
3174
            else
3175
                printk("<1>%s:MI Preamble suppression incapable\n", dev->name);
3176
 
3177
            if(status & PHY_STAT_ANEG_ACK)
3178
                printk("<1>%s:Auto-Negotiation Acknowledgment completed\n",
3179
                        dev->name);
3180
            else
3181
                printk("<1>%s:Auto-Negotiation Acknowledgment incomplete\n",
3182
                        dev->name);
3183
 
3184
            if(status & PHY_STAT_REM_FLT)
3185
                printk("<1>%s:Remote Fault Detected :-(\n", dev->name);
3186
            else
3187
                printk("<1>%s:Remote Fault NOT Detected :-)\n", dev->name);
3188
 
3189
            if(status & PHY_STAT_CAP_ANEG)
3190
                printk("<1>%s:Auto-Negotiate Capable\n", dev->name);
3191
            else
3192
                printk("<1>%s:Auto-Negotiate InCapable\n", dev->name);
3193
 
3194
            if(status & PHY_STAT_LINK)
3195
                printk("<1>%s:Valid Link Detected\n", dev->name);
3196
            else
3197
                printk("<1>%s:Invalid Link Detected\n", dev->name);
3198
 
3199
            if(status & PHY_STAT_JAB)
3200
                printk("<1>%s:Jabber Detected\n", dev->name);
3201
            else
3202
                printk("<1>%s:Jabber Not Detected\n", dev->name);
3203
 
3204
            if(status & PHY_STAT_EXREG)
3205
                printk("<1>%s:Extended Registers Implemented\n", dev->name);
3206
            else
3207
                printk("<1>%s:Extended Registers Not Implemented\n", dev->name);
3208
 
3209
            break;
3210
 
3211
        case PHY_INT_REG:
3212
            if(status & PHY_INT_INT)
3213
                printk("<1>%s:Bits have changed since last read\n", dev->name);
3214
            else
3215
                printk("<1>%s:Bits have not changed since last read\n",
3216
                        dev->name);
3217
 
3218
            if(status & PHY_INT_LNKFAIL)
3219
                printk("<1>%s:Link Fail Detected\n", dev->name);
3220
            else
3221
                printk("<1>%s:Link Normal Detected\n", dev->name);
3222
 
3223
            if(status & PHY_INT_LOSSSYNC)
3224
                printk("<1>%s:Descrambler lost sync\n", dev->name);
3225
            else
3226
                printk("<1>%s:No loss of sync\n", dev->name);
3227
 
3228
            if(status & PHY_INT_CWRD)
3229
                printk("<1>%s:Invalid 4B5B Code Word received\n", dev->name);
3230
            else
3231
                printk("<1>%s:No Invalid 4B5B Code Word\n", dev->name);
3232
 
3233
            if(status & PHY_INT_SSD)
3234
                printk("<1>%s:No Start of stream detected on rx\n", dev->name);
3235
            else
3236
                printk("<1>%s:Start of stream detected on rx\n", dev->name);
3237
 
3238
            if(status & PHY_INT_ESD)
3239
                printk("<1>%s:No End of stream detected on rx\n", dev->name);
3240
            else
3241
                printk("<1>%s:End of stream detected on rx\n", dev->name);
3242
 
3243
            if(status & PHY_INT_RPOL)
3244
                printk("<1>%s:Reverse Polarity Detected\n", dev->name);
3245
            else
3246
                printk("<1>%s:Normal Polarity Detected\n", dev->name);
3247
 
3248
            if(status & PHY_INT_JAB)
3249
                printk("<1>%s:Jabber Detected\n", dev->name);
3250
            else
3251
                printk("<1>%s:Jabber Not Detected\n", dev->name);
3252
 
3253
            if(status & PHY_INT_SPDDET)
3254
                printk("<1>%s:100 MBps Operation\n", dev->name);
3255
            else
3256
                printk("<1>%s:10 MBps Operation\n", dev->name);
3257
 
3258
            if(status & PHY_INT_DPLXDET)
3259
                printk("<1>%s:Device in Full Duplex Mode\n", dev->name);
3260
            else
3261
                printk("<1>%s:Device in Half Duplex Mode\n", dev->name);
3262
 
3263
            break;
3264
 
3265
        default:
3266
            printk(KERN_DEBUG
3267
                    "%s:Don't Know How to interpret the specified register\n",
3268
                    dev->name);
3269
            break;
3270
    }
3271
#endif
3272
    return(status);
3273
}
3274
#endif
3275
 
3276
/*------------------------------------------------------------
3277
 . Reads a register from the MII Management serial interface
3278
 .-------------------------------------------------------------*/
3279
static word smc_read_phy_register(unsigned long ioaddr, byte phyaddr,
3280
        byte phyreg)
3281
{
3282
        int oldBank;
3283
        int i;
3284
        byte mask;
3285
        word mii_reg;
3286
        byte bits[64];
3287
        int clk_idx = 0;
3288
        int input_idx;
3289
        word phydata;
3290
 
3291
        // 32 consecutive ones on MDO to establish sync
3292
    for (i = 0; i < 32; ++i)
3293
        bits[clk_idx++] = MII_MDOE | MII_MDO;
3294
 
3295
        // Start code <01>
3296
        bits[clk_idx++] = MII_MDOE;
3297
        bits[clk_idx++] = MII_MDOE | MII_MDO;
3298
 
3299
        // Read command <10>
3300
        bits[clk_idx++] = MII_MDOE | MII_MDO;
3301
        bits[clk_idx++] = MII_MDOE;
3302
 
3303
        // Output the PHY address, msb first
3304
        mask = (byte)0x10;
3305
        for (i = 0; i < 5; ++i)
3306
    {
3307
        if (phyaddr & mask)
3308
            bits[clk_idx++] = MII_MDOE | MII_MDO;
3309
        else
3310
            bits[clk_idx++] = MII_MDOE;
3311
        // Shift to next lowest bit
3312
        mask >>= 1;
3313
    }
3314
 
3315
        // Output the phy register number, msb first
3316
        mask = (byte)0x10;
3317
        for (i = 0; i < 5; ++i)
3318
    {
3319
        if (phyreg & mask)
3320
            bits[clk_idx++] = MII_MDOE | MII_MDO;
3321
        else
3322
            bits[clk_idx++] = MII_MDOE;
3323
        // Shift to next lowest bit
3324
        mask >>= 1;
3325
    }
3326
 
3327
        // Tristate and turnaround (2 bit times)
3328
        bits[clk_idx++] = 0;
3329
        //bits[clk_idx++] = 0;
3330
 
3331
        // Input starts at this bit time
3332
        input_idx = clk_idx;
3333
 
3334
        // Will input 16 bits
3335
        for (i = 0; i < 16; ++i)
3336
                bits[clk_idx++] = 0;
3337
 
3338
        // Final clock bit
3339
        bits[clk_idx++] = 0;
3340
 
3341
        // Save the current bank
3342
        oldBank = inw( ioaddr+BANK_SELECT );
3343
 
3344
        // Select bank 3
3345
        SMC_SELECT_BANK( 3 );
3346
 
3347
        // Get the current MII register value
3348
        mii_reg = inw( ioaddr+MII_REG );
3349
 
3350
        // Turn off all MII Interface bits
3351
        mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
3352
 
3353
        // Clock all 64 cycles
3354
        for (i = 0; i < sizeof bits; ++i)
3355
                {
3356
                // Clock Low - output data
3357
                outw( mii_reg | bits[i], ioaddr+MII_REG );
3358
                udelay(50);
3359
 
3360
 
3361
                // Clock Hi - input data
3362
                outw( mii_reg | bits[i] | MII_MCLK, ioaddr+MII_REG );
3363
                udelay(50);
3364
                bits[i] |= inw( ioaddr+MII_REG ) & MII_MDI;
3365
                }
3366
 
3367
        // Return to idle state
3368
        // Set clock to low, data to low, and output tristated
3369
        outw( mii_reg, ioaddr+MII_REG );
3370
        udelay(50);
3371
 
3372
        // Restore original bank select
3373
        SMC_SELECT_BANK( oldBank );
3374
 
3375
        // Recover input data
3376
        phydata = 0;
3377
        for (i = 0; i < 16; ++i)
3378
                {
3379
                phydata <<= 1;
3380
 
3381
                if (bits[input_idx++] & MII_MDI)
3382
                        phydata |= 0x0001;
3383
                }
3384
 
3385
//    printk("Slow the system down by a bit.\n");
3386
#if defined(CONFIG_SMC91C111_EXTRA_DELAY)
3387
    mdelay(SMC91C111_EXTRA_DELAY);
3388
#endif
3389
#if (SMC_DEBUG > 2 )
3390
        printk("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
3391
                phyaddr, phyreg, phydata);
3392
        smc_dump_mii_stream(bits, sizeof bits);
3393
#endif
3394
 
3395
        return(phydata);
3396
}
3397
 
3398
 
3399
/*------------------------------------------------------------
3400
 . Writes a register to the MII Management serial interface
3401
 .-------------------------------------------------------------*/
3402
static void smc_write_phy_register(unsigned long ioaddr,
3403
        byte phyaddr, byte phyreg, word phydata)
3404
{
3405
        int oldBank;
3406
        int i;
3407
        word mask;
3408
        word mii_reg;
3409
        byte bits[65];
3410
        int clk_idx = 0;
3411
 
3412
        // 32 consecutive ones on MDO to establish sync
3413
        for (i = 0; i < 32; ++i)
3414
                bits[clk_idx++] = MII_MDOE | MII_MDO;
3415
 
3416
        // Start code <01>
3417
        bits[clk_idx++] = MII_MDOE;
3418
        bits[clk_idx++] = MII_MDOE | MII_MDO;
3419
 
3420
        // Write command <01>
3421
        bits[clk_idx++] = MII_MDOE;
3422
        bits[clk_idx++] = MII_MDOE | MII_MDO;
3423
 
3424
        // Output the PHY address, msb first
3425
        mask = (byte)0x10;
3426
        for (i = 0; i < 5; ++i)
3427
                {
3428
                if (phyaddr & mask)
3429
                        bits[clk_idx++] = MII_MDOE | MII_MDO;
3430
                else
3431
                        bits[clk_idx++] = MII_MDOE;
3432
 
3433
                // Shift to next lowest bit
3434
                mask >>= 1;
3435
                }
3436
 
3437
        // Output the phy register number, msb first
3438
        mask = (byte)0x10;
3439
        for (i = 0; i < 5; ++i)
3440
                {
3441
                if (phyreg & mask)
3442
                        bits[clk_idx++] = MII_MDOE | MII_MDO;
3443
                else
3444
                        bits[clk_idx++] = MII_MDOE;
3445
 
3446
                // Shift to next lowest bit
3447
                mask >>= 1;
3448
                }
3449
 
3450
        // Tristate and turnaround (2 bit times)
3451
        bits[clk_idx++] = 0;
3452
        bits[clk_idx++] = 0;
3453
 
3454
        // Write out 16 bits of data, msb first
3455
        mask = 0x8000;
3456
        for (i = 0; i < 16; ++i)
3457
                {
3458
                if (phydata & mask)
3459
                        bits[clk_idx++] = MII_MDOE | MII_MDO;
3460
                else
3461
                        bits[clk_idx++] = MII_MDOE;
3462
 
3463
                // Shift to next lowest bit
3464
                mask >>= 1;
3465
                }
3466
 
3467
        // Final clock bit (tristate)
3468
        bits[clk_idx++] = 0;
3469
 
3470
        // Save the current bank
3471
        oldBank = inw( ioaddr+BANK_SELECT );
3472
 
3473
        // Select bank 3
3474
        SMC_SELECT_BANK( 3 );
3475
 
3476
        // Get the current MII register value
3477
        mii_reg = inw( ioaddr+MII_REG );
3478
 
3479
        // Turn off all MII Interface bits
3480
        mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
3481
 
3482
        // Clock all cycles
3483
        for (i = 0; i < sizeof bits; ++i)
3484
                {
3485
                // Clock Low - output data
3486
                outw( mii_reg | bits[i], ioaddr+MII_REG );
3487
                udelay(50);
3488
 
3489
 
3490
                // Clock Hi - input data
3491
                outw( mii_reg | bits[i] | MII_MCLK, ioaddr+MII_REG );
3492
                udelay(50);
3493
                bits[i] |= inw( ioaddr+MII_REG ) & MII_MDI;
3494
                }
3495
 
3496
        // Return to idle state
3497
        // Set clock to low, data to low, and output tristated
3498
        outw( mii_reg, ioaddr+MII_REG );
3499
        udelay(50);
3500
 
3501
        // Restore original bank select
3502
        SMC_SELECT_BANK( oldBank );
3503
 
3504
//    printk("Slow the system down by a bit.\n");
3505
#if defined(CONFIG_SMC91C111_EXTRA_DELAY)
3506
    mdelay(20);
3507
#endif
3508
#if (SMC_DEBUG > 2 )
3509
        printk("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
3510
                phyaddr, phyreg, phydata);
3511
        smc_dump_mii_stream(bits, sizeof bits);
3512
#endif
3513
}
3514
 
3515
 
3516
/*------------------------------------------------------------
3517
 . Finds and reports the PHY address
3518
 .-------------------------------------------------------------*/
3519
static int smc_detect_phy(struct device* dev)
3520
{
3521
        struct smc_local *lp = (struct smc_local *)dev->priv;
3522
        unsigned long ioaddr = dev->base_addr;
3523
        word phy_id1;
3524
        word phy_id2;
3525
        int phyaddr;
3526
        int found = 0;
3527
 
3528
        PRINTK3("%s:smc_detect_phy()\n", dev->name);
3529
 
3530
        // Scan all 32 PHY addresses if necessary
3531
        for (phyaddr = 0; phyaddr < 32; ++phyaddr)
3532
                {
3533
                // Read the PHY identifiers
3534
                phy_id1  = smc_read_phy_register(ioaddr, phyaddr, PHY_ID1_REG);
3535
                phy_id2  = smc_read_phy_register(ioaddr, phyaddr, PHY_ID2_REG);
3536
 
3537
                PRINTK3("%s: phy_id1=%x, phy_id2=%x\n",
3538
                        dev->name, phy_id1, phy_id2);
3539
 
3540
                // Make sure it is a valid identifier   
3541
                if ((phy_id2 > 0x0000) && (phy_id2 < 0xffff) &&
3542
                    (phy_id1 > 0x0000) && (phy_id1 < 0xffff))
3543
                        {
3544
                        if ((phy_id1 != 0x8000) && (phy_id2 != 0x8000))
3545
                                {
3546
                                // Save the PHY's address
3547
                                lp->phyaddr = phyaddr;
3548
                                found = 1;
3549
                                break;
3550
                                }
3551
                        }
3552
                }
3553
 
3554
        if (!found)
3555
                {
3556
                PRINTK("%s: No PHY found\n", dev->name);
3557
                return(0);
3558
                }
3559
 
3560
        // Set the PHY type
3561
        if ( (phy_id1 == 0x0016) && ((phy_id2 & 0xFFF0) == 0xF840 ) )
3562
                {
3563
                lp->phytype = PHY_LAN83C183;
3564
                PRINTK("%s: PHY=LAN83C183 (LAN91C111 Internal)\n", dev->name);
3565
                }
3566
 
3567
        if ( (phy_id1 == 0x0282) && ((phy_id2 & 0xFFF0) == 0x1C50) )
3568
                {
3569
                lp->phytype = PHY_LAN83C180;
3570
                PRINTK("%s: PHY=LAN83C180\n", dev->name);
3571
                }
3572
 
3573
 
3574
        return(1);
3575
}
3576
 
3577
/*------------------------------------------------------------
3578
 . Waits the specified number of milliseconds - kernel friendly
3579
 .-------------------------------------------------------------*/
3580
static void smc_wait_ms(unsigned int ms)
3581
{
3582
 
3583
        if (!in_interrupt())
3584
                {
3585
                current->state = TASK_UNINTERRUPTIBLE;
3586
                schedule_timeout(1 + ms * HZ / 1000);
3587
                }
3588
        else
3589
                {
3590
                current->state = TASK_INTERRUPTIBLE;
3591
                schedule_timeout(1 + ms * HZ / 1000);
3592
                current->state = TASK_RUNNING;
3593
                }
3594
}
3595
 
3596
/*------------------------------------------------------------
3597
 . Sets the PHY to a configuration as determined by the user
3598
 .-------------------------------------------------------------*/
3599
#ifdef CONFIG_SYSCTL
3600
static int smc_phy_fixed(struct device* dev)
3601
{
3602
        unsigned long ioaddr = dev->base_addr;
3603
        struct smc_local *lp = (struct smc_local *)dev->priv;
3604
        byte phyaddr = lp->phyaddr;
3605
        word my_fixed_caps;
3606
        word cfg1;
3607
 
3608
        PRINTK3("%s:smc_phy_fixed()\n", dev->name);
3609
 
3610
        // Enter Link Disable state
3611
        cfg1 = smc_read_phy_register(ioaddr, phyaddr, PHY_CFG1_REG);
3612
        cfg1 |= PHY_CFG1_LNKDIS;
3613
        smc_write_phy_register(ioaddr, phyaddr, PHY_CFG1_REG, cfg1);
3614
 
3615
        // Set our fixed capabilities
3616
        // Disable auto-negotiation
3617
        my_fixed_caps = 0;
3618
 
3619
#ifdef CONFIG_SYSCTL
3620
        if (lp->ctl_rfduplx)
3621
                my_fixed_caps |= PHY_CNTL_DPLX;
3622
 
3623
        if (lp->ctl_rspeed == 100)
3624
                my_fixed_caps |= PHY_CNTL_SPEED;
3625
#endif
3626
 
3627
        // Write our capabilities to the phy control register
3628
        smc_write_phy_register(ioaddr, phyaddr, PHY_CNTL_REG, my_fixed_caps);
3629
 
3630
        // Re-Configure the Receive/Phy Control register
3631
        outw( lp->rpc_cur_mode, ioaddr + RPC_REG );
3632
 
3633
        // Success
3634
        return(1);
3635
}
3636
#endif
3637
 
3638
/*------------------------------------------------------------
3639
 . Configures the specified PHY using Autonegotiation. Calls
3640
 . smc_phy_fixed() if the user has requested a certain config.
3641
 .-------------------------------------------------------------*/
3642
static void smc_phy_configure(struct device* dev)
3643
{
3644
        int ioaddr = dev->base_addr;
3645
        struct smc_local *lp = (struct smc_local *)dev->priv;
3646
        int timeout;
3647
        byte phyaddr;
3648
        word my_phy_caps; // My PHY capabilities
3649
        word my_ad_caps; // My Advertised capabilities
3650
        word status = 0;
3651
        int failed = 0;
3652
 
3653
        PRINTK3("%s:smc_program_phy()\n", dev->name);
3654
 
3655
        // Set the blocking flag
3656
        lp->autoneg_active = 1;
3657
 
3658
        // Find the address and type of our phy
3659
        if (!smc_detect_phy(dev))
3660
                {
3661
                goto smc_phy_configure_exit;
3662
                }
3663
 
3664
        // Get the detected phy address
3665
        phyaddr = lp->phyaddr;
3666
 
3667
        // Reset the PHY, setting all other bits to zero
3668
        smc_write_phy_register(ioaddr, phyaddr, PHY_CNTL_REG, PHY_CNTL_RST);
3669
 
3670
        // Wait for the reset to complete, or time out
3671
        timeout = 6; // Wait up to 3 seconds
3672
        while (timeout--)
3673
                {
3674
                if (!(smc_read_phy_register(ioaddr, phyaddr, PHY_CNTL_REG)
3675
                    & PHY_CNTL_RST))
3676
                        {
3677
                        // reset complete
3678
                        break;
3679
                        }
3680
 
3681
                smc_wait_ms(500); // wait 500 millisecs
3682
                if (signal_pending(current)) // Exit anyway if signaled
3683
                        {
3684
                        PRINTK2("%s:PHY reset interrupted by signal\n",
3685
                                dev->name);
3686
                        timeout = 0;
3687
                        break;
3688
                        }
3689
                }
3690
 
3691
        if (timeout < 1)
3692
                {
3693
                PRINTK2("%s:PHY reset timed out\n", dev->name);
3694
                goto smc_phy_configure_exit;
3695
                }
3696
 
3697
        // Read PHY Register 18, Status Output
3698
        lp->lastPhy18 = smc_read_phy_register(ioaddr, phyaddr, PHY_INT_REG);
3699
 
3700
        // Enable PHY Interrupts (for register 18)
3701
        // Interrupts listed here are disabled
3702
        smc_write_phy_register(ioaddr, phyaddr, PHY_MASK_REG,
3703
                PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD |
3704
                PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB |
3705
                PHY_INT_SPDDET | PHY_INT_DPLXDET);
3706
 
3707
        /* Configure the Receive/Phy Control register */
3708
        SMC_SELECT_BANK( 0 );
3709
        outw( lp->rpc_cur_mode, ioaddr + RPC_REG );
3710
 
3711
        // Copy our capabilities from PHY_STAT_REG to PHY_AD_REG
3712
        my_phy_caps = smc_read_phy_register(ioaddr, phyaddr, PHY_STAT_REG);
3713
        my_ad_caps  = PHY_AD_CSMA; // I am CSMA capable
3714
 
3715
        if (my_phy_caps & PHY_STAT_CAP_T4)
3716
                my_ad_caps |= PHY_AD_T4;
3717
 
3718
        if (my_phy_caps & PHY_STAT_CAP_TXF)
3719
                my_ad_caps |= PHY_AD_TX_FDX;
3720
 
3721
        if (my_phy_caps & PHY_STAT_CAP_TXH)
3722
                my_ad_caps |= PHY_AD_TX_HDX;
3723
 
3724
        if (my_phy_caps & PHY_STAT_CAP_TF)
3725
                my_ad_caps |= PHY_AD_10_FDX;
3726
 
3727
        if (my_phy_caps & PHY_STAT_CAP_TH)
3728
                my_ad_caps |= PHY_AD_10_HDX;
3729
 
3730
#if 0
3731
        // Disable capabilities not selected by our user
3732
        if (lp->ctl_rspeed != 100)
3733
                {
3734
                my_ad_caps &= ~(PHY_AD_T4|PHY_AD_TX_FDX|PHY_AD_TX_HDX);
3735
                }
3736
 
3737
        if (!lp->ctl_rfduplx)
3738
                {
3739
                my_ad_caps &= ~(PHY_AD_TX_FDX|PHY_AD_10_FDX);
3740
                }
3741
#endif
3742
 
3743
        // Update our Auto-Neg Advertisement Register
3744
        smc_write_phy_register(ioaddr, phyaddr, PHY_AD_REG, my_ad_caps);
3745
 
3746
        PRINTK2("%s:phy caps=%x\n", dev->name, my_phy_caps);
3747
        PRINTK2("%s:phy advertised caps=%x\n", dev->name, my_ad_caps);
3748
 
3749
#if 0
3750
        // If the user requested no auto neg, then go set his request
3751
        if (!(lp->ctl_autoneg))
3752
                {
3753
                smc_phy_fixed(dev);
3754
                goto smc_phy_configure_exit;
3755
                }
3756
#endif
3757
 
3758
        // Restart auto-negotiation process in order to advertise my caps
3759
        smc_write_phy_register( ioaddr, phyaddr, PHY_CNTL_REG,
3760
                PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST );
3761
 
3762
        // Wait for the auto-negotiation to complete.  This may take from
3763
        // 2 to 3 seconds.
3764
        // Wait for the reset to complete, or time out
3765
        timeout = 20; // Wait up to 10 seconds
3766
        while (timeout--)
3767
                {
3768
                status = smc_read_phy_register(ioaddr, phyaddr, PHY_STAT_REG);
3769
                if (status & PHY_STAT_ANEG_ACK)
3770
                        {
3771
                        // auto-negotiate complete
3772
                        break;
3773
                        }
3774
 
3775
                smc_wait_ms(500); // wait 500 millisecs
3776
                if (signal_pending(current)) // Exit anyway if signaled
3777
                        {
3778
                        printk(KERN_DEBUG
3779
                                "%s:PHY auto-negotiate interrupted by signal\n",
3780
                                dev->name);
3781
                        timeout = 0;
3782
                        break;
3783
                        }
3784
 
3785
                // Restart auto-negotiation if remote fault
3786
                if (status & PHY_STAT_REM_FLT)
3787
                        {
3788
                        PRINTK2("%s:PHY remote fault detected\n", dev->name);
3789
 
3790
                        // Restart auto-negotiation
3791
                        PRINTK2("%s:PHY restarting auto-negotiation\n",
3792
                                dev->name);
3793
                        smc_write_phy_register( ioaddr, phyaddr, PHY_CNTL_REG,
3794
                                PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST |
3795
                                PHY_CNTL_SPEED | PHY_CNTL_DPLX);
3796
                        }
3797
                }
3798
 
3799
        if (timeout < 1)
3800
                {
3801
                printk(KERN_DEBUG "%s:PHY auto-negotiate timed out\n",
3802
                        dev->name);
3803
                PRINTK2("%s:PHY auto-negotiate timed out\n", dev->name);
3804
                failed = 1;
3805
                }
3806
 
3807
        // Fail if we detected an auto-negotiate remote fault
3808
        if (status & PHY_STAT_REM_FLT)
3809
                {
3810
                PRINTK2("%s:PHY remote fault detected\n", dev->name);
3811
                failed = 1;
3812
                }
3813
 
3814
        // The smc_phy_interrupt() routine will be called to update lastPhy18
3815
 
3816
        // Set our sysctl parameters to match auto-negotiation results
3817
        if ( lp->lastPhy18 & PHY_INT_SPDDET )
3818
                {
3819
                PRINTK2("%s:PHY 100BaseT\n", dev->name);
3820
                lp->rpc_cur_mode |= RPC_SPEED;
3821
                }
3822
        else
3823
                {
3824
                PRINTK2("%s:PHY 10BaseT\n", dev->name);
3825
                lp->rpc_cur_mode &= ~RPC_SPEED;
3826
                }
3827
 
3828
        if ( lp->lastPhy18 & PHY_INT_DPLXDET )
3829
                {
3830
                PRINTK2("%s:PHY Full Duplex\n", dev->name);
3831
                lp->rpc_cur_mode |= RPC_DPLX;
3832
                }
3833
        else
3834
                {
3835
                PRINTK2("%s:PHY Half Duplex\n", dev->name);
3836
                lp->rpc_cur_mode &= ~RPC_DPLX;
3837
                }
3838
 
3839
        // Re-Configure the Receive/Phy Control register
3840
        outw( lp->rpc_cur_mode, ioaddr + RPC_REG );
3841
 
3842
  smc_phy_configure_exit:
3843
 
3844
        // Exit auto-negotiation
3845
        lp->autoneg_active = 0;
3846
}
3847
 
3848
 
3849
void smc_register_dump(const struct device *dev)
3850
{
3851
#if SMC_DEBUG > 3
3852
    //Read all of the configuration registers.
3853
    unsigned long ioaddr = dev->base_addr;
3854
    word current_bank = inw(ioaddr + BANK_SELECT);
3855
    int i;
3856
 
3857
    SMC_SELECT_BANK(0);
3858
    PRINTK("%s:Register Dump Bank 0\n", dev->name);
3859
    for(i = 0; i <= 0x0a; i = i + 2)
3860
        PRINTK("\t%s:Bank 0 Register 0x%02x: 0x%04x\n", dev->name,
3861
                i, inw(ioaddr + i));
3862
 
3863
    SMC_SELECT_BANK(1);
3864
    PRINTK("%s:Register Dump Bank 1\n", dev->name);
3865
    for(i = 0; i <= 0x0c; i = i + 2)
3866
        PRINTK("\t%s:Bank 1 Register 0x%02x: 0x%04x\n", dev->name,
3867
                i, inw(ioaddr + i));
3868
 
3869
    SMC_SELECT_BANK(2);
3870
    PRINTK("%s:Register Dump Bank 2\n", dev->name);
3871
    for(i = 0; i <= 0x0c; i = i + 2)
3872
        PRINTK("\t%s:Bank 2 Register 0x%02x: 0x%04x\n", dev->name,
3873
                i, inw(ioaddr + i));
3874
 
3875
    SMC_SELECT_BANK(3);
3876
    PRINTK("%s:Register Dump Bank 3\n", dev->name);
3877
    for(i = 0; i <= 0x0c; i = i + 2)
3878
        PRINTK("\t%s:Bank 3 Register 0x%02x: 0x%04x\n", dev->name,
3879
                i, inw(ioaddr + i));
3880
 
3881
    PRINTK("%s:Current Bank is 0x%04x\n", dev->name, current_bank);
3882
    SMC_SELECT_BANK((current_bank&0x0007));
3883
#endif
3884
}
3885
 
3886
 
3887
 
3888
/*************************************************************************
3889
 . smc_phy_interrupt
3890
 .
3891
 . Purpose:  Handle interrupts relating to PHY register 18. This is
3892
 .  called from the "hard" interrupt handler.
3893
 .
3894
 ************************************************************************/
3895
static void smc_phy_interrupt(struct device* dev)
3896
{
3897
        unsigned long ioaddr            = dev->base_addr;
3898
        struct smc_local *lp    = (struct smc_local *)dev->priv;
3899
        byte phyaddr = lp->phyaddr;
3900
        word phy18;
3901
 
3902
        PRINTK2("%s: smc_phy_interrupt\n", dev->name);
3903
 
3904
  while (1)
3905
        {
3906
        // Read PHY Register 18, Status Output
3907
        phy18 = smc_read_phy_register(ioaddr, phyaddr, PHY_INT_REG);
3908
 
3909
        // Exit if not more changes
3910
        if (phy18 == lp->lastPhy18)
3911
                break;
3912
 
3913
#if (SMC_DEBUG > 1 )
3914
 
3915
        PRINTK2("%s:     phy18=0x%x\n", dev->name, phy18);
3916
        PRINTK2("%s: lastPhy18=0x%x\n", dev->name, lp->lastPhy18);
3917
 
3918
        // Handle events
3919
        if ((phy18 & PHY_INT_LNKFAIL) != (lp->lastPhy18 & PHY_INT_LNKFAIL))
3920
                {
3921
                PRINTK2("%s: PHY Link Fail=%x\n", dev->name,
3922
                        phy18 & PHY_INT_LNKFAIL);
3923
                }
3924
 
3925
        if ((phy18 & PHY_INT_LOSSSYNC) != (lp->lastPhy18 & PHY_INT_LOSSSYNC))
3926
                {
3927
                PRINTK2("%s: PHY LOSS SYNC=%x\n", dev->name,
3928
                        phy18 & PHY_INT_LOSSSYNC);
3929
                }
3930
 
3931
        if ((phy18 & PHY_INT_CWRD) != (lp->lastPhy18 & PHY_INT_CWRD))
3932
                {
3933
                PRINTK2("%s: PHY INVALID 4B5B code=%x\n", dev->name,
3934
                        phy18 & PHY_INT_CWRD);
3935
                }
3936
 
3937
        if ((phy18 & PHY_INT_SSD) != (lp->lastPhy18 & PHY_INT_SSD))
3938
                {
3939
                PRINTK2("%s: PHY No Start Of Stream=%x\n", dev->name,
3940
                        phy18 & PHY_INT_SSD);
3941
                }
3942
 
3943
        if ((phy18 & PHY_INT_ESD) != (lp->lastPhy18 & PHY_INT_ESD))
3944
                {
3945
                PRINTK2("%s: PHY No End Of Stream=%x\n", dev->name,
3946
                        phy18 & PHY_INT_ESD);
3947
                }
3948
 
3949
        if ((phy18 & PHY_INT_RPOL) != (lp->lastPhy18 & PHY_INT_RPOL))
3950
                {
3951
                PRINTK2("%s: PHY Reverse Polarity Detected=%x\n", dev->name,
3952
                        phy18 & PHY_INT_RPOL);
3953
                }
3954
 
3955
        if ((phy18 & PHY_INT_JAB) != (lp->lastPhy18 & PHY_INT_JAB))
3956
                {
3957
                PRINTK2("%s: PHY Jabber Detected=%x\n", dev->name,
3958
                        phy18 & PHY_INT_JAB);
3959
                }
3960
 
3961
        if ((phy18 & PHY_INT_SPDDET) != (lp->lastPhy18 & PHY_INT_SPDDET))
3962
                {
3963
                PRINTK2("%s: PHY Speed Detect=%x\n", dev->name,
3964
                        phy18 & PHY_INT_SPDDET);
3965
                }
3966
 
3967
        if ((phy18 & PHY_INT_DPLXDET) != (lp->lastPhy18 & PHY_INT_DPLXDET))
3968
                {
3969
                PRINTK2("%s: PHY Duplex Detect=%x\n", dev->name,
3970
                        phy18 & PHY_INT_DPLXDET);
3971
                }
3972
#endif
3973
 
3974
        // Update the last phy 18 variable
3975
        lp->lastPhy18 = phy18;
3976
 
3977
        } // end while
3978
}
3979
 
3980
 

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