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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [drivers/] [sbus/] [char/] [sunserial.h] - Blame information for rev 1765

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Line No. Rev Author Line
1 1626 jcastillo
/* serial.h: Definitions for the Sparc Zilog serial driver.
2
 *
3
 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
4
 */
5
#ifndef _SPARC_SERIAL_H
6
#define _SPARC_SERIAL_H
7
 
8
/* Just one channel */
9
struct sun_zschannel {
10
        volatile unsigned char control;
11
        volatile unsigned char pad1;
12
        volatile unsigned char data;
13
        volatile unsigned char pad2;
14
};
15
 
16
/* The address space layout for each zs chip.  Yes they are
17
 * backwards.
18
 */
19
struct sun_zslayout {
20
        struct sun_zschannel channelB;
21
        struct sun_zschannel channelA;
22
};
23
 
24
/* We need to keep track of the keyboard state, *ahead* of what
25
 * the keyboard driver sees, which will be later on after the
26
 * interrupt via tqueue wait queues and/or base-handler processing.
27
 */
28
struct l1a_kbd_state {
29
        unsigned char kbd_id;
30
        unsigned char l1_down;
31
};
32
 
33
#define NUM_ZSREGS    16
34
 
35
struct serial_struct {
36
        int     type;
37
        int     line;
38
        int     port;
39
        int     irq;
40
        int     flags;
41
        int     xmit_fifo_size;
42
        int     custom_divisor;
43
        int     baud_base;
44
        unsigned short  close_delay;
45
        char    reserved_char[2];
46
        int     hub6;
47
        unsigned short  closing_wait; /* time to wait before closing */
48
        unsigned short  closing_wait2; /* no longer used... */
49
        int     reserved[4];
50
};
51
 
52
/*
53
 * For the close wait times, 0 means wait forever for serial port to
54
 * flush its output.  65535 means don't wait at all.
55
 */
56
#define ZILOG_CLOSING_WAIT_INF  0
57
#define ZILOG_CLOSING_WAIT_NONE 65535
58
 
59
/*
60
 * Definitions for ZILOG_struct (and serial_struct) flags field
61
 */
62
#define ZILOG_HUP_NOTIFY 0x0001 /* Notify getty on hangups and closes 
63
                                   on the callout port */
64
#define ZILOG_FOURPORT  0x0002  /* Set OU1, OUT2 per AST Fourport settings */
65
#define ZILOG_SAK       0x0004  /* Secure Attention Key (Orange book) */
66
#define ZILOG_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */
67
 
68
#define ZILOG_SPD_MASK  0x0030
69
#define ZILOG_SPD_HI    0x0010  /* Use 56000 instead of 38400 bps */
70
 
71
#define ZILOG_SPD_VHI   0x0020  /* Use 115200 instead of 38400 bps */
72
#define ZILOG_SPD_CUST  0x0030  /* Use user-specified divisor */
73
 
74
#define ZILOG_SKIP_TEST 0x0040 /* Skip UART test during autoconfiguration */
75
#define ZILOG_AUTO_IRQ  0x0080 /* Do automatic IRQ during autoconfiguration */
76
#define ZILOG_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */
77
#define ZILOG_PGRP_LOCKOUT    0x0200 /* Lock out cua opens based on pgrp */
78
#define ZILOG_CALLOUT_NOHUP   0x0400 /* Don't do hangups for cua device */
79
 
80
#define ZILOG_FLAGS     0x0FFF  /* Possible legal ZILOG flags */
81
#define ZILOG_USR_MASK 0x0430   /* Legal flags that non-privileged
82
                                 * users can set or reset */
83
 
84
/* Internal flags used only by kernel/chr_drv/serial.c */
85
#define ZILOG_INITIALIZED       0x80000000 /* Serial port was initialized */
86
#define ZILOG_CALLOUT_ACTIVE    0x40000000 /* Call out device is active */
87
#define ZILOG_NORMAL_ACTIVE     0x20000000 /* Normal device is active */
88
#define ZILOG_BOOT_AUTOCONF     0x10000000 /* Autoconfigure port on bootup */
89
#define ZILOG_CLOSING           0x08000000 /* Serial port is closing */
90
#define ZILOG_CTS_FLOW          0x04000000 /* Do CTS flow control */
91
#define ZILOG_CHECK_CD          0x02000000 /* i.e., CLOCAL */
92
 
93
/* Software state per channel */
94
 
95
#ifdef __KERNEL__
96
/*
97
 * This is our internal structure for each serial port's state.
98
 *
99
 * Many fields are paralleled by the structure used by the serial_struct
100
 * structure.
101
 *
102
 * For definitions of the flags field, see tty.h
103
 */
104
 
105
struct sun_serial {
106
        struct sun_serial *zs_next;       /* For IRQ servicing chain */
107
        struct sun_zschannel *zs_channel; /* Channel registers */
108
        unsigned char read_reg_zero;
109
 
110
        char soft_carrier;  /* Use soft carrier on this channel */
111
        char cons_keyb;     /* Channel runs the keyboard */
112
        char cons_mouse;    /* Channel runs the mouse */
113
        char break_abort;   /* Is serial console in, so process brk/abrt */
114
        char kgdb_channel;  /* Kgdb is running on this channel */
115
        char is_cons;       /* Is this our console. */
116
 
117
        /* We need to know the current clock divisor
118
         * to read the bps rate the chip has currently
119
         * loaded.
120
         */
121
        unsigned char clk_divisor;  /* May be 1, 16, 32, or 64 */
122
        int zs_baud;
123
 
124
        /* Current write register values */
125
        unsigned char curregs[NUM_ZSREGS];
126
 
127
        /* Values we need to set next opportunity */
128
        unsigned char pendregs[NUM_ZSREGS];
129
 
130
        char change_needed;
131
 
132
        int                     magic;
133
        int                     baud_base;
134
        int                     port;
135
        int                     irq;
136
        int                     flags;          /* defined in tty.h */
137
        int                     type;           /* UART type */
138
        struct tty_struct       *tty;
139
        int                     read_status_mask;
140
        int                     ignore_status_mask;
141
        int                     timeout;
142
        int                     xmit_fifo_size;
143
        int                     custom_divisor;
144
        int                     x_char; /* xon/xoff character */
145
        int                     close_delay;
146
        unsigned short          closing_wait;
147
        unsigned short          closing_wait2;
148
        unsigned long           event;
149
        unsigned long           last_active;
150
        int                     line;
151
        int                     count;      /* # of fd on device */
152
        int                     blocked_open; /* # of blocked opens */
153
        long                    session; /* Session of opening process */
154
        long                    pgrp; /* pgrp of opening process */
155
        unsigned char           *xmit_buf;
156
        int                     xmit_head;
157
        int                     xmit_tail;
158
        int                     xmit_cnt;
159
        struct tq_struct        tqueue;
160
        struct tq_struct        tqueue_hangup;
161
        struct termios          normal_termios;
162
        struct termios          callout_termios;
163
        struct wait_queue       *open_wait;
164
        struct wait_queue       *close_wait;
165
};
166
 
167
 
168
#define SERIAL_MAGIC 0x5301
169
 
170
/*
171
 * The size of the serial xmit buffer is 1 page, or 4096 bytes
172
 */
173
#define SERIAL_XMIT_SIZE 4096
174
 
175
/*
176
 * Events are used to schedule things to happen at timer-interrupt
177
 * time, instead of at rs interrupt time.
178
 */
179
#define RS_EVENT_WRITE_WAKEUP   0
180
 
181
#endif /* __KERNEL__ */
182
 
183
/* Conversion routines to/from brg time constants from/to bits
184
 * per second.
185
 */
186
#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
187
#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
188
 
189
/* The Zilog register set */
190
 
191
#define FLAG    0x7e
192
 
193
/* Write Register 0 */
194
#define R0      0                /* Register selects */
195
#define R1      1
196
#define R2      2
197
#define R3      3
198
#define R4      4
199
#define R5      5
200
#define R6      6
201
#define R7      7
202
#define R8      8
203
#define R9      9
204
#define R10     10
205
#define R11     11
206
#define R12     12
207
#define R13     13
208
#define R14     14
209
#define R15     15
210
 
211
#define NULLCODE        0        /* Null Code */
212
#define POINT_HIGH      0x8     /* Select upper half of registers */
213
#define RES_EXT_INT     0x10    /* Reset Ext. Status Interrupts */
214
#define SEND_ABORT      0x18    /* HDLC Abort */
215
#define RES_RxINT_FC    0x20    /* Reset RxINT on First Character */
216
#define RES_Tx_P        0x28    /* Reset TxINT Pending */
217
#define ERR_RES         0x30    /* Error Reset */
218
#define RES_H_IUS       0x38    /* Reset highest IUS */
219
 
220
#define RES_Rx_CRC      0x40    /* Reset Rx CRC Checker */
221
#define RES_Tx_CRC      0x80    /* Reset Tx CRC Checker */
222
#define RES_EOM_L       0xC0    /* Reset EOM latch */
223
 
224
/* Write Register 1 */
225
 
226
#define EXT_INT_ENAB    0x1     /* Ext Int Enable */
227
#define TxINT_ENAB      0x2     /* Tx Int Enable */
228
#define PAR_SPEC        0x4     /* Parity is special condition */
229
 
230
#define RxINT_DISAB     0        /* Rx Int Disable */
231
#define RxINT_FCERR     0x8     /* Rx Int on First Character Only or Error */
232
#define INT_ALL_Rx      0x10    /* Int on all Rx Characters or error */
233
#define INT_ERR_Rx      0x18    /* Int on error only */
234
 
235
#define WT_RDY_RT       0x20    /* Wait/Ready on R/T */
236
#define WT_FN_RDYFN     0x40    /* Wait/FN/Ready FN */
237
#define WT_RDY_ENAB     0x80    /* Wait/Ready Enable */
238
 
239
/* Write Register #2 (Interrupt Vector) */
240
 
241
/* Write Register 3 */
242
 
243
#define RxENABLE        0x1     /* Rx Enable */
244
#define SYNC_L_INH      0x2     /* Sync Character Load Inhibit */
245
#define ADD_SM          0x4     /* Address Search Mode (SDLC) */
246
#define RxCRC_ENAB      0x8     /* Rx CRC Enable */
247
#define ENT_HM          0x10    /* Enter Hunt Mode */
248
#define AUTO_ENAB       0x20    /* Auto Enables */
249
#define Rx5             0x0     /* Rx 5 Bits/Character */
250
#define Rx7             0x40    /* Rx 7 Bits/Character */
251
#define Rx6             0x80    /* Rx 6 Bits/Character */
252
#define Rx8             0xc0    /* Rx 8 Bits/Character */
253
 
254
/* Write Register 4 */
255
 
256
#define PAR_ENA         0x1     /* Parity Enable */
257
#define PAR_EVEN        0x2     /* Parity Even/Odd* */
258
 
259
#define SYNC_ENAB       0        /* Sync Modes Enable */
260
#define SB1             0x4     /* 1 stop bit/char */
261
#define SB15            0x8     /* 1.5 stop bits/char */
262
#define SB2             0xc     /* 2 stop bits/char */
263
 
264
#define MONSYNC         0        /* 8 Bit Sync character */
265
#define BISYNC          0x10    /* 16 bit sync character */
266
#define SDLC            0x20    /* SDLC Mode (01111110 Sync Flag) */
267
#define EXTSYNC         0x30    /* External Sync Mode */
268
 
269
#define X1CLK           0x0     /* x1 clock mode */
270
#define X16CLK          0x40    /* x16 clock mode */
271
#define X32CLK          0x80    /* x32 clock mode */
272
#define X64CLK          0xC0    /* x64 clock mode */
273
 
274
/* Write Register 5 */
275
 
276
#define TxCRC_ENAB      0x1     /* Tx CRC Enable */
277
#define RTS             0x2     /* RTS */
278
#define SDLC_CRC        0x4     /* SDLC/CRC-16 */
279
#define TxENAB          0x8     /* Tx Enable */
280
#define SND_BRK         0x10    /* Send Break */
281
#define Tx5             0x0     /* Tx 5 bits (or less)/character */
282
#define Tx7             0x20    /* Tx 7 bits/character */
283
#define Tx6             0x40    /* Tx 6 bits/character */
284
#define Tx8             0x60    /* Tx 8 bits/character */
285
#define DTR             0x80    /* DTR */
286
 
287
/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
288
 
289
/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
290
 
291
/* Write Register 8 (transmit buffer) */
292
 
293
/* Write Register 9 (Master interrupt control) */
294
#define VIS     1       /* Vector Includes Status */
295
#define NV      2       /* No Vector */
296
#define DLC     4       /* Disable Lower Chain */
297
#define MIE     8       /* Master Interrupt Enable */
298
#define STATHI  0x10    /* Status high */
299
#define NORESET 0        /* No reset on write to R9 */
300
#define CHRB    0x40    /* Reset channel B */
301
#define CHRA    0x80    /* Reset channel A */
302
#define FHWRES  0xc0    /* Force hardware reset */
303
 
304
/* Write Register 10 (misc control bits) */
305
#define BIT6    1       /* 6 bit/8bit sync */
306
#define LOOPMODE 2      /* SDLC Loop mode */
307
#define ABUNDER 4       /* Abort/flag on SDLC xmit underrun */
308
#define MARKIDLE 8      /* Mark/flag on idle */
309
#define GAOP    0x10    /* Go active on poll */
310
#define NRZ     0        /* NRZ mode */
311
#define NRZI    0x20    /* NRZI mode */
312
#define FM1     0x40    /* FM1 (transition = 1) */
313
#define FM0     0x60    /* FM0 (transition = 0) */
314
#define CRCPS   0x80    /* CRC Preset I/O */
315
 
316
/* Write Register 11 (Clock Mode control) */
317
#define TRxCXT  0        /* TRxC = Xtal output */
318
#define TRxCTC  1       /* TRxC = Transmit clock */
319
#define TRxCBR  2       /* TRxC = BR Generator Output */
320
#define TRxCDP  3       /* TRxC = DPLL output */
321
#define TRxCOI  4       /* TRxC O/I */
322
#define TCRTxCP 0        /* Transmit clock = RTxC pin */
323
#define TCTRxCP 8       /* Transmit clock = TRxC pin */
324
#define TCBR    0x10    /* Transmit clock = BR Generator output */
325
#define TCDPLL  0x18    /* Transmit clock = DPLL output */
326
#define RCRTxCP 0        /* Receive clock = RTxC pin */
327
#define RCTRxCP 0x20    /* Receive clock = TRxC pin */
328
#define RCBR    0x40    /* Receive clock = BR Generator output */
329
#define RCDPLL  0x60    /* Receive clock = DPLL output */
330
#define RTxCX   0x80    /* RTxC Xtal/No Xtal */
331
 
332
/* Write Register 12 (lower byte of baud rate generator time constant) */
333
 
334
/* Write Register 13 (upper byte of baud rate generator time constant) */
335
 
336
/* Write Register 14 (Misc control bits) */
337
#define BRENABL 1       /* Baud rate generator enable */
338
#define BRSRC   2       /* Baud rate generator source */
339
#define DTRREQ  4       /* DTR/Request function */
340
#define AUTOECHO 8      /* Auto Echo */
341
#define LOOPBAK 0x10    /* Local loopback */
342
#define SEARCH  0x20    /* Enter search mode */
343
#define RMC     0x40    /* Reset missing clock */
344
#define DISDPLL 0x60    /* Disable DPLL */
345
#define SSBR    0x80    /* Set DPLL source = BR generator */
346
#define SSRTxC  0xa0    /* Set DPLL source = RTxC */
347
#define SFMM    0xc0    /* Set FM mode */
348
#define SNRZI   0xe0    /* Set NRZI mode */
349
 
350
/* Write Register 15 (external/status interrupt control) */
351
#define ZCIE    2       /* Zero count IE */
352
#define DCDIE   8       /* DCD IE */
353
#define SYNCIE  0x10    /* Sync/hunt IE */
354
#define CTSIE   0x20    /* CTS IE */
355
#define TxUIE   0x40    /* Tx Underrun/EOM IE */
356
#define BRKIE   0x80    /* Break/Abort IE */
357
 
358
 
359
/* Read Register 0 */
360
#define Rx_CH_AV        0x1     /* Rx Character Available */
361
#define ZCOUNT          0x2     /* Zero count */
362
#define Tx_BUF_EMP      0x4     /* Tx Buffer empty */
363
#define DCD             0x8     /* DCD */
364
#define SYNC_HUNT       0x10    /* Sync/hunt */
365
#define CTS             0x20    /* CTS */
366
#define TxEOM           0x40    /* Tx underrun */
367
#define BRK_ABRT        0x80    /* Break/Abort */
368
 
369
/* Read Register 1 */
370
#define ALL_SNT         0x1     /* All sent */
371
/* Residue Data for 8 Rx bits/char programmed */
372
#define RES3            0x8     /* 0/3 */
373
#define RES4            0x4     /* 0/4 */
374
#define RES5            0xc     /* 0/5 */
375
#define RES6            0x2     /* 0/6 */
376
#define RES7            0xa     /* 0/7 */
377
#define RES8            0x6     /* 0/8 */
378
#define RES18           0xe     /* 1/8 */
379
#define RES28           0x0     /* 2/8 */
380
/* Special Rx Condition Interrupts */
381
#define PAR_ERR         0x10    /* Parity error */
382
#define Rx_OVR          0x20    /* Rx Overrun Error */
383
#define CRC_ERR         0x40    /* CRC/Framing Error */
384
#define END_FR          0x80    /* End of Frame (SDLC) */
385
 
386
/* Read Register 2 (channel b only) - Interrupt vector */
387
 
388
/* Read Register 3 (interrupt pending register) ch a only */
389
#define CHBEXT  0x1             /* Channel B Ext/Stat IP */
390
#define CHBTxIP 0x2             /* Channel B Tx IP */
391
#define CHBRxIP 0x4             /* Channel B Rx IP */
392
#define CHAEXT  0x8             /* Channel A Ext/Stat IP */
393
#define CHATxIP 0x10            /* Channel A Tx IP */
394
#define CHARxIP 0x20            /* Channel A Rx IP */
395
 
396
/* Read Register 8 (receive data register) */
397
 
398
/* Read Register 10  (misc status bits) */
399
#define ONLOOP  2               /* On loop */
400
#define LOOPSEND 0x10           /* Loop sending */
401
#define CLK2MIS 0x40            /* Two clocks missing */
402
#define CLK1MIS 0x80            /* One clock missing */
403
 
404
/* Read Register 12 (lower byte of baud rate generator constant) */
405
 
406
/* Read Register 13 (upper byte of baud rate generator constant) */
407
 
408
/* Read Register 15 (value of WR 15) */
409
 
410
/* Misc macros */
411
#define ZS_CLEARERR(channel)    (channel->control = ERR_RES)
412
#define ZS_CLEARFIFO(channel)   do { volatile unsigned char garbage; \
413
                                     garbage = channel->data; \
414
                                     udelay(2); \
415
                                     garbage = channel->data; \
416
                                     udelay(2); \
417
                                     garbage = channel->data; \
418
                                     udelay(2); } while(0)
419
 
420
#endif /* !(_SPARC_SERIAL_H) */

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