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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [drivers/] [scsi/] [AM53C974.h] - Blame information for rev 1765

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Line No. Rev Author Line
1 1626 jcastillo
/* AM53/79C974 (PCscsi) driver release 0.5
2
 *
3
 * The architecture and much of the code of this device
4
 * driver was originally developed by Drew Eckhardt for
5
 * the NCR5380. The following copyrights apply:
6
 *  For the architecture and all parts similar to the NCR5380:
7
 *    Copyright 1993, Drew Eckhardt
8
 *      Visionary Computing
9
 *      (Unix and Linux consulting and custom programming)
10
 *      drew@colorado.edu
11
 *      +1 (303) 666-5836
12
 *
13
 *  The AM53C974_nobios_detect code was originally developed by
14
 *   Robin Cutshaw (robin@xfree86.org) and is used here in a
15
 *   modified form.
16
 *
17
 *  For the other parts:
18
 *    Copyright 1994, D. Frieauff
19
 *    EMail: fri@rsx42sun0.dofn.de
20
 *    Phone: x49-7545-8-2256 , x49-7541-42305
21
 */
22
 
23
/*
24
 * $Log: not supported by cvs2svn $
25
 * Revision 1.1.1.1  2001/09/10 07:44:28  simons
26
 * Initial import
27
 *
28
 * Revision 1.1.1.1  2001/07/02 17:58:29  simons
29
 * Initial revision
30
 *
31
 */
32
 
33
#ifndef AM53C974_H
34
#define AM53C974_H
35
 
36
#include <scsi/scsicam.h>
37
 
38
/***************************************************************************************
39
* Default setting of the controller's SCSI id. Edit and uncomment this only if your    *
40
* BIOS does not correctly initialize the controller's SCSI id.                         *
41
* If you don't get a warning during boot, it is correctly initialized.                 *
42
****************************************************************************************/
43
/* #define AM53C974_SCSI_ID 7 */
44
 
45
/***************************************************************************************
46
* Default settings for sync. negotiation enable, transfer rate and sync. offset.       *
47
* These settings can be replaced by LILO overrides (append) with the following syntax:          *
48
* AM53C974=host-scsi-id, target-scsi-id, max-rate, max-offset                          *
49
* Sync. negotiation is disabled by default and will be enabled for those targets which *
50
* are specified in the LILO override                                                   *
51
****************************************************************************************/
52
#define DEFAULT_SYNC_NEGOTIATION_ENABLED 0 /* 0 or 1 */
53
#define DEFAULT_RATE                     5 /* MHz, min: 3; max: 10 */
54
#define DEFAULT_SYNC_OFFSET              0 /* bytes, min: 0; max: 15; use 0 for async. mode */
55
 
56
 
57
/* --------------------- don't edit below here  --------------------- */
58
 
59
#define AM53C974_DRIVER_REVISION_MAJOR 0
60
#define AM53C974_DRIVER_REVISION_MINOR 5
61
#define SEPARATOR_LINE  \
62
"--------------------------------------------------------------------------\n"
63
 
64
/* debug control */
65
/* #define AM53C974_DEBUG */
66
/* #define AM53C974_DEBUG_MSG */
67
/* #define AM53C974_DEBUG_KEYWAIT */
68
/* #define AM53C974_DEBUG_INIT */
69
/* #define AM53C974_DEBUG_QUEUE */
70
/* #define AM53C974_DEBUG_INFO */
71
/* #define AM53C974_DEBUG_LINKED */
72
/* #define VERBOSE_AM53C974_DEBUG */
73
/* #define AM53C974_DEBUG_INTR */
74
/* #define AM53C974_DEB_RESEL */
75
#define AM53C974_DEBUG_ABORT
76
/* #define AM53C974_OPTION_DEBUG_PROBE_ONLY */
77
 
78
/* special options/constants */
79
#define DEF_CLK                 40   /* chip clock freq. in MHz */
80
#define MIN_PERIOD               4   /* for negotiation: min. number of clocks per cycle */
81
#define MAX_PERIOD              13   /* for negotiation: max. number of clocks per cycle */
82
#define MAX_OFFSET              15   /* for negotiation: max. offset (0=async) */
83
 
84
#define DEF_SCSI_TIMEOUT        245  /* STIMREG value, 40 Mhz */
85
#define DEF_STP                 8    /* STPREG value assuming 5.0 MB/sec, FASTCLK, FASTSCSI */
86
#define DEF_SOF_RAD             0    /* REQ/ACK deassertion delay */
87
#define DEF_SOF_RAA             0    /* REQ/ACK assertion delay */
88
#define DEF_ETM                 0    /* CNTLREG1, ext. timing mode */
89
#define DEF_PERE                1    /* CNTLREG1, parity error reporting */
90
#define DEF_CLKF                0    /* CLKFREG,  0=40 Mhz */
91
#define DEF_ENF                 1    /* CNTLREG2, enable features */
92
#define DEF_ADIDCHK             0    /* CNTLREG3, additional ID check */
93
#define DEF_FASTSCSI            1    /* CNTLREG3, fast SCSI */
94
#define DEF_FASTCLK             1    /* CNTLREG3, fast clocking, 5 MB/sec at 40MHz chip clk */
95
#define DEF_GLITCH              1    /* CNTLREG4, glitch eater, 0=12ns, 1=35ns, 2=25ns, 3=off */
96
#define DEF_PWD                 0    /* CNTLREG4, reduced power feature */
97
#define DEF_RAE                 0    /* CNTLREG4, RAE active negation on REQ, ACK only */
98
#define DEF_RADE                1    /* 1CNTLREG4, active negation on REQ, ACK and data */
99
 
100
/*** PCI block ***/
101
/* standard registers are defined in <linux/pci.h> */
102
#ifndef PCI_VENDOR_ID_AMD
103
#define PCI_VENDOR_ID_AMD       0x1022
104
#define PCI_DEVICE_ID_AMD_SCSI  0x2020
105
#endif
106
#define PCI_BASE_MASK           0xFFFFFFE0
107
#define PCI_COMMAND_PERREN      0x40
108
#define PCI_SCRATCH_REG_0       0x40    /* 16 bits */
109
#define PCI_SCRATCH_REG_1       0x42    /* 16 bits */
110
#define PCI_SCRATCH_REG_2       0x44    /* 16 bits */
111
#define PCI_SCRATCH_REG_3       0x46    /* 16 bits */
112
#define PCI_SCRATCH_REG_4       0x48    /* 16 bits */
113
#define PCI_SCRATCH_REG_5       0x4A    /* 16 bits */
114
#define PCI_SCRATCH_REG_6       0x4C    /* 16 bits */
115
#define PCI_SCRATCH_REG_7       0x4E    /* 16 bits */
116
 
117
/*** SCSI block ***/
118
#define CTCLREG                 0x00    /* r    current transf. count, low byte    */
119
#define CTCMREG                 0x04    /* r    current transf. count, middle byte */
120
#define CTCHREG                 0x38    /* r    current transf. count, high byte   */
121
#define STCLREG                 0x00    /* w    start transf. count, low byte      */
122
#define STCMREG                 0x04    /* w    start transf. count, middle byte   */
123
#define STCHREG                 0x38    /* w    start transf. count, high byte     */
124
#define FFREG                   0x08    /* rw   SCSI FIFO reg.                     */
125
#define STIMREG                 0x14    /* w    SCSI timeout reg.                  */
126
 
127
#define SDIDREG                 0x10    /* w    SCSI destination ID reg.           */
128
#define SDIREG_MASK             0x07    /* mask                                    */
129
 
130
#define STPREG                  0x18    /* w    synchronous transf. period reg.    */
131
#define STPREG_STP              0x1F    /* synchr. transfer period                 */
132
 
133
#define CLKFREG                 0x24    /* w    clock factor reg.                  */
134
#define CLKFREG_MASK            0x07    /* mask                                    */
135
 
136
#define CMDREG                  0x0C    /* rw   SCSI command reg.                  */
137
#define CMDREG_DMA              0x80    /* set DMA mode (set together with opcodes below) */
138
#define CMDREG_IT               0x10    /* information transfer                    */
139
#define CMDREG_ICCS             0x11    /* initiator command complete steps        */
140
#define CMDREG_MA               0x12    /* message accepted                        */
141
#define CMDREG_TPB              0x98    /* transfer pad bytes, DMA mode only       */
142
#define CMDREG_SATN             0x1A    /* set ATN                                 */
143
#define CMDREG_RATN             0x1B    /* reset ATN                               */
144
#define CMDREG_SOAS             0x41    /* select without ATN steps                */
145
#define CMDREG_SAS              0x42    /* select with ATN steps (1 msg byte)      */
146
#define CMDREG_SASS             0x43    /* select with ATN and stop steps          */
147
#define CMDREG_ESR              0x44    /* enable selection/reselection            */
148
#define CMDREG_DSR              0x45    /* disable selection/reselection           */
149
#define CMDREG_SA3S             0x46    /* select with ATN 3 steps  (3 msg bytes)  */
150
#define CMDREG_NOP              0x00    /* no operation                            */
151
#define CMDREG_CFIFO            0x01    /* clear FIFO                              */
152
#define CMDREG_RDEV             0x02    /* reset device                            */
153
#define CMDREG_RBUS             0x03    /* reset SCSI bus                          */
154
 
155
#define STATREG                 0x10    /* r    SCSI status reg.                   */
156
#define STATREG_INT             0x80    /* SCSI interrupt condition detected       */
157
#define STATREG_IOE             0x40    /* SCSI illegal operation error detected   */
158
#define STATREG_PE              0x20    /* SCSI parity error detected              */
159
#define STATREG_CTZ             0x10    /* CTC reg decremented to zero             */
160
#define STATREG_MSG             0x04    /* SCSI MSG phase (latched?)               */
161
#define STATREG_CD              0x02    /* SCSI C/D phase (latched?)               */
162
#define STATREG_IO              0x01    /* SCSI I/O phase (latched?)               */
163
#define STATREG_PHASE           0x07    /* SCSI phase mask                         */
164
 
165
#define INSTREG                 0x14    /* r    interrupt status reg.              */
166
#define INSTREG_SRST            0x80    /* SCSI reset detected                     */
167
#define INSTREG_ICMD            0x40    /* SCSI invalid command detected           */
168
#define INSTREG_DIS             0x20    /* target disconnected or sel/resel timeout*/
169
#define INSTREG_SR              0x10    /* device on bus has service request       */
170
#define INSTREG_SO              0x08    /* successful operation                    */
171
#define INSTREG_RESEL           0x04    /* device reselected as initiator          */
172
 
173
#define ISREG                   0x18    /* r    internal state reg.                */
174
#define ISREG_SOF               0x08    /* synchronous offset flag (act. low)      */
175
#define ISREG_IS                0x07    /* status of intermediate op.              */
176
#define ISREG_OK_NO_STOP        0x04    /* selection successful                    */
177
#define ISREG_OK_STOP           0x01    /* selection successful                    */
178
 
179
#define CFIREG                  0x1C    /* r    current FIFO/internal state reg.   */
180
#define CFIREG_IS               0xE0    /* status of intermediate op.              */
181
#define CFIREG_CF               0x1F    /* number of bytes in SCSI FIFO            */
182
 
183
#define SOFREG                  0x1C    /* w    synchr. offset reg.                */
184
#define SOFREG_RAD              0xC0    /* REQ/ACK deassertion delay (sync.)       */
185
#define SOFREG_RAA              0x30    /* REQ/ACK assertion delay (sync.)         */
186
#define SOFREG_SO               0x0F    /* synch. offset (sync.)                   */
187
 
188
#define CNTLREG1                0x20    /* rw   control register one               */
189
#define CNTLREG1_ETM            0x80    /* set extended timing mode                */
190
#define CNTLREG1_DISR           0x40    /* disable interrupt on SCSI reset         */
191
#define CNTLREG1_PERE           0x10    /* enable parity error reporting           */
192
#define CNTLREG1_SID            0x07    /* host adapter SCSI ID                    */
193
 
194
#define CNTLREG2                0x2C    /* rw   control register two               */
195
#define CNTLREG2_ENF            0x40    /* enable features                         */
196
 
197
#define CNTLREG3                0x30    /* rw   control register three             */ 
198
#define CNTLREG3_ADIDCHK        0x80    /* additional ID check                     */
199
#define CNTLREG3_FASTSCSI       0x10    /* fast SCSI                               */
200
#define CNTLREG3_FASTCLK        0x08    /* fast SCSI clocking                      */
201
 
202
#define CNTLREG4                0x34    /* rw   control register four              */ 
203
#define CNTLREG4_GLITCH         0xC0    /* glitch eater                            */
204
#define CNTLREG4_PWD            0x20    /* reduced power feature                   */
205
#define CNTLREG4_RAE            0x08    /* write only, active negot. ctrl.         */
206
#define CNTLREG4_RADE           0x04    /* active negot. ctrl.                     */
207
#define CNTLREG4_RES            0x10    /* reserved bit, must be 1                 */
208
 
209
/*** DMA block ***/
210
#define DMACMD                  0x40    /* rw   command                            */
211
#define DMACMD_DIR              0x80    /* transfer direction (1=read from device) */
212
#define DMACMD_INTE_D           0x40    /* DMA transfer interrupt enable           */
213
#define DMACMD_INTE_P           0x20    /* page transfer interrupt enable          */
214
#define DMACMD_MDL              0x10    /* map to memory descriptor list           */
215
#define DMACMD_DIAG             0x04    /* diagnostics, set to 0                   */
216
#define DMACMD_IDLE             0x00    /* idle cmd                                */
217
#define DMACMD_BLAST            0x01    /* flush FIFO to memory                    */
218
#define DMACMD_ABORT            0x02    /* terminate DMA                           */
219
#define DMACMD_START            0x03    /* start DMA                               */
220
 
221
#define DMASTATUS               0x54    /* r    status register                    */
222
#define DMASTATUS_BCMPLT        0x20    /* BLAST complete                          */
223
#define DMASTATUS_SCSIINT       0x10    /* SCSI interrupt pending                  */
224
#define DMASTATUS_DONE          0x08    /* DMA transfer terminated                 */
225
#define DMASTATUS_ABORT         0x04    /* DMA transfer aborted                    */
226
#define DMASTATUS_ERROR         0x02    /* DMA transfer error                      */
227
#define DMASTATUS_PWDN          0x02    /* power down indicator                    */
228
 
229
#define DMASTC                  0x44    /* rw   starting transfer count            */
230
#define DMASPA                  0x48    /* rw   starting physical address          */
231
#define DMAWBC                  0x4C    /* r    working byte counter               */
232
#define DMAWAC                  0x50    /* r    working address counter            */
233
#define DMASMDLA                0x58    /* rw   starting MDL address               */
234
#define DMAWMAC                 0x5C    /* r    working MDL counter                */
235
 
236
/*** SCSI phases ***/
237
#define PHASE_MSGIN             0x07
238
#define PHASE_MSGOUT            0x06
239
#define PHASE_RES_1             0x05
240
#define PHASE_RES_0             0x04
241
#define PHASE_STATIN            0x03
242
#define PHASE_CMDOUT            0x02
243
#define PHASE_DATAIN            0x01
244
#define PHASE_DATAOUT           0x00
245
 
246
struct AM53C974_hostdata {
247
    volatile unsigned       in_reset:1;          /* flag, says bus reset pending */
248
    volatile unsigned       aborted:1;           /* flag, says aborted */
249
    volatile unsigned       selecting:1;         /* selection started, but not yet finished */
250
    volatile unsigned       disconnecting: 1;    /* disconnection started, but not yet finished */
251
    volatile unsigned       dma_busy:1;          /* dma busy when service request for info transfer received */
252
    volatile unsigned  char msgout[10];          /* message to output in MSGOUT_PHASE */
253
    volatile unsigned  char last_message[10];   /* last message OUT */
254
    volatile Scsi_Cmnd      *issue_queue;       /* waiting to be issued */
255
    volatile Scsi_Cmnd      *disconnected_queue;        /* waiting for reconnect */
256
    volatile Scsi_Cmnd      *sel_cmd;            /* command for selection */
257
    volatile Scsi_Cmnd      *connected;         /* currently connected command */
258
    volatile unsigned  char busy[8];            /* index = target, bit = lun */
259
    unsigned  char sync_per[8];         /* synchronous transfer period (in effect) */
260
    unsigned  char sync_off[8];         /* synchronous offset (in effect) */
261
    unsigned  char sync_neg[8];         /* sync. negotiation performed (in effect) */
262
    unsigned  char sync_en[8];          /* sync. negotiation performed (in effect) */
263
    unsigned  char max_rate[8];         /* max. transfer rate (setup) */
264
    unsigned  char max_offset[8];       /* max. sync. offset (setup), only valid if corresponding sync_en is nonzero */
265
    };
266
 
267
#define AM53C974 { \
268
    NULL,                       /* pointer to next in list                      */  \
269
    NULL,                       /* long * usage_count                           */  \
270
    NULL,                       /* struct proc_dir_entry *proc_dir              */ \
271
    NULL,                       /* int (*proc_info)(char *, char **, off_t, int, int, int); */ \
272
    "AM53C974",                 /* name                                         */  \
273
    AM53C974_detect,            /* int (* detect)(struct SHT *)                 */  \
274
    NULL,                       /* int (*release)(struct Scsi_Host *)           */  \
275
    AM53C974_info,              /* const char *(* info)(struct Scsi_Host *)     */  \
276
    AM53C974_command,           /* int (* command)(Scsi_Cmnd *)                 */  \
277
    AM53C974_queue_command,     /* int (* queuecommand)(Scsi_Cmnd *,                \
278
                                           void (*done)(Scsi_Cmnd *))           */  \
279
    AM53C974_abort,             /* int (* abort)(Scsi_Cmnd *)                   */  \
280
    AM53C974_reset,             /* int (* reset)(Scsi_Cmnd *)                   */  \
281
    NULL,                       /* int (* slave_attach)(int, int)               */  \
282
    scsicam_bios_param,         /* int (* bios_param)(Disk *, int, int[])       */  \
283
    12,                         /* can_queue                                    */  \
284
    -1,                         /* this_id                                      */  \
285
    SG_ALL,                     /* sg_tablesize                                 */  \
286
    1,                          /* cmd_per_lun                                  */  \
287
    0,                           /* present, i.e. how many adapters of this kind */  \
288
    0,                           /* unchecked_isa_dma                            */  \
289
    DISABLE_CLUSTERING          /* use_clustering                               */  \
290
    }
291
 
292
void AM53C974_setup(char *str, int *ints);
293
int AM53C974_detect(Scsi_Host_Template *tpnt);
294
int AM53C974_biosparm(Disk *disk, int dev, int *info_array);
295
const char *AM53C974_info(struct Scsi_Host *);
296
int AM53C974_command(Scsi_Cmnd *SCpnt);
297
int AM53C974_queue_command(Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
298
int AM53C974_abort(Scsi_Cmnd *cmd);
299
int AM53C974_reset (Scsi_Cmnd *cmd, unsigned int flags);
300
 
301
#define AM53C974_local_declare()        unsigned long io_port
302
#define AM53C974_setio(instance)        io_port = instance->io_port
303
#define AM53C974_read_8(addr)           inb(io_port + (addr))
304
#define AM53C974_write_8(addr,x)        outb((x), io_port + (addr))
305
#define AM53C974_read_16(addr)          inw(io_port + (addr))
306
#define AM53C974_write_16(addr,x)       outw((x), io_port + (addr))
307
#define AM53C974_read_32(addr)          inl(io_port + (addr))
308
#define AM53C974_write_32(addr,x)       outl((x), io_port + (addr))
309
 
310
#define AM53C974_poll_int()             { do { statreg = AM53C974_read_8(STATREG); } \
311
                                             while (!(statreg & STATREG_INT)) ; \
312
                                          AM53C974_read_8(INSTREG) ; } /* clear int */
313
#define AM53C974_cfifo()                (AM53C974_read_8(CFIREG) & CFIREG_CF)
314
 
315
/* These are "special" values for the tag parameter passed to AM53C974_select. */
316
#define TAG_NEXT        -1      /* Use next free tag */
317
#define TAG_NONE        -2      /* Establish I_T_L nexus instead of I_T_L_Q
318
                                 * even on SCSI-II devices */
319
 
320
/************ LILO overrides *************/
321
typedef struct _override_t {
322
    int host_scsi_id;                   /* SCSI id of the bus controller */
323
    int target_scsi_id;                 /* SCSI id of target */
324
    int max_rate;                       /* max. transfer rate */
325
    int max_offset;                     /* max. sync. offset, 0 = asynchronous */
326
    } override_t;
327
 
328
/************ PCI stuff *************/
329
#define AM53C974_PCIREG_OPEN()                    outb(0xF1, 0xCF8); outb(0, 0xCFA)
330
#define AM53C974_PCIREG_CLOSE()                   outb(0, 0xCF8)
331
#define AM53C974_PCIREG_READ_BYTE(instance,a)     ( inb((a) + (instance)->io_port) )
332
#define AM53C974_PCIREG_READ_WORD(instance,a)     ( inw((a) + (instance)->io_port) )
333
#define AM53C974_PCIREG_READ_DWORD(instance,a)    ( inl((a) + (instance)->io_port) )
334
#define AM53C974_PCIREG_WRITE_BYTE(instance,x,a)  ( outb((x), (a) + (instance)->io_port) )
335
#define AM53C974_PCIREG_WRITE_WORD(instance,x,a)  ( outw((x), (a) + (instance)->io_port) )
336
#define AM53C974_PCIREG_WRITE_DWORD(instance,x,a) ( outl((x), (a) + (instance)->io_port) )
337
 
338
typedef struct _pci_config_t {
339
    /* start of official PCI config space header */
340
    union {
341
        unsigned int device_vendor;
342
        struct {
343
          unsigned short vendor;
344
          unsigned short device;
345
          } dv;
346
        } dv_id;
347
#define _device_vendor dv_id.device_vendor
348
#define _vendor dv_id.dv.vendor
349
#define _device dv_id.dv.device
350
    union {
351
        unsigned int status_command;
352
        struct {
353
          unsigned short command;
354
          unsigned short status;
355
          } sc;
356
        } stat_cmd;
357
#define _status_command stat_cmd.status_command
358
#define _command stat_cmd.sc.command
359
#define _status  stat_cmd.sc.status
360
    union {
361
        unsigned int class_revision;
362
        struct {
363
            unsigned char rev_id;
364
            unsigned char prog_if;
365
            unsigned char sub_class;
366
            unsigned char base_class;
367
        } cr;
368
    } class_rev;
369
#define _class_revision class_rev.class_revision
370
#define _rev_id     class_rev.cr.rev_id
371
#define _prog_if    class_rev.cr.prog_if
372
#define _sub_class  class_rev.cr.sub_class
373
#define _base_class class_rev.cr.base_class
374
    union {
375
        unsigned int bist_header_latency_cache;
376
        struct {
377
            unsigned char cache_line_size;
378
            unsigned char latency_timer;
379
            unsigned char header_type;
380
            unsigned char bist;
381
        } bhlc;
382
    } bhlc;
383
#define _bist_header_latency_cache bhlc.bist_header_latency_cache
384
#define _cache_line_size bhlc.bhlc.cache_line_size
385
#define _latency_timer   bhlc.bhlc.latency_timer
386
#define _header_type     bhlc.bhlc.header_type
387
#define _bist            bhlc.bhlc.bist
388
    unsigned int _base0;
389
    unsigned int _base1;
390
    unsigned int _base2;
391
    unsigned int _base3;
392
    unsigned int _base4;
393
    unsigned int _base5;
394
    unsigned int rsvd1;
395
    unsigned int rsvd2;
396
    unsigned int _baserom;
397
    unsigned int rsvd3;
398
    unsigned int rsvd4;
399
    union {
400
        unsigned int max_min_ipin_iline;
401
        struct {
402
            unsigned char int_line;
403
            unsigned char int_pin;
404
            unsigned char min_gnt;
405
            unsigned char max_lat;
406
        } mmii;
407
    } mmii;
408
#define _max_min_ipin_iline mmii.max_min_ipin_iline
409
#define _int_line mmii.mmii.int_line
410
#define _int_pin  mmii.mmii.int_pin
411
#define _min_gnt  mmii.mmii.min_gnt
412
#define _max_lat  mmii.mmii.max_lat
413
    /* end of official PCI config space header */
414
    unsigned short _ioaddr; /* config type 1 - private I/O addr    */
415
    unsigned int _pcibus;  /* config type 2 - private bus id      */
416
    unsigned int _cardnum; /* config type 2 - private card number */
417
} pci_config_t;
418
 
419
#endif /* AM53C974_H */

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