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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [include/] [asm-alpha/] [fpu.h] - Blame information for rev 1765

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1 1632 jcastillo
#ifndef __ASM_ALPHA_FPU_H
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#define __ASM_ALPHA_FPU_H
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/*
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 * Alpha floating-point control register defines:
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 */
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#define FPCR_INVD       (1UL<<49)       /* invalid op disable (opt.) */
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#define FPCR_DZED       (1UL<<50)       /* division by zero disable (opt.) */
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#define FPCR_OVFD       (1UL<<51)       /* overflow disable (optional) */
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#define FPCR_INV        (1UL<<52)       /* invalid operation */
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#define FPCR_DZE        (1UL<<53)       /* division by zero */
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#define FPCR_OVF        (1UL<<54)       /* overflow */
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#define FPCR_UNF        (1UL<<55)       /* underflow */
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#define FPCR_INE        (1UL<<56)       /* inexact */
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#define FPCR_IOV        (1UL<<57)       /* integer overflow */
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#define FPCR_UNDZ       (1UL<<60)       /* underflow to zero (opt.) */
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#define FPCR_UNFD       (1UL<<61)       /* underflow disable (opt.) */
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#define FPCR_INED       (1UL<<62)       /* inexact disable (opt.) */
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#define FPCR_SUM        (1UL<<63)       /* summary bit */
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#define FPCR_DYN_SHIFT  58              /* first dynamic rounding mode bit */
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#define FPCR_DYN_CHOPPED (0x0UL << FPCR_DYN_SHIFT)      /* towards 0 */
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#define FPCR_DYN_MINUS   (0x1UL << FPCR_DYN_SHIFT)      /* towards -INF */
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#define FPCR_DYN_NORMAL  (0x2UL << FPCR_DYN_SHIFT)      /* towards nearest */
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#define FPCR_DYN_PLUS    (0x3UL << FPCR_DYN_SHIFT)      /* towards +INF */
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#define FPCR_DYN_MASK    (0x3UL << FPCR_DYN_SHIFT)
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#define FPCR_MASK       0xfffe000000000000
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/*
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 * IEEE trap enables are implemented in software.  These per-thread
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 * bits are stored in the "flags" field of "struct thread_struct".
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 * Thus, the bits are defined so as not to conflict with the
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 * floating-point enable bit (which is architected).  On top of that,
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 * we want to make these bits compatible with OSF/1 so
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 * ieee_set_fp_control() etc. can be implemented easily and
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 * compatibly.  The corresponding definitions are in
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 * /usr/include/machine/fpu.h under OSF/1.
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 */
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#define IEEE_TRAP_ENABLE_INV    (1<<1)  /* invalid op */
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#define IEEE_TRAP_ENABLE_DZE    (1<<2)  /* division by zero */
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#define IEEE_TRAP_ENABLE_OVF    (1<<3)  /* overflow */
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#define IEEE_TRAP_ENABLE_UNF    (1<<4)  /* underflow */
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#define IEEE_TRAP_ENABLE_INE    (1<<5)  /* inexact */
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#define IEEE_TRAP_ENABLE_MASK   (IEEE_TRAP_ENABLE_INV | IEEE_TRAP_ENABLE_DZE |\
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                                 IEEE_TRAP_ENABLE_OVF | IEEE_TRAP_ENABLE_UNF |\
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                                 IEEE_TRAP_ENABLE_INE)
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/* status bits coming from fpcr: */
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#define IEEE_STATUS_INV         (1<<17)
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#define IEEE_STATUS_DZE         (1<<18)
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#define IEEE_STATUS_OVF         (1<<19)
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#define IEEE_STATUS_UNF         (1<<20)
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#define IEEE_STATUS_INE         (1<<21)
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#define IEEE_STATUS_MASK        (IEEE_STATUS_INV | IEEE_STATUS_DZE |    \
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                                 IEEE_STATUS_OVF | IEEE_STATUS_UNF |    \
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                                 IEEE_STATUS_INE)
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#define IEEE_SW_MASK            (IEEE_TRAP_ENABLE_MASK | IEEE_STATUS_MASK)
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#define IEEE_STATUS_TO_EXCSUM_SHIFT     16
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#define IEEE_INHERIT    (1UL<<63)       /* inherit on thread create? */
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/*
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 * Convert the software IEEE trap enables and status bits into the
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 * hardware fpcr format.
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 */
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static inline unsigned long
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ieee_sw_to_fpcr(unsigned long sw)
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{
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        unsigned long fpcw;
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        fpcw = (sw & IEEE_STATUS_MASK) << 35;
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        fpcw |= sw & IEEE_STATUS_MASK ? FPCR_SUM : 0;
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        fpcw |= (~sw & (IEEE_TRAP_ENABLE_INV
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                        | IEEE_TRAP_ENABLE_DZE
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                        | IEEE_TRAP_ENABLE_OVF)) << 48;
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        fpcw |= (~sw & (IEEE_TRAP_ENABLE_UNF | IEEE_TRAP_ENABLE_INE)) << 57;
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        return fpcw;
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}
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#endif /* __ASM_ALPHA_FPU_H */

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