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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [include/] [asm-armnommu/] [proc-armo/] [system.h] - Blame information for rev 1777

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/*
 * linux/include/asm-arm/proc-armo/system.h
 *
 * Copyright (C) 1995, 1996 Russell King
 */
 
#ifndef __ASM_PROC_SYSTEM_H
#define __ASM_PROC_SYSTEM_H
 
extern const char xchg_str[];
 
#include <asm/proc-fns.h>
 
extern __inline__ unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
{
        switch (size) {
                case 1: return processor.u.armv2._xchg_1(x, ptr);
                case 2: return processor.u.armv2._xchg_2(x, ptr);
                case 4: return processor.u.armv2._xchg_4(x, ptr);
                default: arm_invalidptr(xchg_str, size);
        }
}
 
/*
 * We need to turn the caches off before calling the reset vector - RiscOS
 * messes up if we don't
 */
#define proc_hard_reset()       processor._proc_fin()
 
/*
 * This processor does not idle
 */
#define proc_idle()
 
/*
 * A couple of speedups for the ARM
 */
 
/*
 * Save the current interrupt enable state & disable IRQs
 */
#define save_flags_cli(x)               \
        do {                            \
          unsigned long temp;           \
          __asm__ __volatile__(         \
"       mov     %0, pc\n"               \
"       orr     %1, %0, #0x08000000\n"  \
"       and     %0, %0, #0x0c000000\n"  \
"       teqp    %1, #0\n"               \
          : "=r" (x), "=r" (temp)       \
          :                             \
          : "memory");                  \
        } while (0)
 
/*
 * Enable IRQs
 */
#define sti()                           \
        do {                            \
          unsigned long temp;           \
          __asm__ __volatile__(         \
"       mov     %0, pc\n"               \
"       bic     %0, %0, #0x08000000\n"  \
"       teqp    %0, #0\n"               \
          : "=r" (temp)                 \
          :                             \
          : "memory");                  \
        } while(0)
 
/*
 * Disable IRQs
 */
#define cli()                           \
        do {                            \
          unsigned long temp;           \
          __asm__ __volatile__(         \
"       mov     %0, pc\n"               \
"       orr     %0, %0, #0x08000000\n"  \
"       teqp    %0, #0\n"               \
          : "=r" (temp)                 \
          :                             \
          : "memory");                  \
        } while(0)
 
/*
 * save current IRQ & FIQ state
 */
#define save_flags(x)                   \
        do {                            \
          __asm__ __volatile__(         \
"       mov     %0, pc\n"               \
"       and     %0, %0, #0x0c000000\n"  \
          : "=r" (x));                  \
        } while (0)
 
/*
 * restore saved IRQ & FIQ state
 */
#define restore_flags(x)                \
        do {                            \
          unsigned long temp;           \
          __asm__ __volatile__(         \
"       mov     %0, pc\n"               \
"       bic     %0, %0, #0x0c000000\n"  \
"       orr     %0, %0, %1\n"           \
"       teqp    %0, #0\n"               \
          : "=r" (temp)                 \
          : "r" (x)                     \
          : "memory");                  \
        } while (0)
 
#endif

Line No.	Rev	Author	Line
1	1633	jcastillo	`/*`
2			`* linux/include/asm-arm/proc-armo/system.h`
3			`*`
4			`* Copyright (C) 1995, 1996 Russell King`
5			`*/`
6
7			`#ifndef __ASM_PROC_SYSTEM_H`
8			`#define __ASM_PROC_SYSTEM_H`
9
10			`extern const char xchg_str[];`
11
12			`#include <asm/proc-fns.h>`
13
14			`extern __inline__ unsigned long __xchg(unsigned long x, volatile void *ptr, int size)`
15			`{`
16			`switch (size) {`
17			`case 1: return processor.u.armv2._xchg_1(x, ptr);`
18			`case 2: return processor.u.armv2._xchg_2(x, ptr);`
19			`case 4: return processor.u.armv2._xchg_4(x, ptr);`
20			`default: arm_invalidptr(xchg_str, size);`
21			`}`
22			`}`
23
24			`/*`
25			`* We need to turn the caches off before calling the reset vector - RiscOS`
26			`* messes up if we don't`
27			`*/`
28			`#define proc_hard_reset() processor._proc_fin()`
29
30			`/*`
31			`* This processor does not idle`
32			`*/`
33			`#define proc_idle()`
34
35			`/*`
36			`* A couple of speedups for the ARM`
37			`*/`
38
39			`/*`
40			`* Save the current interrupt enable state & disable IRQs`
41			`*/`
42			`#define save_flags_cli(x) \`
43			`do { \`
44			`unsigned long temp; \`
45			`__asm__ __volatile__( \`
46			`" mov %0, pc\n" \`
47			`" orr %1, %0, #0x08000000\n" \`
48			`" and %0, %0, #0x0c000000\n" \`
49			`" teqp %1, #0\n" \`
50			`: "=r" (x), "=r" (temp) \`
51			`: \`
52			`: "memory"); \`
53			`} while (0)`
54
55			`/*`
56			`* Enable IRQs`
57			`*/`
58			`#define sti() \`
59			`do { \`
60			`unsigned long temp; \`
61			`__asm__ __volatile__( \`
62			`" mov %0, pc\n" \`
63			`" bic %0, %0, #0x08000000\n" \`
64			`" teqp %0, #0\n" \`
65			`: "=r" (temp) \`
66			`: \`
67			`: "memory"); \`
68			`} while(0)`
69
70			`/*`
71			`* Disable IRQs`
72			`*/`
73			`#define cli() \`
74			`do { \`
75			`unsigned long temp; \`
76			`__asm__ __volatile__( \`
77			`" mov %0, pc\n" \`
78			`" orr %0, %0, #0x08000000\n" \`
79			`" teqp %0, #0\n" \`
80			`: "=r" (temp) \`
81			`: \`
82			`: "memory"); \`
83			`} while(0)`
84
85			`/*`
86			`* save current IRQ & FIQ state`
87			`*/`
88			`#define save_flags(x) \`
89			`do { \`
90			`__asm__ __volatile__( \`
91			`" mov %0, pc\n" \`
92			`" and %0, %0, #0x0c000000\n" \`
93			`: "=r" (x)); \`
94			`} while (0)`
95
96			`/*`
97			`* restore saved IRQ & FIQ state`
98			`*/`
99			`#define restore_flags(x) \`
100			`do { \`
101			`unsigned long temp; \`
102			`__asm__ __volatile__( \`
103			`" mov %0, pc\n" \`
104			`" bic %0, %0, #0x0c000000\n" \`
105			`" orr %0, %0, %1\n" \`
106			`" teqp %0, #0\n" \`
107			`: "=r" (temp) \`
108			`: "r" (x) \`
109			`: "memory"); \`
110			`} while (0)`
111
112			`#endif`

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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [include/] [asm-armnommu/] [proc-armo/] [system.h] - Blame information for rev 1777