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/*
 * linux/asm-arm/proc-armv/assembler.h
 *
 * Copyright (C) 1996 Russell King
 *
 * This file contains arm architecture specific defines
 * for the different processors
 */
 
/*
 * LOADREGS: multiple register load (ldm) with pc in register list
 *              (takes account of ARM6 not using ^)
 *
 * RETINSTR: return instruction: adds the 's' in at the end of the
 *              instruction if this is not an ARM6
 *
 * SAVEIRQS: save IRQ state (not required on ARM2/ARM3 - done
 *              implicitly
 *
 * RESTOREIRQS: restore IRQ state (not required on ARM2/ARM3 - done
 *              implicitly with ldm ... ^ or movs.
 *
 * These next two need thinking about - can't easily use stack... (see system.S)
 * DISABLEIRQS: disable IRQS in SVC mode
 *
 * ENABLEIRQS: enable IRQS in SVC mode
 *
 * USERMODE: switch to USER mode
 *
 * SVCMODE: switch to SVC mode
 */
 
#define N_BIT   (1 << 31)
#define Z_BIT   (1 << 30)
#define C_BIT   (1 << 29)
#define V_BIT   (1 << 28)
 
#define PCMASK  0
 
#ifdef __ASSEMBLER__
 
#define I_BIT   (1 << 7)
#define F_BIT   (1 << 6)
 
#define MODE_FIQ26      0x01
#define MODE_FIQ32      0x11
 
#define DEFAULT_FIQ     MODE_FIQ32
 
#define LOADREGS(cond, base, reglist...)\
        ldm##cond       base,reglist
 
#define RETINSTR(instr, regs...)\
        instr   regs
 
#define MODENOP
 
#define MODE(savereg,tmpreg,mode) \
        mrs     savereg, cpsr; \
        bic     tmpreg, savereg, $0x1f; \
        orr     tmpreg, tmpreg, $mode; \
        msr     cpsr, tmpreg
 
#define RESTOREMODE(savereg) \
        msr     cpsr, savereg
 
#define SAVEIRQS(tmpreg)\
        mrs     tmpreg, cpsr; \
        str     tmpreg, [sp, $-4]!
 
#define RESTOREIRQS(tmpreg)\
        ldr     tmpreg, [sp], $4; \
        msr     cpsr, tmpreg
 
#define DISABLEIRQS(tmpreg)\
        mrs     tmpreg , cpsr; \
        orr     tmpreg , tmpreg , $I_BIT; \
        msr     cpsr, tmpreg
 
#define ENABLEIRQS(tmpreg)\
        mrs     tmpreg , cpsr; \
        bic     tmpreg , tmpreg , $I_BIT; \
        msr     cpsr, tmpreg
#endif

Line No.	Rev	Author	Line
1	1633	jcastillo	`/*`
2			`* linux/asm-arm/proc-armv/assembler.h`
3			`*`
4			`* Copyright (C) 1996 Russell King`
5			`*`
6			`* This file contains arm architecture specific defines`
7			`* for the different processors`
8			`*/`
9
10			`/*`
11			`* LOADREGS: multiple register load (ldm) with pc in register list`
12			`* (takes account of ARM6 not using ^)`
13			`*`
14			`* RETINSTR: return instruction: adds the 's' in at the end of the`
15			`* instruction if this is not an ARM6`
16			`*`
17			`* SAVEIRQS: save IRQ state (not required on ARM2/ARM3 - done`
18			`* implicitly`
19			`*`
20			`* RESTOREIRQS: restore IRQ state (not required on ARM2/ARM3 - done`
21			`* implicitly with ldm ... ^ or movs.`
22			`*`
23			`* These next two need thinking about - can't easily use stack... (see system.S)`
24			`* DISABLEIRQS: disable IRQS in SVC mode`
25			`*`
26			`* ENABLEIRQS: enable IRQS in SVC mode`
27			`*`
28			`* USERMODE: switch to USER mode`
29			`*`
30			`* SVCMODE: switch to SVC mode`
31			`*/`
32
33			`#define N_BIT (1 << 31)`
34			`#define Z_BIT (1 << 30)`
35			`#define C_BIT (1 << 29)`
36			`#define V_BIT (1 << 28)`
37
38			`#define PCMASK 0`
39
40			`#ifdef __ASSEMBLER__`
41
42			`#define I_BIT (1 << 7)`
43			`#define F_BIT (1 << 6)`
44
45			`#define MODE_FIQ26 0x01`
46			`#define MODE_FIQ32 0x11`
47
48			`#define DEFAULT_FIQ MODE_FIQ32`
49
50			`#define LOADREGS(cond, base, reglist...)\`
51			`ldm##cond base,reglist`
52
53			`#define RETINSTR(instr, regs...)\`
54			`instr regs`
55
56			`#define MODENOP`
57
58			`#define MODE(savereg,tmpreg,mode) \`
59			`mrs savereg, cpsr; \`
60			`bic tmpreg, savereg, $0x1f; \`
61			`orr tmpreg, tmpreg, $mode; \`
62			`msr cpsr, tmpreg`
63
64			`#define RESTOREMODE(savereg) \`
65			`msr cpsr, savereg`
66
67			`#define SAVEIRQS(tmpreg)\`
68			`mrs tmpreg, cpsr; \`
69			`str tmpreg, [sp, $-4]!`
70
71			`#define RESTOREIRQS(tmpreg)\`
72			`ldr tmpreg, [sp], $4; \`
73			`msr cpsr, tmpreg`
74
75			`#define DISABLEIRQS(tmpreg)\`
76			`mrs tmpreg , cpsr; \`
77			`orr tmpreg , tmpreg , $I_BIT; \`
78			`msr cpsr, tmpreg`
79
80			`#define ENABLEIRQS(tmpreg)\`
81			`mrs tmpreg , cpsr; \`
82			`bic tmpreg , tmpreg , $I_BIT; \`
83			`msr cpsr, tmpreg`
84			`#endif`

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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [include/] [asm-armnommu/] [proc-trio/] [assembler.h] - Blame information for rev 1633