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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [include/] [asm-i386/] [smp.h] - Blame information for rev 1765

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1 1633 jcastillo
#ifndef __ASM_SMP_H
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#define __ASM_SMP_H
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#ifdef __SMP__
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#ifndef ASSEMBLY
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#include <asm/i82489.h>
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#include <asm/bitops.h>
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#include <linux/tasks.h>
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#include <linux/ptrace.h>
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/*
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 *      Support definitions for SMP machines following the intel multiprocessing
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 *      specification
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 */
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/*
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 *      This tag identifies where the SMP configuration
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 *      information is.
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 */
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#define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_')
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struct intel_mp_floating
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{
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        char mpf_signature[4];          /* "_MP_"                       */
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        unsigned long mpf_physptr;      /* Configuration table address  */
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        unsigned char mpf_length;       /* Our length (paragraphs)      */
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        unsigned char mpf_specification;/* Specification version        */
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        unsigned char mpf_checksum;     /* Checksum (makes sum 0)       */
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        unsigned char mpf_feature1;     /* Standard or configuration ?  */
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        unsigned char mpf_feature2;     /* Bit7 set for IMCR|PIC        */
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        unsigned char mpf_feature3;     /* Unused (0)                   */
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        unsigned char mpf_feature4;     /* Unused (0)                   */
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        unsigned char mpf_feature5;     /* Unused (0)                   */
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};
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struct mp_config_table
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{
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        char mpc_signature[4];
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#define MPC_SIGNATURE "PCMP"
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        unsigned short mpc_length;      /* Size of table */
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        char  mpc_spec;                 /* 0x01 */
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        char  mpc_checksum;
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        char  mpc_oem[8];
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        char  mpc_productid[12];
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        unsigned long mpc_oemptr;       /* 0 if not present */
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        unsigned short mpc_oemsize;     /* 0 if not present */
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        unsigned short mpc_oemcount;
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        unsigned long mpc_lapic;        /* APIC address */
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        unsigned long reserved;
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};
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/* Followed by entries */
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#define MP_PROCESSOR    0
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#define MP_BUS          1
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#define MP_IOAPIC       2
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#define MP_INTSRC       3
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#define MP_LINTSRC      4
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struct mpc_config_processor
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{
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        unsigned char mpc_type;
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        unsigned char mpc_apicid;       /* Local APIC number */
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        unsigned char mpc_apicver;      /* Its versions */
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        unsigned char mpc_cpuflag;
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#define CPU_ENABLED             1       /* Processor is available */
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#define CPU_BOOTPROCESSOR       2       /* Processor is the BP */
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        unsigned long mpc_cpufeature;
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#define CPU_STEPPING_MASK 0x0F
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#define CPU_MODEL_MASK  0xF0
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#define CPU_FAMILY_MASK 0xF00
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        unsigned long mpc_featureflag;  /* CPUID feature value */
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        unsigned long mpc_reserved[2];
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};
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struct mpc_config_bus
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{
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        unsigned char mpc_type;
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        unsigned char mpc_busid;
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        unsigned char mpc_bustype[6] __attribute((packed));
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};
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#define BUSTYPE_EISA    "EISA"
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#define BUSTYPE_ISA     "ISA"
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#define BUSTYPE_INTERN  "INTERN"        /* Internal BUS */
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#define BUSTYPE_MCA     "MCA"
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#define BUSTYPE_VL      "VL"            /* Local bus */
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#define BUSTYPE_PCI     "PCI"
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#define BUSTYPE_PCMCIA  "PCMCIA"
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/* We don't understand the others */
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struct mpc_config_ioapic
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{
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        unsigned char mpc_type;
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        unsigned char mpc_apicid;
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        unsigned char mpc_apicver;
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        unsigned char mpc_flags;
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#define MPC_APIC_USABLE         0x01
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        unsigned long mpc_apicaddr;
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};
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struct mpc_config_intsrc
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{
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        unsigned char mpc_type;
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        unsigned char mpc_irqtype;
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        unsigned short mpc_irqflag;
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        unsigned char mpc_srcbus;
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        unsigned char mpc_srcbusirq;
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        unsigned char mpc_dstapic;
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        unsigned char mpc_dstirq;
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};
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#define MP_INT_VECTORED         0
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#define MP_INT_NMI              1
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#define MP_INT_SMI              2
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#define MP_INT_EXTINT           3
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#define MP_IRQDIR_DEFAULT       0
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#define MP_IRQDIR_HIGH          1
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#define MP_IRQDIR_LOW           3
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struct mpc_config_intlocal
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{
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        unsigned char mpc_type;
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        unsigned char mpc_irqtype;
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        unsigned short mpc_irqflag;
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        unsigned char mpc_srcbusid;
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        unsigned char mpc_srcbusirq;
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        unsigned char mpc_destapic;
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#define MP_APIC_ALL     0xFF
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        unsigned char mpc_destapiclint;
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};
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/*
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 *      Default configurations
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 *
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 *      1       2 CPU ISA 82489DX
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 *      2       2 CPU EISA 82489DX no IRQ 8 or timer chaining
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 *      3       2 CPU EISA 82489DX
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 *      4       2 CPU MCA 82489DX
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 *      5       2 CPU ISA+PCI
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 *      6       2 CPU EISA+PCI
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 *      7       2 CPU MCA+PCI
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 */
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/*
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 *      Per process x86 parameters
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 */
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struct cpuinfo_x86
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{
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        char hard_math;
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        char x86;
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        char x86_model;
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        char x86_mask;
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        char x86_vendor_id[16];
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        int  x86_capability;
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        int  x86_ext_capability;
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        int  fdiv_bug;
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        int  have_cpuid;
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        char wp_works_ok;
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        char hlt_works_ok;
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        unsigned long udelay_val;
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};
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extern struct cpuinfo_x86 cpu_data[NR_CPUS];
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/*
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 *      Private routines/data
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 */
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extern int smp_found_config;
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extern int smp_scan_config(unsigned long, unsigned long);
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extern unsigned long smp_alloc_memory(unsigned long mem_base);
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extern unsigned char *apic_reg;
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extern unsigned char *kernel_stacks[NR_CPUS];
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extern unsigned char boot_cpu_id;
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extern unsigned long cpu_present_map;
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extern volatile int cpu_number_map[NR_CPUS];
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extern volatile int cpu_logical_map[NR_CPUS];
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extern volatile unsigned long smp_invalidate_needed;
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extern void smp_flush_tlb(void);
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extern volatile unsigned long kernel_flag, kernel_counter;
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extern volatile unsigned long cpu_callin_map[NR_CPUS];
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extern volatile unsigned char active_kernel_processor;
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extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs);
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extern void smp_reschedule_irq(int cpl, struct pt_regs *regs);
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extern unsigned long ipi_count;
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extern void smp_invalidate_rcv(void);           /* Process an NMI */
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extern volatile unsigned long kernel_counter;
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extern volatile unsigned long syscall_count;
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/*
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 *      General functions that each host system must provide.
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 */
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extern void smp_callin(void);
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extern void smp_boot_cpus(void);
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extern void smp_store_cpu_info(int id);         /* Store per cpu info (like the initial udelay numbers */
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extern volatile unsigned long smp_proc_in_lock[NR_CPUS]; /* for computing process time */
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extern volatile unsigned long smp_process_available;
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/*
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 *      APIC handlers: Note according to the Intel specification update
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 *      you should put reads between APIC writes.
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 *      Intel Pentium processor specification update [11AP, pg 64]
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 *              "Back to Back Assertions of HOLD May Cause Lost APIC Write Cycle"
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 */
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extern __inline void apic_write(unsigned long reg, unsigned long v)
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{
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        *((volatile unsigned long *)(apic_reg+reg))=v;
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}
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extern __inline unsigned long apic_read(unsigned long reg)
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{
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        return *((volatile unsigned long *)(apic_reg+reg));
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}
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/*
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 *      This function is needed by all SMP systems. It must _always_ be valid from the initial
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 *      startup. This may require magic on some systems (in the i86 case we dig out the boot
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 *      cpu id from the config and set up a fake apic_reg pointer so that before we activate
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 *      the apic we get the right answer). Hopefully other processors are more sensible 8)
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 */
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extern __inline int smp_processor_id(void)
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{
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        return GET_APIC_ID(apic_read(APIC_ID));
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}
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#endif /* !ASSEMBLY */
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#define NO_PROC_ID              0xFF            /* No processor magic marker */
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/*
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 *      This magic constant controls our willingness to transfer
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 *      a process across CPUs. Such a transfer incurs misses on the L1
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 *      cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
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 *      gut feeling is this will vary by board in value. For a board
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 *      with separate L2 cache it probably depends also on the RSS, and
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 *      for a board with shared L2 cache it ought to decay fast as other
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 *      processes are run.
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 */
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#define PROC_CHANGE_PENALTY     20              /* Schedule penalty */
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#define SMP_FROM_INT            1
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#define SMP_FROM_SYSCALL        2
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#endif
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#endif

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