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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [include/] [asm-m68knommu/] [m68302.h] - Blame information for rev 1765

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Line No. Rev Author Line
1 1633 jcastillo
#ifndef _m68302_h_
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#define _m68302_h_
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#ifndef REG8 /* 8-bit reg */
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#define REG8(addr)  *((volatile unsigned char * ) (addr))
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#endif
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#ifndef REG16 /* 16-bit reg */
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#define REG16(addr) *((volatile unsigned short * ) (addr))
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#endif
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#ifndef REG32 /* 32-bit reg */
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#define REG32(addr) *((volatile unsigned long * ) (addr))
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#endif
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#ifndef AREG8 /* 8-bit reg */
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#define AREG8(addr)  ((volatile unsigned char * ) (addr))
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#endif
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#ifndef AREG16 /* 16-bit reg */
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#define AREG16(addr) ((volatile unsigned short * ) (addr))
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#endif
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#ifndef AREG32 /* 32-bit reg */
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#define AREG32(addr) ((volatile unsigned short * ) (addr))
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#endif
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/* These values must be the same as in begin.s */
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#define BAR             0xF00000
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//#define BAR           0xFFF000
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#define GIMR    BAR+0x812 /* Global Interrupt Mode Reg's Memory Address */
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#define IMR             BAR+0x816 /* Interrupt Mask Reg'S Memory Address */
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#define ISR             BAR+0x818
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#define TMR1    BAR+0x840  /* Timer Mode Register 1 */
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#define TRR1    BAR+0x842  /* Timer Reference Register 1 */
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#define TCR1    BAR+0x844  /* Timer Capture Register 1 */
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#define TCN1    BAR+0x846  /* Timer Counter 1 */
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#define TER1    BAR+0x849  /* Timer Event Register 1 */
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#define TMR2    BAR+0x850  /* Timer Mode Register 2 */
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#define TRR2    BAR+0x852  /* Timer Reference Register 2 */
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#define TCR2    BAR+0x854  /* Timer Capture Register 2 */
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#define TCN2    BAR+0x856  /* Timer Counter 2 */
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#define TER2    BAR+0x859  /* Timer Event Register 2 */
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#define WRR     BAR+0x84A  /* Watchdog Reference Register */
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#define WCN     BAR+0x84C  /* Watchdog Counter */
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#define ISR_TMR1 (1 << 9)  /* TIMER1 bit in the ISR and IMR */
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#define ISR_TMR2 (1 << 6)  /* TIMER3 bit in the ISR and IMR */
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#define ISR_PB10 (1 << 14)  /* PB10 bit in the ISR and IMR */
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#define ISR_PB11 (1 << 15)  /* PB11 bit in the ISR and IMR */
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#define ISR_SCC1 (1 << 13)  /* SCC1 bit in the ISR and IMR */
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#define ISR_SCC2 (1 << 10)  /* SCC2 bit in the ISR and IMR */
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#define ISR_SCC3 (1 << 8)  /* SCC3 bit in the ISR and IMR */
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struct _68302_TMR
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{
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        unsigned short  PS:8;
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        unsigned short  CE:2;
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        unsigned short  OM:1;
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        unsigned short  ORI:1;
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        unsigned short  FRR:1;
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        unsigned short  ICLK:2;
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        unsigned short  RST:1;
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};
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struct _68302_TIMER
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{
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        struct _68302_TMR TMR;
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        unsigned short    TRR;
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        unsigned short    TCR;
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        unsigned short    TCN;
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        unsigned char     RES;
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        unsigned char     TER;
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};
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// port A 
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#define PACNT    REG16(BAR+0x81E)
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#define PADDR    REG16(BAR+0x820)
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#define PADAT    REG16(BAR+0x822)
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#define A_PADAT  AREG16(BAR+0x822)
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/* port B */
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#define PBCNT            REG16(BAR+0x824)
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#define PBDDR            REG16(BAR+0x826) 
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#define PBDAT            REG16(BAR+0x828)
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#define A_PBDAT          AREG16(BAR+0x828)
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// Common SCC
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#define SIMODE     REG16(BAR+0x8B4)
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#define SIMASK     REG16(BAR+0x8B2)
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#define SPMODE     REG16(BAR+0x8B0)
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#define SMC2Rx     REG16(BAR+0x66A)
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#define SMC1Rx     REG16(BAR+0x666)
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#define SMC2Tx     REG16(BAR+0x66C)
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#define SCC_BD_SIZE         4                                           // Each BD has 4 ushorts
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struct _68302_scc{
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        unsigned short res1;
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        unsigned short scon;                    // configuration
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        unsigned short scm;                             // mode
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        unsigned short dsr;                             // data sync 
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        unsigned char scce;             // event
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        unsigned char res2;
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        unsigned char sccm;             // mask
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        unsigned char res3;
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        unsigned char sccs;             // status
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        unsigned char res4;
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        unsigned short res5;
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};
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#define SCC1_BASE    REG16(BAR+0x880)
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#define SCC2_BASE    REG16(BAR+0x890)
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#define SCC3_BASE    REG16(BAR+0x8A0)
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#define SCM_MODE0       (1 << 0)
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#define SCM_MODE1       (1 << 1)
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#define SCM_ENT         (1 << 2)
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#define SCM_ENR         (1 << 3)
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#define SCM_DIAG0       (1 << 4)
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#define SCM_DIAG1       (1 << 5)
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#define SCCME_CTS       (1 << 7)
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#define SCCME_CD        (1 << 6)
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#define SCCME_IDL       (1 << 5)
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#define SCCME_BRK       (1 << 4)                // receive break
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#define SCCME_CCR       (1 << 3)                // control char received
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#define SCCME_BSY       (1 << 2)                // receive overrun
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#define SCCME_TX        (1 << 1)                // buffer transmitted
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#define SCCME_RX        (1 << 0)                // buffer received
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#define SCCS_CTS        (1 << 0)
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#define SCCS_CD (1 << 1)
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/*  SCC1 */
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#define SCON1            REG16(BAR+0x882)  
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#define SCM1             REG16(BAR+0x884)
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#define SCCE1           REG8(BAR+0x888)
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#define SCCM1           REG8(BAR+0x88A)
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#define SCCS1           REG8(BAR+0x88C)
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#define SCC1_BD_BASE    REG16(BAR+0x400)
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#define SCC1_TXBD0_1W    REG16(BAR+0x440)  
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#define SCC1_TXBD0_2W    REG16(BAR+0x442)
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#define SCC1_TXBD0_1L    REG32(BAR+0x444)
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#define SCC1_RXBD0_1W    REG16(BAR+0x400) 
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#define SCC1_RXBD0_2W    REG16(BAR+0x402)
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#define SCC1_RXBD0_1L    REG32(BAR+0x404)
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#define SCC1_MAX_IDL     REG16(BAR+0x49C)
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#define SCC1_BRKCR       REG16(BAR+0x4A0)
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#define SCC1_PAREC       REG16(BAR+0x4A2)
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#define SCC1_FRMEC       REG16(BAR+0x4A4)
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#define SCC1_NOSEC       REG16(BAR+0x4A6)
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#define SCC1_BRKEC       REG16(BAR+0x4A8) 
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#define SCC1_MRBLR       REG16(BAR+0x482)
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#define SCC1_RFCR        REG16(BAR+0x480)
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#define SCC1_CARACT              REG16(BAR+0x4B0)
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#define SCC1_UADDR1      REG16(BAR+0x4aa)
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#define SCC1_UADDR2      REG16(BAR+0x4ac)
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/*  SCC2 */
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#define SCON2                    REG16(BAR+0x892) 
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#define SCM2                     REG16(BAR+0x894)
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#define SCCE2                   REG8(BAR+0x898)
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#define SCCM2                   REG8(BAR+0x89A)
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#define SCCS2                   REG8(BAR+0x89C)
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#define SCC2_BD_BASE    REG16(BAR+0x500)
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#define SCC2_TXBD0_1W    REG16(BAR+0x540)  
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#define SCC2_TXBD0_2W    REG16(BAR+0x542)
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#define SCC2_TXBD0_1L    REG32(BAR+0x544)
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#define SCC2_RXBD0_1W    REG16(BAR+0x500) 
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#define SCC2_RXBD0_2W    REG16(BAR+0x502)
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#define SCC2_RXBD0_1L    REG32(BAR+0x504)
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#define SCC2_MAX_IDL     REG16(BAR+0x59C)
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#define SCC2_BRKCR       REG16(BAR+0x5A0)
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#define SCC2_PAREC       REG16(BAR+0x5A2)
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#define SCC2_FRMEC       REG16(BAR+0x5A4)
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#define SCC2_NOSEC       REG16(BAR+0x5A6)
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#define SCC2_BRKEC       REG16(BAR+0x5A8) 
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#define SCC2_MRBLR       REG16(BAR+0x582)
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#define SCC2_RFCR        REG16(BAR+0x580)
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#define SCC2_CARACT              REG16(BAR+0x5B0)
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#define SCC2_UADDR1      REG16(BAR+0x5aa)
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#define SCC2_UADDR2      REG16(BAR+0x5ac)
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/*  SCC3 */
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#define SCON3                    REG16(BAR+0x8A2) 
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#define SCM3                     REG16(BAR+0x8A4)
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#define SCCE3                   REG8(BAR+0x8A8)
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#define SCCM3                   REG8(BAR+0x8AA)
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#define SCCS3                   REG8(BAR+0x8AC)
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#define SCC3_BD_BASE    REG16(BAR+0x600)
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#define SCC3_TXBD0_1W    REG16(BAR+0x640)  
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#define SCC3_TXBD0_2W    REG16(BAR+0x642)
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#define SCC3_TXBD0_1L    REG32(BAR+0x644)
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#define SCC3_RXBD0_1W    REG16(BAR+0x600) 
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#define SCC3_RXBD0_2W    REG16(BAR+0x602)
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#define SCC3_RXBD0_1L    REG32(BAR+0x604)
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#define SCC3_MAX_IDL     REG16(BAR+0x69C)
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#define SCC3_BRKCR       REG16(BAR+0x6A0)
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#define SCC3_PAREC       REG16(BAR+0x6A2)
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#define SCC3_FRMEC       REG16(BAR+0x6A4)
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#define SCC3_NOSEC       REG16(BAR+0x6A6)
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#define SCC3_BRKEC       REG16(BAR+0x6A8) 
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#define SCC3_MRBLR       REG16(BAR+0x682)
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#define SCC3_RFCR        REG16(BAR+0x680)
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#define SCC3_CARACT              REG16(BAR+0x6B0)
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#define SCC3_UADDR1      REG16(BAR+0x6aa)
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#define SCC3_UADDR2      REG16(BAR+0x6ac)
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#endif

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