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/****************************************************************************/
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/*
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* mcfdma.h -- Coldfire internal DMA support defines.
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*
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* (C) Copyright 1999, Rob Scott (rscott@mtrob.ml.org)
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*/
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/****************************************************************************/
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#ifndef mcfdma_h
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#define mcfdma_h
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/****************************************************************************/
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#include <linux/config.h>
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/*
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* Get address specific defines for this Coldfire member.
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*/
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#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
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#define MCFDMA_BASE0 0x200 /* Base address of DMA 0 */
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#define MCFDMA_BASE1 0x240 /* Base address of DMA 1 */
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#elif defined(CONFIG_M5307)
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#define MCFDMA_BASE0 0x300 /* Base address of DMA 0 */
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#define MCFDMA_BASE1 0x340 /* Base address of DMA 1 */
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#define MCFDMA_BASE2 0x380 /* Base address of DMA 2 */
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#define MCFDMA_BASE3 0x3C0 /* Base address of DMA 3 */
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#endif
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/*
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* Define the DMA register set addresses.
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* Note: these are longword registers, use unsigned long as data type
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*/
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#define MCFDMA_SAR 0x00 /* DMA source address (r/w) */
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#define MCFDMA_DAR 0x01 /* DMA destination adr (r/w) */
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/* these are word registers, use unsigned short data type */
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#define MCFDMA_DCR 0x04 /* DMA control reg (r/w) */
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#define MCFDMA_BCR 0x06 /* DMA byte count reg (r/w) */
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/* these are byte registers, use unsiged char data type */
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#define MCFDMA_DSR 0x10 /* DMA status reg (r/w) */
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#define MCFDMA_DIVR 0x14 /* DMA interrupt vec (r/w) */
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/*
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* Bit definitions for the DMA Control Register (DCR).
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*/
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#define MCFDMA_DCR_INT 0x8000 /* Enable completion irq */
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#define MCFDMA_DCR_EEXT 0x4000 /* Enable external DMA req */
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#define MCFDMA_DCR_CS 0x2000 /* Enable cycle steal */
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#define MCFDMA_DCR_AA 0x1000 /* Enable auto alignment */
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#define MCFDMA_DCR_BWC_MASK 0x0E00 /* Bandwidth ctl mask */
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#define MCFDMA_DCR_BWC_512 0x0200 /* Bandwidth: 512 Bytes */
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#define MCFDMA_DCR_BWC_1024 0x0400 /* Bandwidth: 1024 Bytes */
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#define MCFDMA_DCR_BWC_2048 0x0600 /* Bandwidth: 2048 Bytes */
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#define MCFDMA_DCR_BWC_4096 0x0800 /* Bandwidth: 4096 Bytes */
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#define MCFDMA_DCR_BWC_8192 0x0a00 /* Bandwidth: 8192 Bytes */
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#define MCFDMA_DCR_BWC_16384 0x0c00 /* Bandwidth: 16384 Bytes */
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#define MCFDMA_DCR_BWC_32768 0x0e00 /* Bandwidth: 32768 Bytes */
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#define MCFDMA_DCR_SAA 0x0100 /* Single Address Access */
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#define MCFDMA_DCR_S_RW 0x0080 /* SAA read/write value */
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#define MCFDMA_DCR_SINC 0x0040 /* Source addr inc enable */
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#define MCFDMA_DCR_SSIZE_MASK 0x0030 /* Src xfer size */
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#define MCFDMA_DCR_SSIZE_LONG 0x0000 /* Src xfer size, 00 = longw */
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#define MCFDMA_DCR_SSIZE_BYTE 0x0010 /* Src xfer size, 01 = byte */
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#define MCFDMA_DCR_SSIZE_WORD 0x0020 /* Src xfer size, 10 = word */
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#define MCFDMA_DCR_SSIZE_LINE 0x0030 /* Src xfer size, 11 = line */
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#define MCFDMA_DCR_DINC 0x0008 /* Dest addr inc enable */
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#define MCFDMA_DCR_DSIZE_MASK 0x0006 /* Dest xfer size */
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#define MCFDMA_DCR_DSIZE_LONG 0x0000 /* Dest xfer size, 00 = long */
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#define MCFDMA_DCR_DSIZE_BYTE 0x0002 /* Dest xfer size, 01 = byte */
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#define MCFDMA_DCR_DSIZE_WORD 0x0004 /* Dest xfer size, 10 = word */
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#define MCFDMA_DCR_DSIZE_LINE 0x0006 /* Dest xfer size, 11 = line */
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#define MCFDMA_DCR_START 0x0001 /* Start transfer */
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/*
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* Bit definitions for the DMA Status Register (DSR).
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*/
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#define MCFDMA_DSR_CE 0x40 /* Config error */
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#define MCFDMA_DSR_BES 0x20 /* Bus Error on source */
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#define MCFDMA_DSR_BED 0x10 /* Bus Error on dest */
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#define MCFDMA_DSR_REQ 0x04 /* Requests remaining */
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#define MCFDMA_DSR_BSY 0x02 /* Busy */
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#define MCFDMA_DSR_DONE 0x01 /* DMA transfer complete */
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/****************************************************************************/
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#endif /* mcfdma_h */
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