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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [include/] [asm-m68knommu/] [mcfuart.h] - Blame information for rev 1777

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1 1633 jcastillo 
/****************************************************************************/
2 
 
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/*
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 *      mcfuart.h -- ColdFire internal UART support defines.
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 *
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 *      (C) Copyright 1999, Greg Ungerer (gerg@moreton.com.au)
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 */
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/****************************************************************************/
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#ifndef mcfuart_h
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#define mcfuart_h
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/****************************************************************************/
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#include <linux/config.h>
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/*
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 *      Define the base address of the UARTS within the MBAR address
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 *      space.
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 */
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#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5204)
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#if defined(CONFIG_NETtel)
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#define MCFUART_BASE1           0x180           /* Base address of UART1 */
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#define MCFUART_BASE2           0x140           /* Base address of UART2 */
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#else
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#define MCFUART_BASE1           0x140           /* Base address of UART1 */
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#define MCFUART_BASE2           0x180           /* Base address of UART2 */
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#endif
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#elif defined(CONFIG_M5307)
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#if defined(CONFIG_NETtel) || defined(CONFIG_MATtel)
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#define MCFUART_BASE1           0x200           /* Base address of UART1 */
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#define MCFUART_BASE2           0x1c0           /* Base address of UART2 */
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#else
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#define MCFUART_BASE1           0x1c0           /* Base address of UART1 */
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#define MCFUART_BASE2           0x200           /* Base address of UART2 */
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#endif
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#endif
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/*
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 *      Define the ColdFire UART register set addresses.
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 */
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#define MCFUART_UMR             0x00            /* Mode register (r/w) */
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#define MCFUART_USR             0x04            /* Status register (r) */
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#define MCFUART_UCSR            0x04            /* Clock Select (w) */
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#define MCFUART_UCR             0x08            /* Command register (w) */
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#define MCFUART_URB             0x0c            /* Receiver Buffer (r) */
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#define MCFUART_UTB             0x0c            /* Transmit Buffer (w) */
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#define MCFUART_UIPCR           0x10            /* Input Port Change (r) */
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#define MCFUART_UACR            0x10            /* Auxiliary Control (w) */
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#define MCFUART_UISR            0x14            /* Interrup Status (r) */
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#define MCFUART_UIMR            0x14            /* Interrupt Mask (w) */
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#define MCFUART_UBG1            0x18            /* Baud Rate MSB (r/w) */
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#define MCFUART_UBG2            0x1c            /* Baud Rate LSB (r/w) */
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#define MCFUART_UIVR            0x30            /* Interrupt Vector (r/w) */
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#define MCFUART_UIPR            0x34            /* Input Port (r) */
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#define MCFUART_UOP1            0x38            /* Output Port Bit Set (w) */
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#define MCFUART_UOP0            0x3c            /* Output Port Bit Reset (w) */
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/*
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 *      Define bit flags in Mode Register 1 (MR1).
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 */
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#define MCFUART_MR1_RXRTS       0x80            /* Auto RTS flow control */
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#define MCFUART_MR1_RXIRQFULL   0x40            /* RX IRQ type FULL */
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#define MCFUART_MR1_RXIRQRDY    0x00            /* RX IRQ type RDY */
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#define MCFUART_MR1_RXERRBLOCK  0x20            /* RX block error mode */
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#define MCFUART_MR1_RXERRCHAR   0x00            /* RX char error mode */
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#define MCFUART_MR1_PARITYNONE  0x10            /* No parity */
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#define MCFUART_MR1_PARITYEVEN  0x00            /* Even parity */
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#define MCFUART_MR1_PARITYODD   0x04            /* Odd parity */
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#define MCFUART_MR1_PARITYSPACE 0x08            /* Space parity */
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#define MCFUART_MR1_PARITYMARK  0x06            /* Mark parity */
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#define MCFUART_MR1_CS5         0x00            /* 5 bits per char */
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#define MCFUART_MR1_CS6         0x01            /* 6 bits per char */
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#define MCFUART_MR1_CS7         0x02            /* 7 bits per char */
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#define MCFUART_MR1_CS8         0x03            /* 8 bits per char */
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/*
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 *      Define bit flags in Mode Register 2 (MR2).
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 */
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#define MCFUART_MR2_LOOPBACK    0x80            /* Loopback mode */
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#define MCFUART_MR2_REMOTELOOP  0xc0            /* Remote loopback mode */
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#define MCFUART_MR2_AUTOECHO    0x40            /* Automatic echo */
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#define MCFUART_MR2_TXRTS       0x20            /* Assert RTS on TX */
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#define MCFUART_MR2_TXCTS       0x10            /* Auto CTS flow control */
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#define MCFUART_MR2_STOP1       0x07            /* 1 stop bit */
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#define MCFUART_MR2_STOP15      0x08            /* 1.5 stop bits */
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#define MCFUART_MR2_STOP2       0x0f            /* 2 stop bits */
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/*
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 *      Define bit flags in Status Register (USR).
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 */
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#define MCFUART_USR_RXBREAK     0x80            /* Received BREAK */
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#define MCFUART_USR_RXFRAMING   0x40            /* Received framing error */
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#define MCFUART_USR_RXPARITY    0x20            /* Received parity error */
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#define MCFUART_USR_RXOVERRUN   0x10            /* Received overrun error */
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#define MCFUART_USR_TXEMPTY     0x08            /* Transmitter empty */
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#define MCFUART_USR_TXREADY     0x04            /* Transmitter ready */
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#define MCFUART_USR_RXFULL      0x02            /* Receiver full */
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#define MCFUART_USR_RXREADY     0x01            /* Receiver ready */
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#define MCFUART_USR_RXERR       (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
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                                MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
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/*
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 *      Define bit flags in Clock Select Register (UCSR).
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 */
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#define MCFUART_UCSR_RXCLKTIMER 0xd0            /* RX clock is timer */
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#define MCFUART_UCSR_RXCLKEXT16 0xe0            /* RX clock is external x16 */
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#define MCFUART_UCSR_RXCLKEXT1  0xf0            /* RX clock is external x1 */
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#define MCFUART_UCSR_TXCLKTIMER 0x0d            /* TX clock is timer */
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#define MCFUART_UCSR_TXCLKEXT16 0x0e            /* TX clock is external x16 */
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#define MCFUART_UCSR_TXCLKEXT1  0x0f            /* TX clock is external x1 */
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/*
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 *      Define bit flags in Command Register (UCR).
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 */
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#define MCFUART_UCR_CMDNULL             0x00    /* No command */
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#define MCFUART_UCR_CMDRESETMRPTR       0x10    /* Reset MR pointer */
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#define MCFUART_UCR_CMDRESETRX          0x20    /* Reset receiver */
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#define MCFUART_UCR_CMDRESETTX          0x30    /* Reset transmitter */
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#define MCFUART_UCR_CMDRESETERR         0x40    /* Reset error status */
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#define MCFUART_UCR_CMDRESETBREAK       0x50    /* Reset BREAK change */
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#define MCFUART_UCR_CMDBREAKSTART       0x60    /* Start BREAK */
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#define MCFUART_UCR_CMDBREAKSTOP        0x70    /* Stop BREAK */
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#define MCFUART_UCR_TXNULL      0x00            /* No TX command */
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#define MCFUART_UCR_TXENABLE    0x04            /* Enable TX */
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#define MCFUART_UCR_TXDISABLE   0x08            /* Disable TX */
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#define MCFUART_UCR_RXNULL      0x00            /* No RX command */
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#define MCFUART_UCR_RXENABLE    0x01            /* Enable RX */
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#define MCFUART_UCR_RXDISABLE   0x02            /* Disable RX */
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/*
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 *      Define bit flags in Input Port Change Register (UIPCR).
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 */
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#define MCFUART_UIPCR_CTSCOS    0x10            /* CTS change of state */
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#define MCFUART_UIPCR_CTS       0x01            /* CTS value */
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/*
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 *      Define bit flags in Input Port Register (UIP).
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 */
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#define MCFUART_UIPR_CTS        0x01            /* CTS value */
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/*
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 *      Define bit flags in Output Port Registers (UOP).
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 *      Clear bit by writing to UOP0, set by writing to UOP1.
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 */
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#define MCFUART_UOP_RTS         0x01            /* RTS set or clear */
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/*
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 *      Define bit flags in the Auxiliary Control Register (UACR).
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 */
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#define MCFUART_UACR_IEC        0x01            /* Input enable control */
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/*
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 *      Define bit flags in Interrupt Status Register (UISR).
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 *      These same bits are used for the Interrupt Mask Register (UIMR).
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 */
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#define MCFUART_UIR_COS         0x80            /* Change of state (CTS) */
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#define MCFUART_UIR_DELTABREAK  0x04            /* Break start or stop */
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#define MCFUART_UIR_RXREADY     0x02            /* Receiver ready */
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#define MCFUART_UIR_TXREADY     0x01            /* Transmitter ready */
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/****************************************************************************/
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#endif  /* mcfuart_h */

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