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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [include/] [asm-mips/] [mipsregs.h] - Blame information for rev 1765

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1 1633 jcastillo 
/*
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 * include/asm-mips/mipsregs.h
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 *
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 * This file is subject to the terms and conditions of the GNU General Public
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 * License.  See the file "COPYING" in the main directory of this archive
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 * for more details.
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 *
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 * Copyright (C) 1994, 1995 by Ralf Baechle
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 */
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#ifndef __ASM_MIPS_MIPSREGS_H
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#define __ASM_MIPS_MIPSREGS_H
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/*
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 * The following macros are especially useful for __asm__
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 * inline assembler.
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 */
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#ifndef __STR
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#define __STR(x) #x
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#endif
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#ifndef STR
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#define STR(x) __STR(x)
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#endif
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/*
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 * On the R2000/3000 load instructions are not interlocked -
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 * we therefore sometimes need to fill load delay slots with a nop
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 * which would be useless for ISA >= 2.
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 */
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#if !defined (__R4000__)
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#define FILL_LDS nop
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#else
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#define FILL_LDS
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#endif
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/*
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 * Coprocessor 0 register names
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 */
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#define CP0_INDEX $0
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#define CP0_RANDOM $1
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#define CP0_ENTRYLO0 $2
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#define CP0_ENTRYLO1 $3
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#define CP0_CONTEXT $4
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#define CP0_PAGEMASK $5
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#define CP0_WIRED $6
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#define CP0_BADVADDR $8
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#define CP0_COUNT $9
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#define CP0_ENTRYHI $10
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#define CP0_COMPARE $11
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#define CP0_STATUS $12
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#define CP0_CAUSE $13
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#define CP0_EPC $14
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#define CP0_PRID $15
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#define CP0_CONFIG $16
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#define CP0_LLADDR $17
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#define CP0_WATCHLO $18
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#define CP0_WATCHHI $19
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#define CP0_XCONTEXT $20
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#define CP0_FRAMEMASK $21
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#define CP0_DIAGNOSTIC $22
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#define CP0_PERFORMANCE $25
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#define CP0_ECC $26
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#define CP0_CACHEERR $27
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#define CP0_TAGLO $28
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#define CP0_TAGHI $29
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#define CP0_ERROREPC $30
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/*
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 * Coprocessor 1 (FPU) register names
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 */
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#define CP1_REVISION   $0
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#define CP1_STATUS     $31
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/*
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 * Values for PageMask register
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 */
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#define PM_4K   0x00000000
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#define PM_16K  0x00006000
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#define PM_64K  0x0001e000
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#define PM_256K 0x0007e000
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#define PM_1M   0x001fe000
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#define PM_4M   0x007fe000
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#define PM_16M  0x01ffe000
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/*
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 * Values used for computation of new tlb entries
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 */
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#define PL_4K   12
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#define PL_16K  14
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#define PL_64K  16
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#define PL_256K 18
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#define PL_1M   20
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#define PL_4M   22
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#define PL_16M  24
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/*
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 * Macros to access the system control coprocessor
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 */
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#define read_32bit_cp0_register(source)                         \
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({ int __res;                                                   \
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        __asm__ __volatile__(                                   \
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        "mfc0\t%0,"STR(source)                                  \
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        : "=r" (__res));                                        \
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        __res;})
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#define read_64bit_cp0_register(source)                         \
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({ int __res;                                                   \
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        __asm__ __volatile__(                                   \
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        ".set\tmips3\n\t"                                       \
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        "dmfc0\t%0,"STR(source)"\n\t"                           \
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        ".set\tmips0"                                           \
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        : "=r" (__res));                                        \
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        __res;})
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#define write_32bit_cp0_register(register,value)                \
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        __asm__ __volatile__(                                   \
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        "mtc0\t%0,"STR(register)                                \
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        : : "r" (value));
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#define write_64bit_cp0_register(register,value)                \
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        __asm__ __volatile__(                                   \
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        ".set\tmips3\n\t"                                       \
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        "dmtc0\t%0,"STR(register)"\n\t"                         \
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        ".set\tmips0"                                           \
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        : : "r" (value))
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/*
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 * R4x00 interrupt enable / cause bits
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 */
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#define IE_SW0          (1<< 8)
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#define IE_SW1          (1<< 9)
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#define IE_IRQ0         (1<<10)
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#define IE_IRQ1         (1<<11)
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#define IE_IRQ2         (1<<12)
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#define IE_IRQ3         (1<<13)
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#define IE_IRQ4         (1<<14)
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#define IE_IRQ5         (1<<15)
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/*
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 * R4x00 interrupt cause bits
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 */
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#define C_SW0           (1<< 8)
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#define C_SW1           (1<< 9)
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#define C_IRQ0          (1<<10)
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#define C_IRQ1          (1<<11)
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#define C_IRQ2          (1<<12)
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#define C_IRQ3          (1<<13)
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#define C_IRQ4          (1<<14)
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#define C_IRQ5          (1<<15)
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#ifndef __LANGUAGE_ASSEMBLY__
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/*
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 * Manipulate the status register.
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 * Mostly used to access the interrupt bits.
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 */
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#define BUILD_SET_CP0(name,register)                            \
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extern __inline__ unsigned int                                  \
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set_cp0_##name(unsigned int change, unsigned int new)           \
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{                                                               \
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        unsigned int res;                                       \
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                                                                \
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        res = read_32bit_cp0_register(register);                \
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        res &= ~change;                                         \
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        res |= (new & change);                                  \
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        if(change)                                              \
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                write_32bit_cp0_register(register, res);        \
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                                                                \
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        return res;                                             \
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}
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BUILD_SET_CP0(status,CP0_STATUS)
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BUILD_SET_CP0(cause,CP0_CAUSE)
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#endif /* defined (__LANGUAGE_ASSEMBLY__) */
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/*
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 * Inline code for use of the ll and sc instructions
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 *
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 * FIXME: This instruction is only available on MIPS ISA >=3.
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 * Since these operations are only being used for atomic operations
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 * the easiest workaround for the R[23]00 is to disable interrupts.
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 */
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#define load_linked(addr)                                       \
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({                                                              \
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        unsigned int __res;                                     \
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                                                                \
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        __asm__ __volatile__(                                   \
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        "ll\t%0,(%1)"                                           \
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        : "=r" (__res)                                          \
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        : "r" ((unsigned int) (addr)));                         \
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                                                                \
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        __res;                                                  \
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})
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195 
#define store_conditional(addr,value)                           \
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({                                                              \
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        int     __res;                                          \
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                                                                \
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        __asm__ __volatile__(                                   \
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        "sc\t%0,(%2)"                                           \
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        : "=r" (__res)                                          \
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        : "0" (value), "r" (addr));                             \
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                                                                \
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        __res;                                                  \
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})
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/*
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 * Bitfields in the cp0 status register
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 *
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 * Refer to the MIPS R4xx0 manuals, chapter 5 for explanation.
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 * FIXME: This doesn't cover all R4xx0 processors.
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 */
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#define ST0_IE                  (1   <<  0)
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#define ST0_EXL                 (1   <<  1)
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#define ST0_ERL                 (1   <<  2)
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#define ST0_KSU                 (3   <<  3)
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#  define KSU_USER              (2  <<   3)
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#  define KSU_SUPERVISOR        (1  <<   3)
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#  define KSU_KERNEL            (0  <<   3)
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#define ST0_UX                  (1   <<  5)
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#define ST0_SX                  (1   <<  6)
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#define ST0_KX                  (1   <<  7)
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#define ST0_IM                  (255 <<  8)
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#define ST0_DE                  (1   << 16)
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#define ST0_CE                  (1   << 17)
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#define ST0_CH                  (1   << 18)
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#define ST0_SR                  (1   << 20)
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#define ST0_BEV                 (1   << 22)
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#define ST0_RE                  (1   << 25)
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#define ST0_FR                  (1   << 26)
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#define ST0_CU                  (15  << 28)
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#define ST0_CU0                 (1   << 28)
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#define ST0_CU1                 (1   << 29)
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#define ST0_CU2                 (1   << 30)
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#define ST0_CU3                 (1   << 31)
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#define ST0_XX                  (1   << 31)     /* R8000/R10000 naming */
237 
 
238 
/*
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 * Bitfields and bit numbers in the coprocessor 0 cause register.
240 
 *
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 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
242 
 */
243 
#define  CAUSEB_EXCCODE         2
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#define  CAUSEF_EXCCODE         (31  <<  2)
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#define  CAUSEB_IP              8
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#define  CAUSEF_IP              (255 <<  8)
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#define  CAUSEB_IP0             8
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#define  CAUSEF_IP0             (1   <<  8)
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#define  CAUSEB_IP1             9
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#define  CAUSEF_IP1             (1   <<  9)
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#define  CAUSEB_IP2             10
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#define  CAUSEF_IP2             (1   << 10)
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#define  CAUSEB_IP3             11
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#define  CAUSEF_IP3             (1   << 11)
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#define  CAUSEB_IP4             12
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#define  CAUSEF_IP4             (1   << 12)
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#define  CAUSEB_IP5             13
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#define  CAUSEF_IP5             (1   << 13)
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#define  CAUSEB_IP6             14
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#define  CAUSEF_IP6             (1   << 14)
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#define  CAUSEB_IP7             15
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#define  CAUSEF_IP7             (1   << 15)
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#define  CAUSEB_CE              28
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#define  CAUSEF_CE              (3   << 28)
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#define  CAUSEB_BD              31
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#define  CAUSEF_BD              (1   << 31)
267 
 
268 
#endif /* __ASM_MIPS_MIPSREGS_H */

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