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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [include/] [asm-ppc/] [dma.h] - Blame information for rev 1765

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1 1633 jcastillo
/* $Id: dma.h,v 1.1 2005-12-20 11:32:05 jcastillo Exp $
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 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
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 * Written by Hennus Bergman, 1992.
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 * High DMA channel support & info by Hannu Savolainen
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 * and John Boyd, Nov. 1992.
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 */
7
 
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/*
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 * Note: Adapted for PowerPC by Gary Thomas
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 *
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 * There may be some comments or restrictions made here which are
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 * not valid for the PowerPC (PreP) platform.  Take what you read
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 * with a grain of salt.
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 */
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#ifndef _ASM_DMA_H
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#define _ASM_DMA_H
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#include <asm/io.h>             /* need byte IO */
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#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
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#define dma_outb        outb_p
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#else
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#define dma_outb        outb
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#endif
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#define dma_inb         inb
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/*
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 * NOTES about DMA transfers:
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 *
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 *  controller 1: channels 0-3, byte operations, ports 00-1F
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 *  controller 2: channels 4-7, word operations, ports C0-DF
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 *
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 *  - ALL registers are 8 bits only, regardless of transfer size
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 *  - channel 4 is not used - cascades 1 into 2.
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 *  - channels 0-3 are byte - addresses/counts are for physical bytes
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 *  - channels 5-7 are word - addresses/counts are for physical words
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 *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
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 *  - transfer count loaded to registers is 1 less than actual count
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 *  - controller 2 offsets are all even (2x offsets for controller 1)
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 *  - page registers for 5-7 don't use data bit 0, represent 128K pages
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 *  - page registers for 0-3 use bit 0, represent 64K pages
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 *
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 * DMA transfers are limited to the lower 16MB of _physical_ memory.
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 * Note that addresses loaded into registers must be _physical_ addresses,
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 * not logical addresses (which may differ if paging is active).
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 *
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 *  Address mapping for channels 0-3:
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 *
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 *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
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 *    |  ...  |   |  ... |   |  ... |
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 *    |  ...  |   |  ... |   |  ... |
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 *    |  ...  |   |  ... |   |  ... |
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 *   P7  ...  P0  A7 ... A0  A7 ... A0
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 * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
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 *
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 *  Address mapping for channels 5-7:
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 *
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 *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
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 *    |  ...  |   \   \   ... \  \  \  ... \  \
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 *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
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 *    |  ...  |     \   \   ... \  \  \  ... \
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 *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
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 * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
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 *
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 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
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 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
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 * the hardware level, so odd-byte transfers aren't possible).
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 *
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 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
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 * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
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 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
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 *
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 */
78
 
79
#define MAX_DMA_CHANNELS        8
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/* The maximum address that we can perform a DMA transfer to on this platform */
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/* Doesn't really apply... */
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#define MAX_DMA_ADDRESS      0xFFFFFFFF
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/* 8237 DMA controllers */
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#define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
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#define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
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/* DMA controller registers */
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#define DMA1_CMD_REG            0x08    /* command register (w) */
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#define DMA1_STAT_REG           0x08    /* status register (r) */
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#define DMA1_REQ_REG            0x09    /* request register (w) */
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#define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
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#define DMA1_MODE_REG           0x0B    /* mode register (w) */
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#define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
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#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
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#define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
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#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
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#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
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#define DMA2_CMD_REG            0xD0    /* command register (w) */
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#define DMA2_STAT_REG           0xD0    /* status register (r) */
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#define DMA2_REQ_REG            0xD2    /* request register (w) */
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#define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
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#define DMA2_MODE_REG           0xD6    /* mode register (w) */
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#define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
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#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
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#define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
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#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
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#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
111
 
112
#define DMA_ADDR_0              0x00    /* DMA address registers */
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#define DMA_ADDR_1              0x02
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#define DMA_ADDR_2              0x04
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#define DMA_ADDR_3              0x06
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#define DMA_ADDR_4              0xC0
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#define DMA_ADDR_5              0xC4
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#define DMA_ADDR_6              0xC8
119
#define DMA_ADDR_7              0xCC
120
 
121
#define DMA_CNT_0               0x01    /* DMA count registers */
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#define DMA_CNT_1               0x03
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#define DMA_CNT_2               0x05
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#define DMA_CNT_3               0x07
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#define DMA_CNT_4               0xC2
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#define DMA_CNT_5               0xC6
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#define DMA_CNT_6               0xCA
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#define DMA_CNT_7               0xCE
129
 
130
#define DMA_LO_PAGE_0              0x87    /* DMA page registers */
131
#define DMA_LO_PAGE_1              0x83
132
#define DMA_LO_PAGE_2              0x81
133
#define DMA_LO_PAGE_3              0x82
134
#define DMA_LO_PAGE_5              0x8B
135
#define DMA_LO_PAGE_6              0x89
136
#define DMA_LO_PAGE_7              0x8A
137
 
138
#define DMA_HI_PAGE_0              0x487    /* DMA page registers */
139
#define DMA_HI_PAGE_1              0x483
140
#define DMA_HI_PAGE_2              0x481
141
#define DMA_HI_PAGE_3              0x482
142
#define DMA_HI_PAGE_5              0x48B
143
#define DMA_HI_PAGE_6              0x489
144
#define DMA_HI_PAGE_7              0x48A
145
 
146
#define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
147
#define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
148
#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
149
 
150
/* enable/disable a specific DMA channel */
151
static __inline__ void enable_dma(unsigned int dmanr)
152
{
153
        if (dmanr != 4)
154
        {
155
                dma_outb(0, DMA2_MASK_REG);  /* This may not be enabled */
156
                dma_outb(0, DMA2_CMD_REG);  /* Enable group */
157
        }
158
        if (dmanr<=3)
159
        {
160
                dma_outb(dmanr,  DMA1_MASK_REG);
161
                dma_outb(0, DMA1_CMD_REG);  /* Enable group */
162
        } else
163
        {
164
                dma_outb(dmanr & 3,  DMA2_MASK_REG);
165
        }
166
}
167
 
168
static __inline__ void disable_dma(unsigned int dmanr)
169
{
170
        if (dmanr<=3)
171
                dma_outb(dmanr | 4,  DMA1_MASK_REG);
172
        else
173
                dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
174
}
175
 
176
/* Clear the 'DMA Pointer Flip Flop'.
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 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
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 * Use this once to initialize the FF to a known state.
179
 * After that, keep track of it. :-)
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 * --- In order to do that, the DMA routines below should ---
181
 * --- only be used while interrupts are disabled! ---
182
 */
183
static __inline__ void clear_dma_ff(unsigned int dmanr)
184
{
185
        if (dmanr<=3)
186
                dma_outb(0,  DMA1_CLEAR_FF_REG);
187
        else
188
                dma_outb(0,  DMA2_CLEAR_FF_REG);
189
}
190
 
191
/* set mode (above) for a specific DMA channel */
192
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
193
{
194
        if (dmanr<=3)
195
                dma_outb(mode | dmanr,  DMA1_MODE_REG);
196
        else
197
                dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
198
}
199
 
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/* Set only the page register bits of the transfer address.
201
 * This is used for successive transfers when we know the contents of
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 * the lower 16 bits of the DMA current address register, but a 64k boundary
203
 * may have been crossed.
204
 */
205
static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
206
{
207
        switch(dmanr) {
208
                case 0:
209
                        dma_outb(pagenr, DMA_LO_PAGE_0);
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                        break;
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                case 1:
212
                        dma_outb(pagenr, DMA_LO_PAGE_1);
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                        break;
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                case 2:
215
                        dma_outb(pagenr, DMA_LO_PAGE_2);
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                        dma_outb(pagenr>>8, DMA_HI_PAGE_2);
217
                        break;
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                case 3:
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                        dma_outb(pagenr, DMA_LO_PAGE_3);
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                        break;
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                case 5:
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                        dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
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                        break;
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                case 6:
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                        dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
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                        break;
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                case 7:
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                        dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
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                        break;
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        }
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}
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/* Set transfer address & page bits for specific DMA channel.
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 * Assumes dma flipflop is clear.
236
 */
237
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
238
{
239
        if (dmanr <= 3)  {
240
            dma_outb( phys & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
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            dma_outb( (phys>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
242
        }  else  {
243
            dma_outb( (phys>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
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            dma_outb( (phys>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
245
        }
246
        set_dma_page(dmanr, phys>>16);
247
}
248
 
249
 
250
/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
251
 * a specific DMA channel.
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 * You must ensure the parameters are valid.
253
 * NOTE: from a manual: "the number of transfers is one more
254
 * than the initial word count"! This is taken into account.
255
 * Assumes dma flip-flop is clear.
256
 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
257
 */
258
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
259
{
260
        count--;
261
        if (dmanr <= 3)  {
262
            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
263
            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
264
        } else {
265
            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
266
            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
267
        }
268
}
269
 
270
 
271
/* Get DMA residue count. After a DMA transfer, this
272
 * should return zero. Reading this while a DMA transfer is
273
 * still in progress will return unpredictable results.
274
 * If called before the channel has been used, it may return 1.
275
 * Otherwise, it returns the number of _bytes_ left to transfer.
276
 *
277
 * Assumes DMA flip-flop is clear.
278
 */
279
static __inline__ int get_dma_residue(unsigned int dmanr)
280
{
281
        unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
282
                                         : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
283
 
284
        /* using short to get 16-bit wrap around */
285
        unsigned short count;
286
 
287
        count = 1 + dma_inb(io_port);
288
        count += dma_inb(io_port) << 8;
289
 
290
        return (dmanr<=3)? count : (count<<1);
291
}
292
 
293
 
294
/* These are in kernel/dma.c: */
295
/*extern int request_dma(unsigned int dmanr, char * device_id);*/       /* reserve a DMA channel */
296
extern void free_dma(unsigned int dmanr);       /* release it again */
297
 
298
 
299
#endif /* _ASM_DMA_H */

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