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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [include/] [asm-ppc/] [mmu.h] - Blame information for rev 1765

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/*
 * PowerPC memory management structures
 */
 
#ifndef _PPC_MMU_H_
#define _PPC_MMU_H_
 
/* Hardware Page Table Entry */
 
typedef struct _PTE
   {
      unsigned long v:1;        /* Entry is valid */
      unsigned long vsid:24;    /* Virtual segment identifier */
      unsigned long h:1;        /* Hash algorithm indicator */
      unsigned long api:6;      /* Abbreviated page index */
      unsigned long rpn:20;     /* Real (physical) page number */
      unsigned long    :3;      /* Unused */
      unsigned long r:1;        /* Referenced */
      unsigned long c:1;        /* Changed */
      unsigned long w:1;        /* Write-thru cache mode */
      unsigned long i:1;        /* Cache inhibited */
      unsigned long m:1;        /* Memory coherence */
      unsigned long g:1;        /* Guarded */
      unsigned long    :1;      /* Unused */
      unsigned long pp:2;       /* Page protection */
   } PTE;
 
/* Values for PP (assumes Ks=0, Kp=1) */
#define PP_RWXX 0        /* Supervisor read/write, User none */
#define PP_RWRX 1       /* Supervisor read/write, User read */
#define PP_RWRW 2       /* Supervisor read/write, User read/write */
#define PP_RXRX 3       /* Supervisor read,       User read */
 
/* Segment Register */
 
typedef struct _SEGREG
   {
      unsigned long t:1;        /* Normal or I/O  type */
      unsigned long ks:1;       /* Supervisor 'key' (normally 0) */
      unsigned long kp:1;       /* User 'key' (normally 1) */
      unsigned long n:1;        /* No-execute */
      unsigned long :4;         /* Unused */
      unsigned long vsid:24;    /* Virtual Segment Identifier */
   } SEGREG;
 
/* Block Address Translation (BAT) Registers */
 
typedef struct _BATU            /* Upper part of BAT */
   {
      unsigned long bepi:15;    /* Effective page index (virtual address) */
      unsigned long :4;         /* Unused */
      unsigned long bl:11;      /* Block size mask */
      unsigned long vs:1;       /* Supervisor valid */
      unsigned long vp:1;       /* User valid */
   } BATU;
 
typedef struct _BATL            /* Lower part of BAT */
   {
      unsigned long brpn:15;    /* Real page index (physical address) */
      unsigned long :10;        /* Unused */
      unsigned long w:1;        /* Write-thru cache */
      unsigned long i:1;        /* Cache inhibit */
      unsigned long m:1;        /* Memory coherence */
      unsigned long g:1;        /* Guarded (MBZ) */
      unsigned long :1;         /* Unused */
      unsigned long pp:2;       /* Page access protections */
   } BATL;
 
typedef struct _BAT
   {
      BATU batu;                /* Upper register */
      BATL batl;                /* Lower register */
   } BAT;
 
/* Block size masks */
#define BL_128K 0x000
#define BL_256K 0x001
#define BL_512K 0x003
#define BL_1M   0x007
#define BL_2M   0x00F
#define BL_4M   0x01F
#define BL_8M   0x03F
#define BL_16M  0x07F
#define BL_32M  0x0FF
#define BL_64M  0x1FF
#define BL_128M 0x3FF
#define BL_256M 0x7FF
 
/* BAT Access Protection */
#define BPP_XX  0x00            /* No access */
#define BPP_RX  0x01            /* Read only */
#define BPP_RW  0x02            /* Read/write */
 
/*
 * Simulated two-level MMU.  This structure is used by the kernel
 * to keep track of MMU mappings and is used to update/maintain
 * the hardware HASH table which is really a cache of mappings.
 *
 * The simulated structures mimic the hardware available on other
 * platforms, notably the 80x86 and 680x0.
 */
 
typedef struct _pte
   {
        unsigned long page_num:20;
        unsigned long flags:12;         /* Page flags (with some unused bits) */
   } pte;
 
#define PD_SHIFT (10+12)                /* Page directory */
#define PD_MASK  0x02FF
#define PT_SHIFT (12)                   /* Page Table */
#define PT_MASK  0x02FF
#define PG_SHIFT (12)                   /* Page Entry */
 
 
/* MMU context */
 
typedef struct _MMU_context
   {
      SEGREG    segs[16];       /* Segment registers */
      pte       **pmap;         /* Two-level page-map structure */
   } MMU_context;
 
#if 0
BAT     ibat[4];        /* Instruction BAT images */
BAT     dbat[4];        /* Data BAT images */
PTE     *hash_table;    /* Hardware hashed page table */
int     hash_table_size;
int     hash_table_mask;
unsigned long sdr;      /* Hardware image of SDR */
#endif   
 
/* Used to set up SDR register */
#define HASH_TABLE_SIZE_64K     0x00010000
#define HASH_TABLE_SIZE_128K    0x00020000
#define HASH_TABLE_SIZE_256K    0x00040000
#define HASH_TABLE_SIZE_512K    0x00080000
#define HASH_TABLE_SIZE_1M      0x00100000
#define HASH_TABLE_SIZE_2M      0x00200000
#define HASH_TABLE_SIZE_4M      0x00400000
#define HASH_TABLE_MASK_64K     0x000   
#define HASH_TABLE_MASK_128K    0x001   
#define HASH_TABLE_MASK_256K    0x003   
#define HASH_TABLE_MASK_512K    0x007
#define HASH_TABLE_MASK_1M      0x00F   
#define HASH_TABLE_MASK_2M      0x01F   
#define HASH_TABLE_MASK_4M      0x03F   
 
#define MMU_PAGE_SIZE   4096
 
extern int MMU_hash_page(struct thread_struct *tss, unsigned long va, pte *pg);
 
#endif

Line No.	Rev	Author	Line
1	1633	jcastillo	`/*`
2			`* PowerPC memory management structures`
3			`*/`
4
5			`#ifndef _PPC_MMU_H_`
6			`#define _PPC_MMU_H_`
7
8			`/* Hardware Page Table Entry */`
9
10			`typedef struct _PTE`
11			`{`
12			`unsigned long v:1; /* Entry is valid */`
13			`unsigned long vsid:24; /* Virtual segment identifier */`
14			`unsigned long h:1; /* Hash algorithm indicator */`
15			`unsigned long api:6; /* Abbreviated page index */`
16			`unsigned long rpn:20; /* Real (physical) page number */`
17			`unsigned long :3; /* Unused */`
18			`unsigned long r:1; /* Referenced */`
19			`unsigned long c:1; /* Changed */`
20			`unsigned long w:1; /* Write-thru cache mode */`
21			`unsigned long i:1; /* Cache inhibited */`
22			`unsigned long m:1; /* Memory coherence */`
23			`unsigned long g:1; /* Guarded */`
24			`unsigned long :1; /* Unused */`
25			`unsigned long pp:2; /* Page protection */`
26			`} PTE;`
27
28			`/* Values for PP (assumes Ks=0, Kp=1) */`
29			`#define PP_RWXX 0 /* Supervisor read/write, User none */`
30			`#define PP_RWRX 1 /* Supervisor read/write, User read */`
31			`#define PP_RWRW 2 /* Supervisor read/write, User read/write */`
32			`#define PP_RXRX 3 /* Supervisor read, User read */`
33
34			`/* Segment Register */`
35
36			`typedef struct _SEGREG`
37			`{`
38			`unsigned long t:1; /* Normal or I/O type */`
39			`unsigned long ks:1; /* Supervisor 'key' (normally 0) */`
40			`unsigned long kp:1; /* User 'key' (normally 1) */`
41			`unsigned long n:1; /* No-execute */`
42			`unsigned long :4; /* Unused */`
43			`unsigned long vsid:24; /* Virtual Segment Identifier */`
44			`} SEGREG;`
45
46			`/* Block Address Translation (BAT) Registers */`
47
48			`typedef struct _BATU /* Upper part of BAT */`
49			`{`
50			`unsigned long bepi:15; /* Effective page index (virtual address) */`
51			`unsigned long :4; /* Unused */`
52			`unsigned long bl:11; /* Block size mask */`
53			`unsigned long vs:1; /* Supervisor valid */`
54			`unsigned long vp:1; /* User valid */`
55			`} BATU;`
56
57			`typedef struct _BATL /* Lower part of BAT */`
58			`{`
59			`unsigned long brpn:15; /* Real page index (physical address) */`
60			`unsigned long :10; /* Unused */`
61			`unsigned long w:1; /* Write-thru cache */`
62			`unsigned long i:1; /* Cache inhibit */`
63			`unsigned long m:1; /* Memory coherence */`
64			`unsigned long g:1; /* Guarded (MBZ) */`
65			`unsigned long :1; /* Unused */`
66			`unsigned long pp:2; /* Page access protections */`
67			`} BATL;`
68
69			`typedef struct _BAT`
70			`{`
71			`BATU batu; /* Upper register */`
72			`BATL batl; /* Lower register */`
73			`} BAT;`
74
75			`/* Block size masks */`
76			`#define BL_128K 0x000`
77			`#define BL_256K 0x001`
78			`#define BL_512K 0x003`
79			`#define BL_1M 0x007`
80			`#define BL_2M 0x00F`
81			`#define BL_4M 0x01F`
82			`#define BL_8M 0x03F`
83			`#define BL_16M 0x07F`
84			`#define BL_32M 0x0FF`
85			`#define BL_64M 0x1FF`
86			`#define BL_128M 0x3FF`
87			`#define BL_256M 0x7FF`
88
89			`/* BAT Access Protection */`
90			`#define BPP_XX 0x00 /* No access */`
91			`#define BPP_RX 0x01 /* Read only */`
92			`#define BPP_RW 0x02 /* Read/write */`
93
94			`/*`
95			`* Simulated two-level MMU. This structure is used by the kernel`
96			`* to keep track of MMU mappings and is used to update/maintain`
97			`* the hardware HASH table which is really a cache of mappings.`
98			`*`
99			`* The simulated structures mimic the hardware available on other`
100			`* platforms, notably the 80x86 and 680x0.`
101			`*/`
102
103			`typedef struct _pte`
104			`{`
105			`unsigned long page_num:20;`
106			`unsigned long flags:12; /* Page flags (with some unused bits) */`
107			`} pte;`
108
109			`#define PD_SHIFT (10+12) /* Page directory */`
110			`#define PD_MASK 0x02FF`
111			`#define PT_SHIFT (12) /* Page Table */`
112			`#define PT_MASK 0x02FF`
113			`#define PG_SHIFT (12) /* Page Entry */`
114
115
116			`/* MMU context */`
117
118			`typedef struct _MMU_context`
119			`{`
120			`SEGREG segs[16]; /* Segment registers */`
121			`pte *pmap; / Two-level page-map structure */`
122			`} MMU_context;`
123
124			`#if 0`
125			`BAT ibat[4]; /* Instruction BAT images */`
126			`BAT dbat[4]; /* Data BAT images */`
127			`PTE hash_table; / Hardware hashed page table */`
128			`int hash_table_size;`
129			`int hash_table_mask;`
130			`unsigned long sdr; /* Hardware image of SDR */`
131			`#endif`
132
133			`/* Used to set up SDR register */`
134			`#define HASH_TABLE_SIZE_64K 0x00010000`
135			`#define HASH_TABLE_SIZE_128K 0x00020000`
136			`#define HASH_TABLE_SIZE_256K 0x00040000`
137			`#define HASH_TABLE_SIZE_512K 0x00080000`
138			`#define HASH_TABLE_SIZE_1M 0x00100000`
139			`#define HASH_TABLE_SIZE_2M 0x00200000`
140			`#define HASH_TABLE_SIZE_4M 0x00400000`
141			`#define HASH_TABLE_MASK_64K 0x000`
142			`#define HASH_TABLE_MASK_128K 0x001`
143			`#define HASH_TABLE_MASK_256K 0x003`
144			`#define HASH_TABLE_MASK_512K 0x007`
145			`#define HASH_TABLE_MASK_1M 0x00F`
146			`#define HASH_TABLE_MASK_2M 0x01F`
147			`#define HASH_TABLE_MASK_4M 0x03F`
148
149			`#define MMU_PAGE_SIZE 4096`
150
151			`extern int MMU_hash_page(struct thread_struct tss, unsigned long va, pte pg);`
152
153			`#endif`

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[/] [or1k/] [trunk/] [rc203soc/] [sw/] [uClinux/] [include/] [asm-ppc/] [mmu.h] - Blame information for rev 1765