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/*

 * PowerPC machine specifics

 */

#ifndef _PPC_MACHINE_H_

#define _PPC_MACHINE_H_ 

/* Bit encodings for Machine State Register (MSR) */

#define MSR_POW         (1<<18)         /* Enable Power Management */

#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */

#define MSR_ILE         (1<<16)         /* Interrupt Little-Endian enable */

#define MSR_EE          (1<<15)         /* External Interrupt enable */

#define MSR_PR          (1<<14)         /* Supervisor/User privilege */

#define MSR_FP          (1<<13)         /* Floating Point enable */

#define MSR_ME          (1<<12)         /* Machine Check enable */

#define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */

#define MSR_SE          (1<<10)         /* Single Step */

#define MSR_BE          (1<<9)          /* Branch Trace */

#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */

#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */

#define MSR_IR          (1<<5)          /* Instruction MMU enable */

#define MSR_DR          (1<<4)          /* Data MMU enable */

#define MSR_RI          (1<<1)          /* Recoverable Exception */

#define MSR_LE          (1<<0)          /* Little-Endian enable */

#define MSR_            MSR_FP|MSR_FE0|MSR_FE1|MSR_ME

#define MSR_USER        MSR_|MSR_PR|MSR_EE|MSR_IR|MSR_DR

/* Bit encodings for Hardware Implementation Register (HID0) */

#define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */

#define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */

#define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */

#define HID0_SBCLK      (1<<27)

#define HID0_EICE       (1<<26)

#define HID0_ECLK       (1<<25)

#define HID0_PAR        (1<<24)

#define HID0_DOZE       (1<<23)

#define HID0_NAP        (1<<22)

#define HID0_SLEEP      (1<<21)

#define HID0_DPM        (1<<20)

#define HID0_ICE        (1<<15)         /* Instruction Cache Enable */

#define HID0_DCE        (1<<14)         /* Data Cache Enable */

#define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */

#define HID0_DLOCK      (1<<12)         /* Data Cache Lock */

#define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */

#define HID0_DCI        (1<<10)         /* Data Cache Invalidate */

#define HID0_SIED       (1<<7)          /* Serial Instruction Execution [Disable] */

#define HID0_BHTE       (1<<2)          /* Branch History Table Enable */

#endif