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jcastillo |
#ifndef __ASM_PPC_PROCESSOR_H
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#define __ASM_PPC_PROCESSOR_H
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/*
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* PowerPC machine specifics
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*/
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#ifndef _PPC_MACHINE_H_
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#define _PPC_MACHINE_H_
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/* Bit encodings for Machine State Register (MSR) */
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#define MSR_POW (1<<18) /* Enable Power Management */
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#define MSR_TGPR (1<<17) /* TLB Update registers in use */
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#define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */
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#define MSR_EE (1<<15) /* External Interrupt enable */
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#define MSR_PR (1<<14) /* Supervisor/User privilege */
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#define MSR_FP (1<<13) /* Floating Point enable */
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#define MSR_ME (1<<12) /* Machine Check enable */
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#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
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#define MSR_SE (1<<10) /* Single Step */
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#define MSR_BE (1<<9) /* Branch Trace */
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#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
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#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
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#define MSR_IR (1<<5) /* Instruction MMU enable */
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#define MSR_DR (1<<4) /* Data MMU enable */
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#define MSR_RI (1<<1) /* Recoverable Exception */
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#define MSR_LE (1<<0) /* Little-Endian enable */
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#define MSR_ MSR_FP|MSR_FE0|MSR_FE1|MSR_ME
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#define MSR_USER MSR_|MSR_PR|MSR_EE|MSR_IR|MSR_DR
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/* Bit encodings for Hardware Implementation Register (HID0) */
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#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
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#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
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#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
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#define HID0_SBCLK (1<<27)
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#define HID0_EICE (1<<26)
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#define HID0_ECLK (1<<25)
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#define HID0_PAR (1<<24)
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#define HID0_DOZE (1<<23)
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#define HID0_NAP (1<<22)
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#define HID0_SLEEP (1<<21)
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#define HID0_DPM (1<<20)
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#define HID0_ICE (1<<15) /* Instruction Cache Enable */
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#define HID0_DCE (1<<14) /* Data Cache Enable */
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#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
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#define HID0_DLOCK (1<<12) /* Data Cache Lock */
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#define HID0_ICFI (1<<11) /* Instruction Cache Flash Invalidate */
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#define HID0_DCI (1<<10) /* Data Cache Invalidate */
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#endif
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static inline void start_thread(struct pt_regs * regs, unsigned long eip, unsigned long esp)
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{
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regs->nip = eip;
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regs->gpr[1] = esp;
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regs->msr = MSR_USER;
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}
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/*
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* Bus types
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*/
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#define EISA_bus 0
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#define EISA_bus__is_a_macro /* for versions in ksyms.c */
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#define MCA_bus 0
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#define MCA_bus__is_a_macro /* for versions in ksyms.c */
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/*
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* Write Protection works right in supervisor mode on the PowerPC
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*/
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#define wp_works_ok 1
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#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
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/*
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* User space process size: 2GB. This is hardcoded into a few places,
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* so don't change it unless you know what you are doing.
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*
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* "this is gonna have to change to 1gig for the sparc" - David S. Miller
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*/
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#define TASK_SIZE (0x80000000UL)
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#define MAX_USER_ADDR TASK_SIZE
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#define MMAP_SEARCH_START (TASK_SIZE/3)
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struct thread_struct
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{
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unsigned long ksp; /* Kernel stack pointer */
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unsigned long *pg_tables; /* MMU information */
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unsigned long segs[16]; /* MMU Segment registers */
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unsigned long last_pc; /* PC when last entered system */
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unsigned long user_stack; /* [User] Stack when entered kernel */
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double fpr[32]; /* Complete floating point set */
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unsigned long wchan; /* Event task is sleeping on */
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unsigned long *regs; /* Pointer to saved register state */
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};
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#define INIT_TSS { \
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0, 0, {0}, \
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0, 0, {0}, \
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}
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#define INIT_MMAP { &init_mm, 0, 0x40000000, \
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PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC }
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#define alloc_kernel_stack() get_free_page(GFP_KERNEL)
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#define free_kernel_stack(page) free_page((page))
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/*
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* Return saved PC of a blocked thread. For now, this is the "user" PC
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*/
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static inline unsigned long thread_saved_pc(struct thread_struct *t)
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{
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return (t->last_pc);
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}
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#endif
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