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jcastillo |
project -new
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#Select FPGA
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set_option -technology VIRTEX2
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set_option -part XC2V3000
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set_option -grade -4
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set_option -package FG676
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set_option -frequency auto
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#
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# Add files to project
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#
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# Memory controllers
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add_file "../../rtl/verilog/rc203/rc203_zbtcontroller.v"
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add_file "../../rtl/verilog/rc203/rc203_romcontroller.v"
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1494 |
jcastillo |
add_file "../../rtl/verilog/rc203/rc203_ethcontroller.v"
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1329 |
jcastillo |
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1599 |
jcastillo |
# RAM wrapppers (you can use unisim.v instead)
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1329 |
jcastillo |
add_file "../RAMB4_S16_S16.v"
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add_file "../RAMB4_S4.v"
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add_file "../RAMB4_S16.v"
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# Dbg_interface
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add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_wb_defines.v"
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add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_cpu.v"
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add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_cpu_defines.v"
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add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_cpu_registers.v"
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add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_crc32_d1.v"
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add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_defines.v"
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add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_register.v"
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add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_top.v"
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add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_wb.v"
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# Tap controller
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add_file "../../rtl/verilog/jtag/tap/rtl/verilog/tap_defines.v"
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add_file "../../rtl/verilog/jtag/tap/rtl/verilog/tap_top.v"
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# UART 16550
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add_file "../../rtl/verilog/uart16550/rtl/verilog/raminfr.v"
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add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v"
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add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_defines.v"
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add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v"
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add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_regs.v"
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add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v"
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add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v"
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add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v"
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add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_top.v"
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add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v"
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add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_wb.v"
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# OR1200 (with 4KB data and instruction caches)
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_alu.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_defines.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_du.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_except.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_if.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_pic.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_pm.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_rf.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_sb.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_top.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_tt.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v"
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# Depending of cache size and register file type you must add or
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# remove some of this files
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v"
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#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v"
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#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v"
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#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v"
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#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v"
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#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v"
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#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v"
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#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v"
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#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v"
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#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v"
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1599 |
jcastillo |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v"
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add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v"
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1329 |
jcastillo |
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# Top files
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add_file "../../rtl/verilog/tc_top.v"
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add_file "../../rtl/verilog/soc.v"
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# Include or1200_defines.v path
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set_option -include_path "../../rtl/verilog/or1200/rtl/verilog/"
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# Results
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impl -name "./rev_1"
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set_option -result_file "./rev_1/rc203soc.edf"
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set_option -top_module soc
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#RUN
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project -run synthesis
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