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/*
 
Based upon IDT provided code with the following release:
 
This source code has been made available to you by IDT on an AS-IS
basis. Anyone receiving this source is licensed under IDT copyrights
to use it in any way he or she deems fit, including copying it,
modifying it, compiling it, and redistributing it either with or
without modifications.  No license under IDT patents or patent
applications is to be implied by the copyright license.
 
Any user of this software should understand that IDT cannot provide
technical support for this software and will not be responsible for
any consequences resulting from the use of this software.
 
Any person who transfers this source code or any derivative work must
include the IDT copyright notice, this paragraph, and the preceeding
two paragraphs in the transferred software.
 
COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 
  $Id: idtcpu.h,v 1.2 2001-09-27 11:59:28 chris Exp $
*/
 
/*
** idtcpu.h -- cpu related defines
*/
 
#ifndef _IDTCPU_H__
#define _IDTCPU_H__
 
/*
 * 950313: Ketan added Register definition for XContext reg.
 *               added define for WAIT instruction.
 * 950421: Ketan added Register definition for Config reg (R3081)
 */
 
/*
** memory configuration and mapping
*/
#define K0BASE  0x80000000
#define K0SIZE  0x20000000
#define K1BASE  0xa0000000
#define K1SIZE  0x20000000
#define K2BASE  0xc0000000
#define K2SIZE  0x20000000
#if defined(CPU_R4000)
#define KSBASE  0xe0000000
#define KSSIZE  0x20000000
#endif
 
#define KUBASE  0
#define KUSIZE  0x80000000
 
/*
** Exception Vectors
*/
#if defined(CPU_R3000)
#define UT_VEC  K0BASE                  /* utlbmiss vector */
#define E_VEC   (K0BASE+0x80)           /* exception vevtor */
#endif
#if defined(CPU_R4000)
#define T_VEC   (K0BASE+0x000)          /* tlbmiss vector */
#define X_VEC   (K0BASE+0x080)          /* xtlbmiss vector */
#define C_VEC   (K0BASE+0x100)          /* cache error vector */
#define E_VEC   (K0BASE+0x180)          /* exception vector */
#endif
#define R_VEC   (K1BASE+0x1fc00000)     /* reset vector */
 
/*
** Address conversion macros
*/
#ifdef CLANGUAGE
#define CAST(as) (as)
#else
#define CAST(as)
#endif
#define K0_TO_K1(x)     (CAST(unsigned)(x)|0xA0000000)  /* kseg0 to kseg1 */
#define K1_TO_K0(x)     (CAST(unsigned)(x)&0x9FFFFFFF)  /* kseg1 to kseg0 */
#define K0_TO_PHYS(x)   (CAST(unsigned)(x)&0x1FFFFFFF)  /* kseg0 to physical */
#define K1_TO_PHYS(x)   (CAST(unsigned)(x)&0x1FFFFFFF)  /* kseg1 to physical */
#define PHYS_TO_K0(x)   (CAST(unsigned)(x)|0x80000000)  /* physical to kseg0 */
#define PHYS_TO_K1(x)   (CAST(unsigned)(x)|0xA0000000)  /* physical to kseg1 */
 
/*
**      Cache size constants
*/
#define MINCACHE        0x200           /* 512       For 3041. */
#define MAXCACHE        0x40000         /* 256*1024   256k */   
 
#if defined(CPU_R4000)
/* R4000 configuration register definitions */
#define CFG_CM          0x80000000      /* Master-Checker mode */
#define CFG_ECMASK      0x70000000      /* System Clock Ratio */
#define CFG_ECBY2       0x00000000      /* divide by 2 */
#define CFG_ECBY3       0x10000000      /* divide by 3 */
#define CFG_ECBY4       0x20000000      /* divide by 4 */
#define CFG_EPMASK      0x0f000000      /* Transmit data pattern */
#define CFG_EPD         0x00000000      /* D */
#define CFG_EPDDX       0x01000000      /* DDX */
#define CFG_EPDDXX      0x02000000      /* DDXX */
#define CFG_EPDXDX      0x03000000      /* DXDX */
#define CFG_EPDDXXX     0x04000000      /* DDXXX */
#define CFG_EPDDXXXX    0x05000000      /* DDXXXX */
#define CFG_EPDXXDXX    0x06000000      /* DXXDXX */
#define CFG_EPDDXXXXX   0x07000000      /* DDXXXXX */
#define CFG_EPDXXXDXXX  0x08000000      /* DXXXDXXX */
#define CFG_SBMASK      0x00c00000      /* Secondary cache block size */
#define CFG_SBSHIFT     22
#define CFG_SB4         0x00000000      /* 4 words */
#define CFG_SB8         0x00400000      /* 8 words */
#define CFG_SB16        0x00800000      /* 16 words */
#define CFG_SB32        0x00c00000      /* 32 words */
#define CFG_SS          0x00200000      /* Split secondary cache */
#define CFG_SW          0x00100000      /* Secondary cache port width */
#define CFG_EWMASK      0x000c0000      /* System port width */
#define CFG_EWSHIFT     18
#define CFG_EW64        0x00000000      /* 64 bit */
#define CFG_EW32        0x00010000      /* 32 bit */
#define CFG_SC          0x00020000      /* Secondary cache absent */
#define CFG_SM          0x00010000      /* Dirty Shared mode disabled */
#define CFG_BE          0x00008000      /* Big Endian */
#define CFG_EM          0x00004000      /* ECC mode enable */
#define CFG_EB          0x00002000      /* Block ordering */
#define CFG_ICMASK      0x00000e00      /* Instruction cache size */
#define CFG_ICSHIFT     9
#define CFG_DCMASK      0x000001c0      /* Data cache size */
#define CFG_DCSHIFT     6
#define CFG_IB          0x00000020      /* Instruction cache block size */
#define CFG_DB          0x00000010      /* Data cache block size */
#define CFG_CU          0x00000008      /* Update on Store Conditional */
#define CFG_K0MASK      0x00000007      /* KSEG0 coherency algorithm */
 
/*
 * R4000 primary cache mode
 */
#define CFG_C_UNCACHED          2
#define CFG_C_NONCOHERENT       3
#define CFG_C_COHERENTXCL       4
#define CFG_C_COHERENTXCLW      5
#define CFG_C_COHERENTUPD       6
 
/*
 * R4000 cache operations (should be in assembler...?)
 */
#define Index_Invalidate_I               0x0         /* 0       0 */
#define Index_Writeback_Inv_D            0x1         /* 0       1 */
#define Index_Invalidate_SI              0x2         /* 0       2 */
#define Index_Writeback_Inv_SD           0x3         /* 0       3 */
#define Index_Load_Tag_I                 0x4         /* 1       0 */
#define Index_Load_Tag_D                 0x5         /* 1       1 */
#define Index_Load_Tag_SI                0x6         /* 1       2 */
#define Index_Load_Tag_SD                0x7         /* 1       3 */
#define Index_Store_Tag_I                0x8         /* 2       0 */
#define Index_Store_Tag_D                0x9         /* 2       1 */
#define Index_Store_Tag_SI               0xA         /* 2       2 */
#define Index_Store_Tag_SD               0xB         /* 2       3 */
#define Create_Dirty_Exc_D               0xD         /* 3       1 */
#define Create_Dirty_Exc_SD              0xF         /* 3       3 */
#define Hit_Invalidate_I                 0x10        /* 4       0 */
#define Hit_Invalidate_D                 0x11        /* 4       1 */
#define Hit_Invalidate_SI                0x12        /* 4       2 */
#define Hit_Invalidate_SD                0x13        /* 4       3 */
#define Hit_Writeback_Inv_D              0x15        /* 5       1 */
#define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
#define Fill_I                           0x14        /* 5       0 */
#define Hit_Writeback_D                  0x19        /* 6       1 */
#define Hit_Writeback_SD                 0x1B        /* 6       3 */
#define Hit_Writeback_I                  0x18        /* 6       0 */
#define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
#define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
 
#ifndef WAIT
#define WAIT .word 0x42000020
#endif WAIT
 
#ifndef wait 
#define wait .word 0x42000020
#endif wait
 
#endif
 
/*
** TLB resource defines
*/
#if defined(CPU_R3000)
#define N_TLB_ENTRIES   64
#define TLB_PGSIZE      0x1000
#define RANDBASE        8
#define TLBLO_PFNMASK   0xfffff000
#define TLBLO_PFNSHIFT  12
#define TLBLO_N         0x800   /* non-cacheable */
#define TLBLO_D         0x400   /* writeable */
#define TLBLO_V         0x200   /* valid bit */
#define TLBLO_G         0x100   /* global access bit */
 
#define TLBHI_VPNMASK   0xfffff000
#define TLBHI_VPNSHIFT  12
#define TLBHI_PIDMASK   0xfc0
#define TLBHI_PIDSHIFT  6
#define TLBHI_NPID      64
 
#define TLBINX_PROBE    0x80000000
#define TLBINX_INXMASK  0x00003f00
#define TLBINX_INXSHIFT 8
 
#define TLBRAND_RANDMASK        0x00003f00
#define TLBRAND_RANDSHIFT       8
 
#define TLBCTXT_BASEMASK        0xffe00000
#define TLBCTXT_BASESHIFT       21
 
#define TLBCTXT_VPNMASK         0x001ffffc
#define TLBCTXT_VPNSHIFT        2
#endif
#if defined(CPU_R4000)
#define N_TLB_ENTRIES   48
 
#define TLBHI_VPN2MASK  0xffffe000
#define TLBHI_PIDMASK   0x000000ff
#define TLBHI_NPID      256
 
#define TLBLO_PFNMASK   0x3fffffc0
#define TLBLO_PFNSHIFT  6
#define TLBLO_D         0x00000004      /* writeable */
#define TLBLO_V         0x00000002      /* valid bit */
#define TLBLO_G         0x00000001      /* global access bit */
#define TLBLO_CMASK     0x00000038      /* cache algorithm mask */
#define TLBLO_CSHIFT    3
 
#define TLBLO_UNCACHED          (CFG_C_UNCACHED<<TLBLO_CSHIFT)
#define TLBLO_NONCOHERENT       (CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
#define TLBLO_COHERENTXCL       (CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
#define TLBLO_COHERENTXCLW      (CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
#define TLBLO_COHERENTUPD       (CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
 
#define TLBINX_PROBE    0x80000000
#define TLBINX_INXMASK  0x0000003f
 
#define TLBRAND_RANDMASK        0x0000003f
 
#define TLBCTXT_BASEMASK        0xff800000
#define TLBCTXT_BASESHIFT       23
 
#define TLBCTXT_VPN2MASK        0x007ffff0
#define TLBCTXT_VPN2SHIFT       4
 
#define TLBPGMASK_MASK          0x01ffe000
#endif
 
#if defined(CPU_R3000)
#define SR_CUMASK       0xf0000000      /* coproc usable bits */
#define SR_CU3          0x80000000      /* Coprocessor 3 usable */
#define SR_CU2          0x40000000      /* Coprocessor 2 usable */
#define SR_CU1          0x20000000      /* Coprocessor 1 usable */
#define SR_CU0          0x10000000      /* Coprocessor 0 usable */
 
#define SR_BEV          0x00400000      /* use boot exception vectors */
 
/* Cache control bits */
#define SR_TS           0x00200000      /* TLB shutdown */
#define SR_PE           0x00100000      /* cache parity error */
#define SR_CM           0x00080000      /* cache miss */
#define SR_PZ           0x00040000      /* cache parity zero */
#define SR_SWC          0x00020000      /* swap cache */
#define SR_ISC          0x00010000      /* Isolate data cache */
 
/*
**      status register interrupt masks and bits
*/
 
#define SR_IMASK        0x0000ff00      /* Interrupt mask */
#define SR_IMASK8       0x00000000      /* mask level 8 */
#define SR_IMASK7       0x00008000      /* mask level 7 */
#define SR_IMASK6       0x0000c000      /* mask level 6 */
#define SR_IMASK5       0x0000e000      /* mask level 5 */
#define SR_IMASK4       0x0000f000      /* mask level 4 */
#define SR_IMASK3       0x0000f800      /* mask level 3 */
#define SR_IMASK2       0x0000fc00      /* mask level 2 */
#define SR_IMASK1       0x0000fe00      /* mask level 1 */
#define SR_IMASK0       0x0000ff00      /* mask level 0 */
 
#define SR_IMASKSHIFT   8
 
#define SR_IBIT8        0x00008000      /* bit level 8 */
#define SR_IBIT7        0x00004000      /* bit level 7 */
#define SR_IBIT6        0x00002000      /* bit level 6 */
#define SR_IBIT5        0x00001000      /* bit level 5 */
#define SR_IBIT4        0x00000800      /* bit level 4 */
#define SR_IBIT3        0x00000400      /* bit level 3 */
#define SR_IBIT2        0x00000200      /* bit level 2 */
#define SR_IBIT1        0x00000100      /* bit level 1 */
 
#define SR_KUO          0x00000020      /* old kernel/user, 0 => k, 1 => u */
#define SR_IEO          0x00000010      /* old interrupt enable, 1 => enable */
#define SR_KUP          0x00000008      /* prev kernel/user, 0 => k, 1 => u */
#define SR_IEP          0x00000004      /* prev interrupt enable, 1 => enable */
#define SR_KUC          0x00000002      /* cur kernel/user, 0 => k, 1 => u */
#define SR_IEC          0x00000001      /* cur interrupt enable, 1 => enable */
#endif
 
#if defined(CPU_R4000)
#define SR_CUMASK       0xf0000000      /* coproc usable bits */
#define SR_CU3          0x80000000      /* Coprocessor 3 usable */
#define SR_CU2          0x40000000      /* Coprocessor 2 usable */
#define SR_CU1          0x20000000      /* Coprocessor 1 usable */
#define SR_CU0          0x10000000      /* Coprocessor 0 usable */
 
#define SR_RP           0x08000000      /* Reduced power operation */
#define SR_FR           0x04000000      /* Additional floating point registers */
#define SR_RE           0x02000000      /* Reverse endian in user mode */
 
#define SR_BEV          0x00400000      /* Use boot exception vectors */
#define SR_TS           0x00200000      /* TLB shutdown */
#define SR_SR           0x00100000      /* Soft reset */
#define SR_CH           0x00040000      /* Cache hit */
#define SR_CE           0x00020000      /* Use cache ECC  */
#define SR_DE           0x00010000      /* Disable cache exceptions */
 
/*
**      status register interrupt masks and bits
*/
 
#define SR_IMASK        0x0000ff00      /* Interrupt mask */
#define SR_IMASK8       0x00000000      /* mask level 8 */
#define SR_IMASK7       0x00008000      /* mask level 7 */
#define SR_IMASK6       0x0000c000      /* mask level 6 */
#define SR_IMASK5       0x0000e000      /* mask level 5 */
#define SR_IMASK4       0x0000f000      /* mask level 4 */
#define SR_IMASK3       0x0000f800      /* mask level 3 */
#define SR_IMASK2       0x0000fc00      /* mask level 2 */
#define SR_IMASK1       0x0000fe00      /* mask level 1 */
#define SR_IMASK0       0x0000ff00      /* mask level 0 */
 
#define SR_IMASKSHIFT   8
 
#define SR_IBIT8        0x00008000      /* bit level 8 */
#define SR_IBIT7        0x00004000      /* bit level 7 */
#define SR_IBIT6        0x00002000      /* bit level 6 */
#define SR_IBIT5        0x00001000      /* bit level 5 */
#define SR_IBIT4        0x00000800      /* bit level 4 */
#define SR_IBIT3        0x00000400      /* bit level 3 */
#define SR_IBIT2        0x00000200      /* bit level 2 */
#define SR_IBIT1        0x00000100      /* bit level 1 */
 
#define SR_KSMASK       0x00000018      /* Kernel mode mask */
#define SR_KSUSER       0x00000010      /* User mode */
#define SR_KSSUPER      0x00000008      /* Supervisor mode */
#define SR_KSKERNEL     0x00000000      /* Kernel mode */
#define SR_ERL          0x00000004      /* Error level */
#define SR_EXL          0x00000002      /* Exception level */
#define SR_IE           0x00000001      /* Interrupts enabled */
#endif
 
 
 
/*
 * Cause Register
 */
#define CAUSE_BD        0x80000000      /* Branch delay slot */
#define CAUSE_CEMASK    0x30000000      /* coprocessor error */
#define CAUSE_CESHIFT   28
 
 
#define CAUSE_IPMASK    0x0000FF00      /* Pending interrupt mask */
#define CAUSE_IPSHIFT   8
 
#define CAUSE_EXCMASK   0x0000003C      /* Cause code bits */
#define CAUSE_EXCSHIFT  2
 
#ifndef XDS
/*
**  Coprocessor 0 registers
*/
#define C0_INX          $0              /* tlb index */
#define C0_RAND         $1              /* tlb random */
#if defined(CPU_R3000)
#define C0_TLBLO        $2              /* tlb entry low */
#endif
#if defined(CPU_R4000)
#define C0_TLBLO0       $2              /* tlb entry low 0 */
#define C0_TLBLO1       $3              /* tlb entry low 1 */
#endif
 
#define C0_CTXT         $4              /* tlb context */
 
#if defined(CPU_R4000)
#define C0_PAGEMASK     $5              /* tlb page mask */
#define C0_WIRED        $6              /* number of wired tlb entries */
#endif
 
#define C0_BADVADDR     $8              /* bad virtual address */
 
#if defined(CPU_R4000)
#define C0_COUNT        $9              /* cycle count */
#endif
 
#define C0_TLBHI        $10             /* tlb entry hi */
 
#if defined(CPU_R4000)
#define C0_COMPARE      $11             /* cyccle count comparator  */
#endif
 
#define C0_SR           $12             /* status register */
#define C0_CAUSE        $13             /* exception cause */
#define C0_EPC          $14             /* exception pc */
#define C0_PRID         $15             /* revision identifier */
 
#if defined(CPU_R3000)
#define C0_CONFIG   $3     /* configuration register R3081*/
#endif
 
#if defined(CPU_R4000)
#define C0_CONFIG       $16             /* configuration register */
#define C0_LLADDR       $17             /* linked load address */
#define C0_WATCHLO      $18             /* watchpoint trap register */
#define C0_WATCHHI      $19             /* watchpoint trap register */
#define C0_XCTXT    $20     /* extended tlb context */
#define C0_ECC          $26             /* secondary cache ECC control */
#define C0_CACHEERR     $27             /* cache error status */
#define C0_TAGLO        $28             /* cache tag lo */
#define C0_TAGHI        $29             /* cache tag hi */
#define C0_ERRPC        $30             /* cache error pc */
#endif
 
#endif XDS
 
#ifdef R4650
#define IWATCH $18
#define DWATCH $19
#define IBASE  $0
#define IBOUND $1
#define DBASE  $2
#define DBOUND $3
#define CALG    $17
#endif
 
#endif /* _IDTCPU_H__ */
 

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[/] [or1k/] [trunk/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [mips64orion/] [idtcpu.h] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	158	chris	`/*`
2
3			`Based upon IDT provided code with the following release:`
4
5			`This source code has been made available to you by IDT on an AS-IS`
6			`basis. Anyone receiving this source is licensed under IDT copyrights`
7			`to use it in any way he or she deems fit, including copying it,`
8			`modifying it, compiling it, and redistributing it either with or`
9			`without modifications. No license under IDT patents or patent`
10			`applications is to be implied by the copyright license.`
11
12			`Any user of this software should understand that IDT cannot provide`
13			`technical support for this software and will not be responsible for`
14			`any consequences resulting from the use of this software.`
15
16			`Any person who transfers this source code or any derivative work must`
17			`include the IDT copyright notice, this paragraph, and the preceeding`
18			`two paragraphs in the transferred software.`
19
20			`COPYRIGHT IDT CORPORATION 1996`
21			`LICENSED MATERIAL - PROGRAM PROPERTY OF IDT`
22
23	208	chris	$Id: idtcpu.h,v 1.2 2001-09-27 11:59:28 chris Exp $
24	158	chris	`*/`
25
26			`/*`
27			`** idtcpu.h -- cpu related defines`
28			`*/`
29
30			`#ifndef _IDTCPU_H__`
31			`#define _IDTCPU_H__`
32
33			`/*`
34			`* 950313: Ketan added Register definition for XContext reg.`
35			`* added define for WAIT instruction.`
36			`* 950421: Ketan added Register definition for Config reg (R3081)`
37			`*/`
38
39			`/*`
40			`** memory configuration and mapping`
41			`*/`
42			`#define K0BASE 0x80000000`
43			`#define K0SIZE 0x20000000`
44			`#define K1BASE 0xa0000000`
45			`#define K1SIZE 0x20000000`
46			`#define K2BASE 0xc0000000`
47			`#define K2SIZE 0x20000000`
48			`#if defined(CPU_R4000)`
49			`#define KSBASE 0xe0000000`
50			`#define KSSIZE 0x20000000`
51			`#endif`
52
53			`#define KUBASE 0`
54			`#define KUSIZE 0x80000000`
55
56			`/*`
57			`** Exception Vectors`
58			`*/`
59			`#if defined(CPU_R3000)`
60			`#define UT_VEC K0BASE /* utlbmiss vector */`
61			`#define E_VEC (K0BASE+0x80) /* exception vevtor */`
62			`#endif`
63			`#if defined(CPU_R4000)`
64			`#define T_VEC (K0BASE+0x000) /* tlbmiss vector */`
65			`#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */`
66			`#define C_VEC (K0BASE+0x100) /* cache error vector */`
67			`#define E_VEC (K0BASE+0x180) /* exception vector */`
68			`#endif`
69			`#define R_VEC (K1BASE+0x1fc00000) /* reset vector */`
70
71			`/*`
72			`** Address conversion macros`
73			`*/`
74			`#ifdef CLANGUAGE`
75			`#define CAST(as) (as)`
76			`#else`
77			`#define CAST(as)`
78			`#endif`
79			`#define K0_TO_K1(x) (CAST(unsigned)(x)\|0xA0000000) /* kseg0 to kseg1 */`
80			`#define K1_TO_K0(x) (CAST(unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */`
81			`#define K0_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */`
82			`#define K1_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */`
83			`#define PHYS_TO_K0(x) (CAST(unsigned)(x)\|0x80000000) /* physical to kseg0 */`
84			`#define PHYS_TO_K1(x) (CAST(unsigned)(x)\|0xA0000000) /* physical to kseg1 */`
85
86			`/*`
87			`** Cache size constants`
88			`*/`
89			`#define MINCACHE 0x200 /* 512 For 3041. */`
90			`#define MAXCACHE 0x40000 /* 2561024 256k /`
91
92			`#if defined(CPU_R4000)`
93			`/* R4000 configuration register definitions */`
94			`#define CFG_CM 0x80000000 /* Master-Checker mode */`
95			`#define CFG_ECMASK 0x70000000 /* System Clock Ratio */`
96			`#define CFG_ECBY2 0x00000000 /* divide by 2 */`
97			`#define CFG_ECBY3 0x10000000 /* divide by 3 */`
98			`#define CFG_ECBY4 0x20000000 /* divide by 4 */`
99			`#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */`
100			`#define CFG_EPD 0x00000000 /* D */`
101			`#define CFG_EPDDX 0x01000000 /* DDX */`
102			`#define CFG_EPDDXX 0x02000000 /* DDXX */`
103			`#define CFG_EPDXDX 0x03000000 /* DXDX */`
104			`#define CFG_EPDDXXX 0x04000000 /* DDXXX */`
105			`#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */`
106			`#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */`
107			`#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */`
108			`#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */`
109			`#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */`
110			`#define CFG_SBSHIFT 22`
111			`#define CFG_SB4 0x00000000 /* 4 words */`
112			`#define CFG_SB8 0x00400000 /* 8 words */`
113			`#define CFG_SB16 0x00800000 /* 16 words */`
114			`#define CFG_SB32 0x00c00000 /* 32 words */`
115			`#define CFG_SS 0x00200000 /* Split secondary cache */`
116			`#define CFG_SW 0x00100000 /* Secondary cache port width */`
117			`#define CFG_EWMASK 0x000c0000 /* System port width */`
118			`#define CFG_EWSHIFT 18`
119			`#define CFG_EW64 0x00000000 /* 64 bit */`
120			`#define CFG_EW32 0x00010000 /* 32 bit */`
121			`#define CFG_SC 0x00020000 /* Secondary cache absent */`
122			`#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */`
123			`#define CFG_BE 0x00008000 /* Big Endian */`
124			`#define CFG_EM 0x00004000 /* ECC mode enable */`
125			`#define CFG_EB 0x00002000 /* Block ordering */`
126			`#define CFG_ICMASK 0x00000e00 /* Instruction cache size */`
127			`#define CFG_ICSHIFT 9`
128			`#define CFG_DCMASK 0x000001c0 /* Data cache size */`
129			`#define CFG_DCSHIFT 6`
130			`#define CFG_IB 0x00000020 /* Instruction cache block size */`
131			`#define CFG_DB 0x00000010 /* Data cache block size */`
132			`#define CFG_CU 0x00000008 /* Update on Store Conditional */`
133			`#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */`
134
135			`/*`
136			`* R4000 primary cache mode`
137			`*/`
138			`#define CFG_C_UNCACHED 2`
139			`#define CFG_C_NONCOHERENT 3`
140			`#define CFG_C_COHERENTXCL 4`
141			`#define CFG_C_COHERENTXCLW 5`
142			`#define CFG_C_COHERENTUPD 6`
143
144			`/*`
145			`* R4000 cache operations (should be in assembler...?)`
146			`*/`
147			`#define Index_Invalidate_I 0x0 /* 0 0 */`
148			`#define Index_Writeback_Inv_D 0x1 /* 0 1 */`
149			`#define Index_Invalidate_SI 0x2 /* 0 2 */`
150			`#define Index_Writeback_Inv_SD 0x3 /* 0 3 */`
151			`#define Index_Load_Tag_I 0x4 /* 1 0 */`
152			`#define Index_Load_Tag_D 0x5 /* 1 1 */`
153			`#define Index_Load_Tag_SI 0x6 /* 1 2 */`
154			`#define Index_Load_Tag_SD 0x7 /* 1 3 */`
155			`#define Index_Store_Tag_I 0x8 /* 2 0 */`
156			`#define Index_Store_Tag_D 0x9 /* 2 1 */`
157			`#define Index_Store_Tag_SI 0xA /* 2 2 */`
158			`#define Index_Store_Tag_SD 0xB /* 2 3 */`
159			`#define Create_Dirty_Exc_D 0xD /* 3 1 */`
160			`#define Create_Dirty_Exc_SD 0xF /* 3 3 */`
161			`#define Hit_Invalidate_I 0x10 /* 4 0 */`
162			`#define Hit_Invalidate_D 0x11 /* 4 1 */`
163			`#define Hit_Invalidate_SI 0x12 /* 4 2 */`
164			`#define Hit_Invalidate_SD 0x13 /* 4 3 */`
165			`#define Hit_Writeback_Inv_D 0x15 /* 5 1 */`
166			`#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */`
167			`#define Fill_I 0x14 /* 5 0 */`
168			`#define Hit_Writeback_D 0x19 /* 6 1 */`
169			`#define Hit_Writeback_SD 0x1B /* 6 3 */`
170			`#define Hit_Writeback_I 0x18 /* 6 0 */`
171			`#define Hit_Set_Virtual_SI 0x1E /* 7 2 */`
172			`#define Hit_Set_Virtual_SD 0x1F /* 7 3 */`
173
174			`#ifndef WAIT`
175			`#define WAIT .word 0x42000020`
176			`#endif WAIT`
177
178			`#ifndef wait`
179			`#define wait .word 0x42000020`
180			`#endif wait`
181
182			`#endif`
183
184			`/*`
185			`** TLB resource defines`
186			`*/`
187			`#if defined(CPU_R3000)`
188			`#define N_TLB_ENTRIES 64`
189			`#define TLB_PGSIZE 0x1000`
190			`#define RANDBASE 8`
191			`#define TLBLO_PFNMASK 0xfffff000`
192			`#define TLBLO_PFNSHIFT 12`
193			`#define TLBLO_N 0x800 /* non-cacheable */`
194			`#define TLBLO_D 0x400 /* writeable */`
195			`#define TLBLO_V 0x200 /* valid bit */`
196			`#define TLBLO_G 0x100 /* global access bit */`
197
198			`#define TLBHI_VPNMASK 0xfffff000`
199			`#define TLBHI_VPNSHIFT 12`
200			`#define TLBHI_PIDMASK 0xfc0`
201			`#define TLBHI_PIDSHIFT 6`
202			`#define TLBHI_NPID 64`
203
204			`#define TLBINX_PROBE 0x80000000`
205			`#define TLBINX_INXMASK 0x00003f00`
206			`#define TLBINX_INXSHIFT 8`
207
208			`#define TLBRAND_RANDMASK 0x00003f00`
209			`#define TLBRAND_RANDSHIFT 8`
210
211			`#define TLBCTXT_BASEMASK 0xffe00000`
212			`#define TLBCTXT_BASESHIFT 21`
213
214			`#define TLBCTXT_VPNMASK 0x001ffffc`
215			`#define TLBCTXT_VPNSHIFT 2`
216			`#endif`
217			`#if defined(CPU_R4000)`
218			`#define N_TLB_ENTRIES 48`
219
220			`#define TLBHI_VPN2MASK 0xffffe000`
221			`#define TLBHI_PIDMASK 0x000000ff`
222			`#define TLBHI_NPID 256`
223
224			`#define TLBLO_PFNMASK 0x3fffffc0`
225			`#define TLBLO_PFNSHIFT 6`
226			`#define TLBLO_D 0x00000004 /* writeable */`
227			`#define TLBLO_V 0x00000002 /* valid bit */`
228			`#define TLBLO_G 0x00000001 /* global access bit */`
229			`#define TLBLO_CMASK 0x00000038 /* cache algorithm mask */`
230			`#define TLBLO_CSHIFT 3`
231
232			`#define TLBLO_UNCACHED (CFG_C_UNCACHED<<TLBLO_CSHIFT)`
233			`#define TLBLO_NONCOHERENT (CFG_C_NONCOHERENT<<TLBLO_CSHIFT)`
234			`#define TLBLO_COHERENTXCL (CFG_C_COHERENTXCL<<TLBLO_CSHIFT)`
235			`#define TLBLO_COHERENTXCLW (CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)`
236			`#define TLBLO_COHERENTUPD (CFG_C_COHERENTUPD<<TLBLO_CSHIFT)`
237
238			`#define TLBINX_PROBE 0x80000000`
239			`#define TLBINX_INXMASK 0x0000003f`
240
241			`#define TLBRAND_RANDMASK 0x0000003f`
242
243			`#define TLBCTXT_BASEMASK 0xff800000`
244			`#define TLBCTXT_BASESHIFT 23`
245
246			`#define TLBCTXT_VPN2MASK 0x007ffff0`
247			`#define TLBCTXT_VPN2SHIFT 4`
248
249			`#define TLBPGMASK_MASK 0x01ffe000`
250			`#endif`
251
252			`#if defined(CPU_R3000)`
253			`#define SR_CUMASK 0xf0000000 /* coproc usable bits */`
254			`#define SR_CU3 0x80000000 /* Coprocessor 3 usable */`
255			`#define SR_CU2 0x40000000 /* Coprocessor 2 usable */`
256			`#define SR_CU1 0x20000000 /* Coprocessor 1 usable */`
257			`#define SR_CU0 0x10000000 /* Coprocessor 0 usable */`
258
259			`#define SR_BEV 0x00400000 /* use boot exception vectors */`
260
261			`/* Cache control bits */`
262			`#define SR_TS 0x00200000 /* TLB shutdown */`
263			`#define SR_PE 0x00100000 /* cache parity error */`
264			`#define SR_CM 0x00080000 /* cache miss */`
265			`#define SR_PZ 0x00040000 /* cache parity zero */`
266			`#define SR_SWC 0x00020000 /* swap cache */`
267			`#define SR_ISC 0x00010000 /* Isolate data cache */`
268
269			`/*`
270			`** status register interrupt masks and bits`
271			`*/`
272
273			`#define SR_IMASK 0x0000ff00 /* Interrupt mask */`
274			`#define SR_IMASK8 0x00000000 /* mask level 8 */`
275			`#define SR_IMASK7 0x00008000 /* mask level 7 */`
276			`#define SR_IMASK6 0x0000c000 /* mask level 6 */`
277			`#define SR_IMASK5 0x0000e000 /* mask level 5 */`
278			`#define SR_IMASK4 0x0000f000 /* mask level 4 */`
279			`#define SR_IMASK3 0x0000f800 /* mask level 3 */`
280			`#define SR_IMASK2 0x0000fc00 /* mask level 2 */`
281			`#define SR_IMASK1 0x0000fe00 /* mask level 1 */`
282			`#define SR_IMASK0 0x0000ff00 /* mask level 0 */`
283
284			`#define SR_IMASKSHIFT 8`
285
286			`#define SR_IBIT8 0x00008000 /* bit level 8 */`
287			`#define SR_IBIT7 0x00004000 /* bit level 7 */`
288			`#define SR_IBIT6 0x00002000 /* bit level 6 */`
289			`#define SR_IBIT5 0x00001000 /* bit level 5 */`
290			`#define SR_IBIT4 0x00000800 /* bit level 4 */`
291			`#define SR_IBIT3 0x00000400 /* bit level 3 */`
292			`#define SR_IBIT2 0x00000200 /* bit level 2 */`
293			`#define SR_IBIT1 0x00000100 /* bit level 1 */`
294
295			`#define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */`
296			`#define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */`
297			`#define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */`
298			`#define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */`
299			`#define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */`
300			`#define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */`
301			`#endif`
302
303			`#if defined(CPU_R4000)`
304			`#define SR_CUMASK 0xf0000000 /* coproc usable bits */`
305			`#define SR_CU3 0x80000000 /* Coprocessor 3 usable */`
306			`#define SR_CU2 0x40000000 /* Coprocessor 2 usable */`
307			`#define SR_CU1 0x20000000 /* Coprocessor 1 usable */`
308			`#define SR_CU0 0x10000000 /* Coprocessor 0 usable */`
309
310			`#define SR_RP 0x08000000 /* Reduced power operation */`
311			`#define SR_FR 0x04000000 /* Additional floating point registers */`
312			`#define SR_RE 0x02000000 /* Reverse endian in user mode */`
313
314			`#define SR_BEV 0x00400000 /* Use boot exception vectors */`
315			`#define SR_TS 0x00200000 /* TLB shutdown */`
316			`#define SR_SR 0x00100000 /* Soft reset */`
317			`#define SR_CH 0x00040000 /* Cache hit */`
318			`#define SR_CE 0x00020000 /* Use cache ECC */`
319			`#define SR_DE 0x00010000 /* Disable cache exceptions */`
320
321			`/*`
322			`** status register interrupt masks and bits`
323			`*/`
324
325			`#define SR_IMASK 0x0000ff00 /* Interrupt mask */`
326			`#define SR_IMASK8 0x00000000 /* mask level 8 */`
327			`#define SR_IMASK7 0x00008000 /* mask level 7 */`
328			`#define SR_IMASK6 0x0000c000 /* mask level 6 */`
329			`#define SR_IMASK5 0x0000e000 /* mask level 5 */`
330			`#define SR_IMASK4 0x0000f000 /* mask level 4 */`
331			`#define SR_IMASK3 0x0000f800 /* mask level 3 */`
332			`#define SR_IMASK2 0x0000fc00 /* mask level 2 */`
333			`#define SR_IMASK1 0x0000fe00 /* mask level 1 */`
334			`#define SR_IMASK0 0x0000ff00 /* mask level 0 */`
335
336			`#define SR_IMASKSHIFT 8`
337
338			`#define SR_IBIT8 0x00008000 /* bit level 8 */`
339			`#define SR_IBIT7 0x00004000 /* bit level 7 */`
340			`#define SR_IBIT6 0x00002000 /* bit level 6 */`
341			`#define SR_IBIT5 0x00001000 /* bit level 5 */`
342			`#define SR_IBIT4 0x00000800 /* bit level 4 */`
343			`#define SR_IBIT3 0x00000400 /* bit level 3 */`
344			`#define SR_IBIT2 0x00000200 /* bit level 2 */`
345			`#define SR_IBIT1 0x00000100 /* bit level 1 */`
346
347			`#define SR_KSMASK 0x00000018 /* Kernel mode mask */`
348			`#define SR_KSUSER 0x00000010 /* User mode */`
349			`#define SR_KSSUPER 0x00000008 /* Supervisor mode */`
350			`#define SR_KSKERNEL 0x00000000 /* Kernel mode */`
351			`#define SR_ERL 0x00000004 /* Error level */`
352			`#define SR_EXL 0x00000002 /* Exception level */`
353			`#define SR_IE 0x00000001 /* Interrupts enabled */`
354			`#endif`
355
356
357
358			`/*`
359			`* Cause Register`
360			`*/`
361			`#define CAUSE_BD 0x80000000 /* Branch delay slot */`
362			`#define CAUSE_CEMASK 0x30000000 /* coprocessor error */`
363			`#define CAUSE_CESHIFT 28`
364
365
366			`#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */`
367			`#define CAUSE_IPSHIFT 8`
368
369			`#define CAUSE_EXCMASK 0x0000003C /* Cause code bits */`
370			`#define CAUSE_EXCSHIFT 2`
371
372			`#ifndef XDS`
373			`/*`
374			`** Coprocessor 0 registers`
375			`*/`
376			`#define C0_INX $0 /* tlb index */`
377			`#define C0_RAND $1 /* tlb random */`
378			`#if defined(CPU_R3000)`
379			`#define C0_TLBLO $2 /* tlb entry low */`
380			`#endif`
381			`#if defined(CPU_R4000)`
382			`#define C0_TLBLO0 $2 /* tlb entry low 0 */`
383			`#define C0_TLBLO1 $3 /* tlb entry low 1 */`
384			`#endif`
385
386			`#define C0_CTXT $4 /* tlb context */`
387
388			`#if defined(CPU_R4000)`
389			`#define C0_PAGEMASK $5 /* tlb page mask */`
390			`#define C0_WIRED $6 /* number of wired tlb entries */`
391			`#endif`
392
393			`#define C0_BADVADDR $8 /* bad virtual address */`
394
395			`#if defined(CPU_R4000)`
396			`#define C0_COUNT $9 /* cycle count */`
397			`#endif`
398
399			`#define C0_TLBHI $10 /* tlb entry hi */`
400
401			`#if defined(CPU_R4000)`
402			`#define C0_COMPARE $11 /* cyccle count comparator */`
403			`#endif`
404
405			`#define C0_SR $12 /* status register */`
406			`#define C0_CAUSE $13 /* exception cause */`
407			`#define C0_EPC $14 /* exception pc */`
408			`#define C0_PRID $15 /* revision identifier */`
409
410			`#if defined(CPU_R3000)`
411			`#define C0_CONFIG $3 /* configuration register R3081*/`
412			`#endif`
413
414			`#if defined(CPU_R4000)`
415			`#define C0_CONFIG $16 /* configuration register */`
416			`#define C0_LLADDR $17 /* linked load address */`
417			`#define C0_WATCHLO $18 /* watchpoint trap register */`
418			`#define C0_WATCHHI $19 /* watchpoint trap register */`
419			`#define C0_XCTXT $20 /* extended tlb context */`
420			`#define C0_ECC $26 /* secondary cache ECC control */`
421			`#define C0_CACHEERR $27 /* cache error status */`
422			`#define C0_TAGLO $28 /* cache tag lo */`
423			`#define C0_TAGHI $29 /* cache tag hi */`
424			`#define C0_ERRPC $30 /* cache error pc */`
425			`#endif`
426
427			`#endif XDS`
428
429			`#ifdef R4650`
430			`#define IWATCH $18`
431			`#define DWATCH $19`
432			`#define IBASE $0`
433			`#define IBOUND $1`
434			`#define DBASE $2`
435			`#define DBOUND $3`
436			`#define CALG $17`
437			`#endif`
438
439			`#endif /* _IDTCPU_H__ */`
440