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[/] [or1k/] [trunk/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [powerpc/] [new_exception_processing/] [cpu_asm.S] - Blame information for rev 1765

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1 158 chris
 
2
/*  cpu_asm.s   1.1 - 95/12/04
3
 *
4
 *  This file contains the assembly code for the PowerPC implementation
5
 *  of RTEMS.
6
 *
7
 *  Author:     Andrew Bray 
8
 *
9
 *  COPYRIGHT (c) 1995 by i-cubed ltd.
10
 *
11
 *  To anyone who acknowledges that this file is provided "AS IS"
12
 *  without any express or implied warranty:
13
 *      permission to use, copy, modify, and distribute this file
14
 *      for any purpose is hereby granted without fee, provided that
15
 *      the above copyright notice and this notice appears in all
16
 *      copies, and that the name of i-cubed limited not be used in
17
 *      advertising or publicity pertaining to distribution of the
18
 *      software without specific, written prior permission.
19
 *      i-cubed limited makes no representations about the suitability
20
 *      of this software for any purpose.
21
 *
22
 *  Derived from c/src/exec/cpu/no_cpu/cpu_asm.c:
23
 *
24
 *  COPYRIGHT (c) 1989-1997.
25
 *  On-Line Applications Research Corporation (OAR).
26
 *  Copyright assigned to U.S. Government, 1994.
27
 *
28
 *  The license and distribution terms for this file may in
29
 *  the file LICENSE in this distribution or at
30
 *  http://www.OARcorp.com/rtems/license.html.
31
 *
32 208 chris
 *  $Id: cpu_asm.S,v 1.2 2001-09-27 11:59:29 chris Exp $
33 158 chris
 */
34
 
35
#include 
36
 
37
/*
38
 * Offsets for various Contexts
39
 */
40
        .set    GP_1, 0
41
        .set    GP_2, (GP_1 + 4)
42
        .set    GP_13, (GP_2 + 4)
43
        .set    GP_14, (GP_13 + 4)
44
 
45
        .set    GP_15, (GP_14 + 4)
46
        .set    GP_16, (GP_15 + 4)
47
        .set    GP_17, (GP_16 + 4)
48
        .set    GP_18, (GP_17 + 4)
49
 
50
        .set    GP_19, (GP_18 + 4)
51
        .set    GP_20, (GP_19 + 4)
52
        .set    GP_21, (GP_20 + 4)
53
        .set    GP_22, (GP_21 + 4)
54
 
55
        .set    GP_23, (GP_22 + 4)
56
        .set    GP_24, (GP_23 + 4)
57
        .set    GP_25, (GP_24 + 4)
58
        .set    GP_26, (GP_25 + 4)
59
 
60
        .set    GP_27, (GP_26 + 4)
61
        .set    GP_28, (GP_27 + 4)
62
        .set    GP_29, (GP_28 + 4)
63
        .set    GP_30, (GP_29 + 4)
64
 
65
        .set    GP_31, (GP_30 + 4)
66
        .set    GP_CR, (GP_31 + 4)
67
        .set    GP_PC, (GP_CR + 4)
68
        .set    GP_MSR, (GP_PC + 4)
69
 
70
        .set    FP_0, 0
71
        .set    FP_1, (FP_0 + 4)
72
        .set    FP_2, (FP_1 + 4)
73
        .set    FP_3, (FP_2 + 4)
74
        .set    FP_4, (FP_3 + 4)
75
        .set    FP_5, (FP_4 + 4)
76
        .set    FP_6, (FP_5 + 4)
77
        .set    FP_7, (FP_6 + 4)
78
        .set    FP_8, (FP_7 + 4)
79
        .set    FP_9, (FP_8 + 4)
80
        .set    FP_10, (FP_9 + 4)
81
        .set    FP_11, (FP_10 + 4)
82
        .set    FP_12, (FP_11 + 4)
83
        .set    FP_13, (FP_12 + 4)
84
        .set    FP_14, (FP_13 + 4)
85
        .set    FP_15, (FP_14 + 4)
86
        .set    FP_16, (FP_15 + 4)
87
        .set    FP_17, (FP_16 + 4)
88
        .set    FP_18, (FP_17 + 4)
89
        .set    FP_19, (FP_18 + 4)
90
        .set    FP_20, (FP_19 + 4)
91
        .set    FP_21, (FP_20 + 4)
92
        .set    FP_22, (FP_21 + 4)
93
        .set    FP_23, (FP_22 + 4)
94
        .set    FP_24, (FP_23 + 4)
95
        .set    FP_25, (FP_24 + 4)
96
        .set    FP_26, (FP_25 + 4)
97
        .set    FP_27, (FP_26 + 4)
98
        .set    FP_28, (FP_27 + 4)
99
        .set    FP_29, (FP_28 + 4)
100
        .set    FP_30, (FP_29 + 4)
101
        .set    FP_31, (FP_30 + 4)
102
        .set    FP_FPSCR, (FP_31 + 4)
103
 
104
        .set    IP_LINK, 0
105
        .set    IP_0, (IP_LINK + 8)
106
        .set    IP_2, (IP_0 + 4)
107
 
108
        .set    IP_3, (IP_2 + 4)
109
        .set    IP_4, (IP_3 + 4)
110
        .set    IP_5, (IP_4 + 4)
111
        .set    IP_6, (IP_5 + 4)
112
 
113
        .set    IP_7, (IP_6 + 4)
114
        .set    IP_8, (IP_7 + 4)
115
        .set    IP_9, (IP_8 + 4)
116
        .set    IP_10, (IP_9 + 4)
117
 
118
        .set    IP_11, (IP_10 + 4)
119
        .set    IP_12, (IP_11 + 4)
120
        .set    IP_13, (IP_12 + 4)
121
        .set    IP_28, (IP_13 + 4)
122
 
123
        .set    IP_29, (IP_28 + 4)
124
        .set    IP_30, (IP_29 + 4)
125
        .set    IP_31, (IP_30 + 4)
126
        .set    IP_CR, (IP_31 + 4)
127
 
128
        .set    IP_CTR, (IP_CR + 4)
129
        .set    IP_XER, (IP_CTR + 4)
130
        .set    IP_LR, (IP_XER + 4)
131
        .set    IP_PC, (IP_LR + 4)
132
 
133
        .set    IP_MSR, (IP_PC + 4)
134
        .set    IP_END, (IP_MSR + 16)
135
 
136
        BEGIN_CODE
137
/*
138
 *  _CPU_Context_save_fp_context
139
 *
140
 *  This routine is responsible for saving the FP context
141
 *  at *fp_context_ptr.  If the point to load the FP context
142
 *  from is changed then the pointer is modified by this routine.
143
 *
144
 *  Sometimes a macro implementation of this is in cpu.h which dereferences
145
 *  the ** and a similarly named routine in this file is passed something
146
 *  like a (Context_Control_fp *).  The general rule on making this decision
147
 *  is to avoid writing assembly language.
148
 */
149
 
150
        ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
151
        PUBLIC_PROC (_CPU_Context_save_fp)
152
PROC (_CPU_Context_save_fp):
153
#if (PPC_HAS_FPU == 1)
154
        lwz     r3, 0(r3)
155
        stfs    f0, FP_0(r3)
156
        stfs    f1, FP_1(r3)
157
        stfs    f2, FP_2(r3)
158
        stfs    f3, FP_3(r3)
159
        stfs    f4, FP_4(r3)
160
        stfs    f5, FP_5(r3)
161
        stfs    f6, FP_6(r3)
162
        stfs    f7, FP_7(r3)
163
        stfs    f8, FP_8(r3)
164
        stfs    f9, FP_9(r3)
165
        stfs    f10, FP_10(r3)
166
        stfs    f11, FP_11(r3)
167
        stfs    f12, FP_12(r3)
168
        stfs    f13, FP_13(r3)
169
        stfs    f14, FP_14(r3)
170
        stfs    f15, FP_15(r3)
171
        stfs    f16, FP_16(r3)
172
        stfs    f17, FP_17(r3)
173
        stfs    f18, FP_18(r3)
174
        stfs    f19, FP_19(r3)
175
        stfs    f20, FP_20(r3)
176
        stfs    f21, FP_21(r3)
177
        stfs    f22, FP_22(r3)
178
        stfs    f23, FP_23(r3)
179
        stfs    f24, FP_24(r3)
180
        stfs    f25, FP_25(r3)
181
        stfs    f26, FP_26(r3)
182
        stfs    f27, FP_27(r3)
183
        stfs    f28, FP_28(r3)
184
        stfs    f29, FP_29(r3)
185
        stfs    f30, FP_30(r3)
186
        stfs    f31, FP_31(r3)
187
        mffs    f2
188
        stfs    f2, FP_FPSCR(r3)
189
#endif
190
        blr
191
 
192
/*
193
 *  _CPU_Context_restore_fp_context
194
 *
195
 *  This routine is responsible for restoring the FP context
196
 *  at *fp_context_ptr.  If the point to load the FP context
197
 *  from is changed then the pointer is modified by this routine.
198
 *
199
 *  Sometimes a macro implementation of this is in cpu.h which dereferences
200
 *  the ** and a similarly named routine in this file is passed something
201
 *  like a (Context_Control_fp *).  The general rule on making this decision
202
 *  is to avoid writing assembly language.
203
 */
204
 
205
        ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
206
        PUBLIC_PROC (_CPU_Context_restore_fp)
207
PROC (_CPU_Context_restore_fp):
208
#if (PPC_HAS_FPU == 1)
209
        lwz     r3, 0(r3)
210
        lfs     f2, FP_FPSCR(r3)
211
        mtfsf   255, f2
212
        lfs     f0, FP_0(r3)
213
        lfs     f1, FP_1(r3)
214
        lfs     f2, FP_2(r3)
215
        lfs     f3, FP_3(r3)
216
        lfs     f4, FP_4(r3)
217
        lfs     f5, FP_5(r3)
218
        lfs     f6, FP_6(r3)
219
        lfs     f7, FP_7(r3)
220
        lfs     f8, FP_8(r3)
221
        lfs     f9, FP_9(r3)
222
        lfs     f10, FP_10(r3)
223
        lfs     f11, FP_11(r3)
224
        lfs     f12, FP_12(r3)
225
        lfs     f13, FP_13(r3)
226
        lfs     f14, FP_14(r3)
227
        lfs     f15, FP_15(r3)
228
        lfs     f16, FP_16(r3)
229
        lfs     f17, FP_17(r3)
230
        lfs     f18, FP_18(r3)
231
        lfs     f19, FP_19(r3)
232
        lfs     f20, FP_20(r3)
233
        lfs     f21, FP_21(r3)
234
        lfs     f22, FP_22(r3)
235
        lfs     f23, FP_23(r3)
236
        lfs     f24, FP_24(r3)
237
        lfs     f25, FP_25(r3)
238
        lfs     f26, FP_26(r3)
239
        lfs     f27, FP_27(r3)
240
        lfs     f28, FP_28(r3)
241
        lfs     f29, FP_29(r3)
242
        lfs     f30, FP_30(r3)
243
        lfs     f31, FP_31(r3)
244
#endif
245
        blr
246
 
247
 
248
/*  _CPU_Context_switch
249
 *
250
 *  This routine performs a normal non-FP context switch.
251
 */
252
        ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
253
        PUBLIC_PROC (_CPU_Context_switch)
254
PROC (_CPU_Context_switch):
255
        sync
256
        isync
257
        /* This assumes that all the registers are in the given order */
258
        li      r5, 32
259
        addi    r3,r3,-4
260
#if ( PPC_USE_DATA_CACHE )
261
        dcbz    r5, r3
262
#endif
263
        stw     r1, GP_1+4(r3)
264
        stw     r2, GP_2+4(r3)
265
#if (PPC_USE_MULTIPLE == 1)
266
        addi    r3, r3, GP_18+4
267
#if ( PPC_USE_DATA_CACHE )
268
        dcbz    r5, r3
269
#endif
270
        stmw    r13, GP_13-GP_18(r3)
271
#else
272
        stw     r13, GP_13+4(r3)
273
        stw     r14, GP_14+4(r3)
274
        stw     r15, GP_15+4(r3)
275
        stw     r16, GP_16+4(r3)
276
        stw     r17, GP_17+4(r3)
277
        stwu    r18, GP_18+4(r3)
278
#if ( PPC_USE_DATA_CACHE )
279
        dcbz    r5, r3
280
#endif
281
        stw     r19, GP_19-GP_18(r3)
282
        stw     r20, GP_20-GP_18(r3)
283
        stw     r21, GP_21-GP_18(r3)
284
        stw     r22, GP_22-GP_18(r3)
285
        stw     r23, GP_23-GP_18(r3)
286
        stw     r24, GP_24-GP_18(r3)
287
        stw     r25, GP_25-GP_18(r3)
288
        stw     r26, GP_26-GP_18(r3)
289
        stw     r27, GP_27-GP_18(r3)
290
        stw     r28, GP_28-GP_18(r3)
291
        stw     r29, GP_29-GP_18(r3)
292
        stw     r30, GP_30-GP_18(r3)
293
        stw     r31, GP_31-GP_18(r3)
294
#endif
295
#if ( PPC_USE_DATA_CACHE )
296
        dcbt    r0, r4
297
#endif
298
        mfcr    r6
299
        stw     r6, GP_CR-GP_18(r3)
300
        mflr    r7
301
        stw     r7, GP_PC-GP_18(r3)
302
        mfmsr   r8
303
        stw     r8, GP_MSR-GP_18(r3)
304
 
305
#if ( PPC_USE_DATA_CACHE )
306
        dcbt    r5, r4
307
#endif
308
        lwz     r1, GP_1(r4)
309
        lwz     r2, GP_2(r4)
310
#if (PPC_USE_MULTIPLE == 1)
311
        addi    r4, r4, GP_19
312
#if ( PPC_USE_DATA_CACHE )
313
        dcbt    r5, r4
314
#endif
315
        lmw     r13, GP_13-GP_19(r4)
316
#else
317
        lwz     r13, GP_13(r4)
318
        lwz     r14, GP_14(r4)
319
        lwz     r15, GP_15(r4)
320
        lwz     r16, GP_16(r4)
321
        lwz     r17, GP_17(r4)
322
        lwz     r18, GP_18(r4)
323
        lwzu    r19, GP_19(r4)
324
#if ( PPC_USE_DATA_CACHE )
325
        dcbt    r5, r4
326
#endif
327
        lwz     r20, GP_20-GP_19(r4)
328
        lwz     r21, GP_21-GP_19(r4)
329
        lwz     r22, GP_22-GP_19(r4)
330
        lwz     r23, GP_23-GP_19(r4)
331
        lwz     r24, GP_24-GP_19(r4)
332
        lwz     r25, GP_25-GP_19(r4)
333
        lwz     r26, GP_26-GP_19(r4)
334
        lwz     r27, GP_27-GP_19(r4)
335
        lwz     r28, GP_28-GP_19(r4)
336
        lwz     r29, GP_29-GP_19(r4)
337
        lwz     r30, GP_30-GP_19(r4)
338
        lwz     r31, GP_31-GP_19(r4)
339
#endif
340
        lwz     r6, GP_CR-GP_19(r4)
341
        lwz     r7, GP_PC-GP_19(r4)
342
        lwz     r8, GP_MSR-GP_19(r4)
343
        mtcrf   255, r6
344
        mtlr    r7
345
        mtmsr   r8
346
 
347
        blr
348
 
349
/*
350
 *  _CPU_Context_restore
351
 *
352
 *  This routine is generallu used only to restart self in an
353
 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
354
 *
355
 *  NOTE: May be unnecessary to reload some registers.
356
 */
357
/*
358
 * ACB: Don't worry about cache optimisation here - this is not THAT critical.
359
 */
360
        ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
361
        PUBLIC_PROC (_CPU_Context_restore)
362
PROC (_CPU_Context_restore):
363
        lwz     r5, GP_CR(r3)
364
        lwz     r6, GP_PC(r3)
365
        lwz     r7, GP_MSR(r3)
366
        mtcrf   255, r5
367
        mtlr    r6
368
        mtmsr   r7
369
        lwz     r1, GP_1(r3)
370
        lwz     r2, GP_2(r3)
371
#if (PPC_USE_MULTIPLE == 1)
372
        lmw     r13, GP_13(r3)
373
#else
374
        lwz     r13, GP_13(r3)
375
        lwz     r14, GP_14(r3)
376
        lwz     r15, GP_15(r3)
377
        lwz     r16, GP_16(r3)
378
        lwz     r17, GP_17(r3)
379
        lwz     r18, GP_18(r3)
380
        lwz     r19, GP_19(r3)
381
        lwz     r20, GP_20(r3)
382
        lwz     r21, GP_21(r3)
383
        lwz     r22, GP_22(r3)
384
        lwz     r23, GP_23(r3)
385
        lwz     r24, GP_24(r3)
386
        lwz     r25, GP_25(r3)
387
        lwz     r26, GP_26(r3)
388
        lwz     r27, GP_27(r3)
389
        lwz     r28, GP_28(r3)
390
        lwz     r29, GP_29(r3)
391
        lwz     r30, GP_30(r3)
392
        lwz     r31, GP_31(r3)
393
#endif
394
 
395
        blr
396
 

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