OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [rtems/] [c/] [src/] [lib/] [include/] [motorola/] [mc68230.h] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 158 chris
/*
2
 * mc68230.h -- Low level support code for the Motorola 68230 Parallel
3
 *              Interface/Timer (PIT)
4
 *
5
 * Modified by Doug McBride, Colorado Space Grant College
6
 *
7
 * Format taken partly from RTEMS code and mostly from Motorola IDP user's
8
 * manual.  RTEMS copyright information below.
9
 *
10
 *  COPYRIGHT (c) 1989-1999.
11
 *  On-Line Applications Research Corporation (OAR).
12
 *
13
 *  The license and distribution terms for this file may be
14
 *  found in the file LICENSE in this distribution or at
15
 *  http://www.OARcorp.com/rtems/license.html.
16
 *
17 208 chris
 *  $Id: mc68230.h,v 1.2 2001-09-27 11:59:35 chris Exp $
18 158 chris
 */
19
 
20
#ifndef __MC68230_H__
21
#define __MC68230_H__
22
 
23
/* Some Motorola IDP User manual defines: */
24
#define PIT_ADDR        0x00c01003              /* base address of the PIT */
25
#define REGOFF  0x04                            /* Difference between addresses */
26
#define VECT    64
27
#define H1VECT  0x00
28
#define H2VECT  0x01
29
#define H3VECT  0x02
30
#define H4VECT  0x03
31
 
32
/*
33
 * mc68230 register offsets
34
 */
35
#define PGCR    0x00
36
#define PSRR    1*REGOFF
37
#define PADDR   2*REGOFF
38
#define PBDDR   3*REGOFF
39
#define PCDDR   4*REGOFF
40
#define PIVR    5*REGOFF
41
#define PACR    6*REGOFF
42
#define PBCR    7*REGOFF
43
#define PADR    8*REGOFF
44
#define PBDR    9*REGOFF
45
#define PAAR    10*REGOFF
46
#define PBAR    11*REGOFF
47
#define PCDR    12*REGOFF
48
#define PITSR   13*REGOFF
49
#define TCR             16*REGOFF
50
#define TIVR    17*REGOFF
51
#define CPRH    19*REGOFF
52
#define CPRM    20*REGOFF
53
#define CPRL    21*REGOFF
54
#define CNTRH   23*REGOFF
55
#define CNTRM   24*REGOFF
56
#define CNTRL   25*REGOFF
57
#define TSR             26*REGOFF
58
 
59
/* Some RTEMS style defines: */
60
#ifndef VOL8
61
#define VOL8( ptr )   ((volatile rtems_unsigned8 *)(ptr))
62
#endif
63
 
64
#define MC68230_WRITE( reg, data ) \
65
   *(VOL8(PIT_ADDR+reg)) = (data)
66
 
67
#define MC68230_READ( reg, data ) \
68
   (data) = *(VOL8(PIT_ADDR+reg))
69
 
70
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.