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1026 |
ivang |
/*
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* VEGA PLUS registers declaration
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*
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* Copyright (c) 2000 Canon Research France SA.
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* Emmanuel Raguet, mailto:raguet@crf.canon.fr
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*
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* The license and distribution terms for this file may be
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* found in found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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*/
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#ifndef __LMREGS_H__
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#define __LMREGS_H__
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/*
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* VARIABLE DECLARATION
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******************************************************************************
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*/
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/* register area size */
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#define LM_REG_AREA_SIZ (0x4000/4)
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/*** Register mapping : defined by indexes in an array ***/
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/*** NOTE : only 1 register every 4 byte address location (+ some holes) */
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#ifndef __asm__
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extern volatile unsigned long *Regs; /* Chip registers */
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#endif
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/******************************************************************************
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* RADIO CONTROLLER BLOCK 0x0C00 - 0x0FFF *
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******************************************************************************
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*/
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#define RC_BASE 0xC00
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#define RCCNTL ((RC_BASE+0x00)/4)
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#define RCIOCNTL0 ((RC_BASE+0x04)/4)
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#define RCIOCNTL1 ((RC_BASE+0x08)/4)
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#define SYNTCNTL0 ((RC_BASE+0x0C)/4)
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#define SYNTCNTL1 ((RC_BASE+0x10)/4)
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#define SYNTCNTL2 ((RC_BASE+0x14)/4)
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#define SYNTFCNTL ((RC_BASE+0x18)/4)
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#define SYNTPCNTL ((RC_BASE+0x1C)/4)
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#define RSSICNTL ((RC_BASE+0x20)/4)
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#define RSSIBASEL ((RC_BASE+0x24)/4)
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#define RSSIBASEH ((RC_BASE+0x28)/4)
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#define CURRSSI ((RC_BASE+0x2C)/4)
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#define RFSCAN ((RC_BASE+0x30)/4)
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#define CURRF ((RC_BASE+0x34)/4)
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#define CURRSSIA ((RC_BASE+0x38)/4)
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#define CURRSSIB ((RC_BASE+0x3C)/4)
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#define CURRSSIAB ((RC_BASE+0x40)/4)
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#define ADCDATAL ((RC_BASE+0x44)/4)
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#define ADCDATAH ((RC_BASE+0x48)/4)
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#define SLICECNTL ((RC_BASE+0x4C)/4)
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#define RCIOCNTL2 ((RC_BASE+0x50)/4)
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#define RCIOCNTL3 ((RC_BASE+0x54)/4)
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#define ADCREF1L ((RC_BASE+0x58)/4)
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#define ADCREF1H ((RC_BASE+0x5C)/4)
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#define ADCREF2L ((RC_BASE+0x60)/4)
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#define ADCREF2H ((RC_BASE+0x64)/4)
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#define ADCCNTL1 ((RC_BASE+0x68)/4)
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#define ADCCNTL2 ((RC_BASE+0x6C)/4)
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#define TESTREG ((RC_BASE+0x70)/4)
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#define SYNTLCNTL ((RC_BASE+0x74)/4)
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#define SYNTCNTL3 ((RC_BASE+0x78)/4)
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#define ADCPERIOD ((RC_BASE+0x7C)/4)
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#define SYNTIOCNTL ((RC_BASE+0x80)/4) /* added 30/08/99 */
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/* modified 30/08/99 by LHT */
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#define SHAPE0 ((RC_BASE+0x100)/4) /* previously 0x80 */
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#define SHAPE1 ((RC_BASE+0x104)/4)
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#define SHAPE2 ((RC_BASE+0x108)/4)
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#define SHAPE3 ((RC_BASE+0x10C)/4)
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#define SHAPE4 ((RC_BASE+0x110)/4)
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#define SHAPE5 ((RC_BASE+0x114)/4)
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#define SHAPE6 ((RC_BASE+0x118)/4)
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#define SHAPE7 ((RC_BASE+0x11C)/4)
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#define SHAPE8 ((RC_BASE+0x120)/4)
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#define SHAPE9 ((RC_BASE+0x124)/4)
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#define SHAPE10 ((RC_BASE+0x128)/4)
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#define SHAPE11 ((RC_BASE+0x12C)/4)
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#define SHAPE12 ((RC_BASE+0x130)/4)
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#define SHAPERMID ((RC_BASE+0x134)/4)
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#define SHAPERCNTL ((RC_BASE+0x138)/4)
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#define CURSHAPE ((RC_BASE+0x13C)/4)
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/** PLP BLOCK 0x1400 - 0x17FF */
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#define PLP_BASE 0x1400
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#define DCNTL0 ((PLP_BASE+0x00)/4)
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#define DCNTL1 ((PLP_BASE+0x04)/4)
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#define SYNC0 ((PLP_BASE+0x08)/4)
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#define SYNC1 ((PLP_BASE+0x0C)/4)
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#define RXSTARTDL ((PLP_BASE+0x10)/4)
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#define TXSTARTDL ((PLP_BASE+0x14)/4)
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#define RXSTOPDL ((PLP_BASE+0x1C)/4)
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#define RXSYNCT ((PLP_BASE+0x20)/4)
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#define HALF_TXSLOT ((PLP_BASE+0x24)/4)
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#define SCB_NUMBER ((PLP_BASE+0x28)/4)
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#define SCB_OPPNUMBER ((PLP_BASE+0x2C)/4)
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#define TXFRAME ((PLP_BASE+0x40)/4)
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#define MSLTPTR ((PLP_BASE+0x44)/4)
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#define CLOCK_CORR ((PLP_BASE+0x48)/4)
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#define PRESYNC ((PLP_BASE+0x4C)/4)
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#define PLPFINE ((PLP_BASE+0x50)/4)
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#define PLPINDEL ((PLP_BASE+0x54)/4)
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#define TXRXSKW ((PLP_BASE+0x58)/4)
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#define PLPALIN ((PLP_BASE+0x5C)/4)
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#define SUSPRFCNTL ((PLP_BASE+0x60)/4)
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#define SUSPCNTL ((PLP_BASE+0x64)/4)
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#define SUSPFC ((PLP_BASE+0x68)/4)
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#define TSTCNTL ((PLP_BASE+0x6C)/4)
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#define TSTDST ((PLP_BASE+0x70)/4)
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#define TSTTXD ((PLP_BASE+0x74)/4)
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#define TSTRXD ((PLP_BASE+0x78)/4)
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#define PLPID ((PLP_BASE+0x7C)/4)
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/** ENCRYPTION ENGINE 0x1800 - 0x1BFF */
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#define EE_BASE 0x1800
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#define EECNTL ((EE_BASE+0x00)/4)
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#define EEBASEL ((EE_BASE+0x08)/4)
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#define EEBASEH ((EE_BASE+0x0C)/4)
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#define MFL ((EE_BASE+0x10)/4)
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#define MFM ((EE_BASE+0x14)/4)
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#define MFH ((EE_BASE+0x18)/4)
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/** TELEPHONE ANSWERING DEVICE 0x1C00 - 0x1FFF */
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#define TAD_BASE 0x1C00
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#define TADCNTL ((TAD_BASE+0x00)/4)
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#define TADCODE1 ((TAD_BASE+0x04)/4)
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#define TADCODE2 ((TAD_BASE+0x08)/4)
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#define TADCODE3 ((TAD_BASE+0x0C)/4)
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#define TADSTAT ((TAD_BASE+0x10)/4)
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#define TADADDRL ((TAD_BASE+0x14)/4)
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#define TADADDRM ((TAD_BASE+0x18)/4)
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#define TADADDRH ((TAD_BASE+0x1C)/4)
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#define TADLEN ((TAD_BASE+0x20)/4)
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#define TADAUXDAT1 ((TAD_BASE+0x24)/4)
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#define TADAUXDAT2 ((TAD_BASE+0x28)/4)
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#define TADSHMEML ((TAD_BASE+0x2C)/4)
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#define TADSHMEMH ((TAD_BASE+0x30)/4)
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#define TADCMD ((TAD_BASE+0x34)/4)
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/** VOICE INTERFACE BLOCK 0x2000 - 0x23FF */
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#define PAINT_BASE 0x2000
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#define PAINTCNTL ((PAINT_BASE+0x00)/4)
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#define PAINTPLLCNTL ((PAINT_BASE+0x08)/4)
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#define PAINTPLLSTAT ((PAINT_BASE+0x0C)/4)
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#define VBAFECNTL ((PAINT_BASE+0x10)/4)
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#define VBAFEAMP ((PAINT_BASE+0x14)/4)
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#define VBAFEPREAMP ((PAINT_BASE+0x18)/4)
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#define PCMAUX ((PAINT_BASE+0x1C)/4)
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#define PCM0RX ((PAINT_BASE+0x20)/4)
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#define PCM0TX ((PAINT_BASE+0x24)/4)
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#define PCM1RX ((PAINT_BASE+0x28)/4)
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#define PCM1TX ((PAINT_BASE+0x2C)/4)
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#define ADPCM0RX ((PAINT_BASE+0x30)/4)
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#define ADPCM0TX ((PAINT_BASE+0x34)/4)
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#define ADPCM1RX ((PAINT_BASE+0x38)/4)
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#define ADPCM1TX ((PAINT_BASE+0x3C)/4)
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#define MPDCNTL ((PAINT_BASE+0x40)/4)
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#define MPDREADY ((PAINT_BASE+0x44)/4)
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#define MPDABS ((PAINT_BASE+0x48)/4)
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#define MPDS1 ((PAINT_BASE+0x4C)/4)
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#define MPDS2 ((PAINT_BASE+0x50)/4)
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#define HPPCMCNTL ((PAINT_BASE+0x60)/4)
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#define HPOUT ((PAINT_BASE+0x64)/4)
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#define HPIN ((PAINT_BASE+0x68)/4)
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#define PAINTBASE0 ((PAINT_BASE+0x70)/4)
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#define PAINTBASE1 ((PAINT_BASE+0x74)/4)
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#define G726AI0 ((PAINT_BASE+0x80)/4)
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#define G726AI1 ((PAINT_BASE+0x84)/4)
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#define G726GAIN0 ((PAINT_BASE+0x88)/4)
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#define G726GAIN1 ((PAINT_BASE+0x8C)/4)
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#define G726VOL ((PAINT_BASE+0x90)/4)
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#define G726GST ((PAINT_BASE+0x94)/4)
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#define G726CNTL0 ((PAINT_BASE+0x98)/4)
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#define G726CNTL1 ((PAINT_BASE+0x9C)/4)
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#define G726CHANNEL ((PAINT_BASE+0xA0)/4)
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#define G726CHANENB ((PAINT_BASE+0xA4)/4)
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/** GENERAL REGISTERS BLOCK 0x2800 - 0x2CFF */
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#define MISC_BASE 0x2800
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#define CHIPID ((MISC_BASE+0x00)/4)
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#define DEVICEID ((MISC_BASE+0x04)/4)
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#define IOACNTL ((MISC_BASE+0x10)/4)
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#define IOADATA ((MISC_BASE+0x18)/4)
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#define IOBCNTL ((MISC_BASE+0x20)/4)
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#define IOBDATA ((MISC_BASE+0x28)/4)
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#define IOCCNTL1 ((MISC_BASE+0x30)/4)
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#define IOCCNTL2 ((MISC_BASE+0x34)/4)
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#define IOCDATA ((MISC_BASE+0x38)/4)
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#define IODCNTL1 ((MISC_BASE+0x40)/4)
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#define IODCNTL2 ((MISC_BASE+0x44)/4)
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#define IODDATA ((MISC_BASE+0x48)/4)
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#define IOECNTL1 ((MISC_BASE+0x50)/4)
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#define IOECNTL2 ((MISC_BASE+0x54)/4)
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#define IOEDATA ((MISC_BASE+0x58)/4)
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#define IOFCNTL ((MISC_BASE+0x60)/4)
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#define IOFDATA ((MISC_BASE+0x68)/4)
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#define IOGCNTL ((MISC_BASE+0x70)/4)
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#define IOGDATA ((MISC_BASE+0x78)/4)
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#define IOHCNTL ((MISC_BASE+0x80)/4)
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#define IOHDATA ((MISC_BASE+0x88)/4)
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#define RINGCNTL ((MISC_BASE+0x90)/4)
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#define RINGFREQ ((MISC_BASE+0x94)/4)
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#define RSCNTL ((MISC_BASE+0xA0)/4)
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/*#ifndef PRODUCT_VERSION*/
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#define RSRXD ((MISC_BASE+0xA4)/4)
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#define RSTXD ((MISC_BASE+0xA8)/4)
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/*#endif*/
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#define PWMCNTL ((MISC_BASE+0xB0)/4)
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#define PWMTIMER0 ((MISC_BASE+0xB4)/4)
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#define PWMTIMER1 ((MISC_BASE+0xB8)/4)
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#define LCDEECNTL1 ((MISC_BASE+0xC0)/4)
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#define LCDEECNTL2 ((MISC_BASE+0xC4)/4)
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#define LCDEEDAIN ((MISC_BASE+0xC8)/4)
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#define LCDEEDAOUT ((MISC_BASE+0xCC)/4)
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#define KEYROW ((MISC_BASE+0xE0)/4)
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#define KEYCOL ((MISC_BASE+0xE4)/4)
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#define KEYDEBOUNCE ((MISC_BASE+0xE8)/4)
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#define DIAGCNTL1 ((MISC_BASE+0xEC)/4)
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#define DIAGCNTL2 ((MISC_BASE+0xF0)/4)
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#define CLKCNTL ((MISC_BASE+0xF4)/4)
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#define OSCCOR ((MISC_BASE+0xF8)/4)
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| 238 |
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/* PRODUCT_VERSION */
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/* Added 30/08/99 : New Control register for UART control */
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#define UART_BASE 0x3000
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#define RSRBR ((UART_BASE+0x00)/4)
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#define RSTHR ((UART_BASE+0x00)/4)
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| 243 |
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#define RSIER ((UART_BASE+0x04)/4)
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| 244 |
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#define RSIIR ((UART_BASE+0x08)/4)
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| 245 |
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#define RSFCR ((UART_BASE+0x08)/4)
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| 246 |
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#define RSLCR ((UART_BASE+0x0C)/4)
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| 247 |
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#define RSLSR ((UART_BASE+0x14)/4)
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| 248 |
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#define RSDLL ((UART_BASE+0x00)/4)
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| 249 |
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#define RSDLH ((UART_BASE+0x04)/4)
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| 250 |
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#define RSCNT ((UART_BASE+0x20)/4)
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| 251 |
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/*PRODUCT_VERSION*/
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| 252 |
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| 253 |
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| 254 |
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/** THUMB and INTERFACES BLOCK 0x3400 - 0x4FFF */
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| 255 |
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| 256 |
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#define TIM_BASE 0x3400
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| 257 |
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#define WDCNTL ((TIM_BASE+0x00)/4)
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#define TIMERLOAD0 ((TIM_BASE+0x80)/4)
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#define TIMER0 ((TIM_BASE+0x8C)/4)
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#define TIMERCNTL0 ((TIM_BASE+0x98)/4)
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#define TIMERLOAD1 ((TIM_BASE+0xA0)/4)
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#define TIMER1 ((TIM_BASE+0xAC)/4)
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#define TIMERCNTL1 ((TIM_BASE+0xB8)/4)
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| 264 |
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| 265 |
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#define INTC_BASE 0x3800
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#define INTMASK ((INTC_BASE+0x20)/4)
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| 267 |
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#define INTSTAT ((INTC_BASE+0x24)/4)
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| 268 |
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#define INTACK ((INTC_BASE+0x24)/4)
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| 269 |
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#define INTACK2 ((INTC_BASE+0x24))
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| 270 |
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#define INTIS ((INTC_BASE+0x28)/4)
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| 271 |
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#define INTIS2 ((INTC_BASE+0x28))
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|
|
#define INTHPAI ((INTC_BASE+0x00)/4)
|
| 273 |
|
|
#define INTHPAI2 ((INTC_BASE+0x00))
|
| 274 |
|
|
#define INTLEVEL ((INTC_BASE+0x04)/4)
|
| 275 |
|
|
#define INTEOI ((INTC_BASE+0x08)/4)
|
| 276 |
|
|
#define INTEOI2 ((INTC_BASE+0x08))
|
| 277 |
|
|
#define INTMASKALL ((INTC_BASE+0x0C)/4)
|
| 278 |
|
|
#define INTTAB ((INTC_BASE+0x10)/4)
|
| 279 |
|
|
#define INTCNTL0 ((INTC_BASE+0x80)/4)
|
| 280 |
|
|
#define INTCNTL1 ((INTC_BASE+0x84)/4)
|
| 281 |
|
|
#define INTCNTL2 ((INTC_BASE+0x88)/4)
|
| 282 |
|
|
#define INTCNTL3 ((INTC_BASE+0x8C)/4)
|
| 283 |
|
|
#define INTCNTL4 ((INTC_BASE+0x90)/4)
|
| 284 |
|
|
#define INTCNTL5 ((INTC_BASE+0x94)/4)
|
| 285 |
|
|
#define INTCNTL6 ((INTC_BASE+0x98)/4)
|
| 286 |
|
|
#define INTCNTL7 ((INTC_BASE+0x9C)/4)
|
| 287 |
|
|
#define INTCNTL8 ((INTC_BASE+0xA0)/4)
|
| 288 |
|
|
#define INTCNTL9 ((INTC_BASE+0xA4)/4)
|
| 289 |
|
|
#define INTCNTL10 ((INTC_BASE+0xA8)/4)
|
| 290 |
|
|
#define INTCNTL11 ((INTC_BASE+0xAC)/4)
|
| 291 |
|
|
#define INTCNTL12 ((INTC_BASE+0xB0)/4)
|
| 292 |
|
|
#define INTCNTL13 ((INTC_BASE+0xB4)/4)
|
| 293 |
|
|
#define INTCNTL14 ((INTC_BASE+0xB8)/4)
|
| 294 |
|
|
#define INTCNTL15 ((INTC_BASE+0xBC)/4)
|
| 295 |
|
|
#define INTGCNTL ((INTC_BASE+0x7C)/4)
|
| 296 |
|
|
|
| 297 |
|
|
/* these "define" are used for the asm code of int managment */
|
| 298 |
|
|
#define INTPHAI3 0xF3800
|
| 299 |
|
|
#define INTSTAT3 0xF3824
|
| 300 |
|
|
#define INTIS3 0xF3828
|
| 301 |
|
|
#define INTACK3 0xF3824
|
| 302 |
|
|
#define INTEOI3 0xF3808
|
| 303 |
|
|
|
| 304 |
|
|
#define TI_BASE 0x3C00
|
| 305 |
|
|
#define CSCNTL0_0 ((TI_BASE+0x00)/4)
|
| 306 |
|
|
#define CSCNTL0_1 ((TI_BASE+0x04)/4)
|
| 307 |
|
|
#define CSCNTL0_2 ((TI_BASE+0x08)/4)
|
| 308 |
|
|
#define CSCNTL0_3 ((TI_BASE+0x0C)/4)
|
| 309 |
|
|
#define CSCNTL0_4 ((TI_BASE+0x10)/4)
|
| 310 |
|
|
#define CSCNTL0_5 ((TI_BASE+0x14)/4)
|
| 311 |
|
|
#define CSCNTL0_6 ((TI_BASE+0x18)/4)
|
| 312 |
|
|
#define CSCNTL1_0 ((TI_BASE+0x20)/4)
|
| 313 |
|
|
#define CSCNTL1_1 ((TI_BASE+0x24)/4)
|
| 314 |
|
|
#define CSCNTL1_2 ((TI_BASE+0x28)/4)
|
| 315 |
|
|
#define CSCNTL1_3 ((TI_BASE+0x2C)/4)
|
| 316 |
|
|
#define CSCNTL1_4 ((TI_BASE+0x30)/4)
|
| 317 |
|
|
#define CSCNTL1_5 ((TI_BASE+0x34)/4)
|
| 318 |
|
|
#define CSCNTL1_6 ((TI_BASE+0x38)/4)
|
| 319 |
|
|
#define CSGCNTL ((TI_BASE+0x40)/4)
|
| 320 |
|
|
#define MUXADCNTL ((TI_BASE+0x48)/4)
|
| 321 |
|
|
#define PORTCNTL ((TI_BASE+0x60)/4)
|
| 322 |
|
|
#define DCC ((TI_BASE+0x78)/4)
|
| 323 |
|
|
#define BRK0 ((TI_BASE+0x100)/4)
|
| 324 |
|
|
#define BRK1 ((TI_BASE+0x104)/4)
|
| 325 |
|
|
#define BRK2 ((TI_BASE+0x108)/4)
|
| 326 |
|
|
#define BRK3 ((TI_BASE+0x10C)/4)
|
| 327 |
|
|
#define BRK4 ((TI_BASE+0x110)/4)
|
| 328 |
|
|
#define BRK5 ((TI_BASE+0x114)/4)
|
| 329 |
|
|
#define BRK6 ((TI_BASE+0x118)/4)
|
| 330 |
|
|
#define BRK7 ((TI_BASE+0x11C)/4)
|
| 331 |
|
|
#define BRKMSK ((TI_BASE+0x140)/4)
|
| 332 |
|
|
#define BRKSTAT ((TI_BASE+0x144)/4)
|
| 333 |
|
|
#define SLEEPTIMER ((TI_BASE+0x204)/4)
|
| 334 |
|
|
#define SLEEPCNTL ((TI_BASE+0x208)/4)
|
| 335 |
|
|
|
| 336 |
|
|
|
| 337 |
|
|
|
| 338 |
|
|
/******************************************************************************
|
| 339 |
|
|
* BIT MASKS for Chip registers
|
| 340 |
|
|
******************************************************************************
|
| 341 |
|
|
*/
|
| 342 |
|
|
|
| 343 |
|
|
/** TELEPHONE ANSWERING DEVICE BLOCK (TAD) */
|
| 344 |
|
|
|
| 345 |
|
|
/* TADCNTL register */
|
| 346 |
|
|
#define IRQCNTL 0x01
|
| 347 |
|
|
#define CE_CNTL 0x02
|
| 348 |
|
|
#define MSKTAD 0x04
|
| 349 |
|
|
#define TAD_PAD_ENB 0x40
|
| 350 |
|
|
#define TADENB 0x80
|
| 351 |
|
|
|
| 352 |
|
|
/* TADSTAT register */
|
| 353 |
|
|
#define RBN 0x01
|
| 354 |
|
|
#define TRANSFER 0x02
|
| 355 |
|
|
#define ACTIVE 0x04
|
| 356 |
|
|
|
| 357 |
|
|
/* TADCMD register */
|
| 358 |
|
|
#define MSK_TADCMD 0x0F /* Mask on TADCMD */
|
| 359 |
|
|
#define CONTINUE 0x10
|
| 360 |
|
|
|
| 361 |
|
|
|
| 362 |
|
|
|
| 363 |
|
|
/** RADIO CONTROLER BLOCK (RC3) */
|
| 364 |
|
|
|
| 365 |
|
|
/* SLICECNTL register */
|
| 366 |
|
|
#define MSK_SLICEDL 0x07 /* Mask on SLICEDL field */
|
| 367 |
|
|
#define MSK_SCNTL 0x18 /* Mask on SCNTL field */
|
| 368 |
|
|
#define SELOCK 0x20
|
| 369 |
|
|
#define MSK_MUXSLICE 0xC0
|
| 370 |
|
|
|
| 371 |
|
|
/* RCIOCNTL0 register */
|
| 372 |
|
|
#define D2SBYPASS 0x01
|
| 373 |
|
|
#define DRBYPASS 0x02
|
| 374 |
|
|
#define RXINV 0x04
|
| 375 |
|
|
#define SELANT 0x10
|
| 376 |
|
|
#define ANT 0x20
|
| 377 |
|
|
#define LDINV0 0x40
|
| 378 |
|
|
#define LDINV1 0x80
|
| 379 |
|
|
|
| 380 |
|
|
/* RCIOCNTL1 register */
|
| 381 |
|
|
#define MSK_GPO 0x0F /* Mask on GPO field */
|
| 382 |
|
|
#define P00ENB 0x10
|
| 383 |
|
|
#define ABORT 0x20
|
| 384 |
|
|
#define TXIO 0x40
|
| 385 |
|
|
#define TXINV 0x80
|
| 386 |
|
|
|
| 387 |
|
|
/* RCIOCNTL2 register */
|
| 388 |
|
|
#define SELRFCLK 0x01
|
| 389 |
|
|
#define SELRXPWR 0x02
|
| 390 |
|
|
#define TXPWRINV 0x04
|
| 391 |
|
|
#define RXPWRINV 0x08
|
| 392 |
|
|
#define SYNTHPWR0INV 0x10
|
| 393 |
|
|
#define SYNTHPWR1INV 0x20
|
| 394 |
|
|
#define TXDRONINV 0x40
|
| 395 |
|
|
#define SELTXDRON 0x80
|
| 396 |
|
|
|
| 397 |
|
|
/* RCIOCNTL3 register */
|
| 398 |
|
|
#define D2SMODE 0x01
|
| 399 |
|
|
#define DRCNTL 0x02
|
| 400 |
|
|
#define MSK_SELGPO 0x0C /* Mask on SELGPO field */
|
| 401 |
|
|
#define MSK_SUSPANT 0x30 /* Mask on SUSO/ANT field */
|
| 402 |
|
|
|
| 403 |
|
|
/* SHAPERCNTL register */
|
| 404 |
|
|
#define INV 0x01
|
| 405 |
|
|
#define MID 0x02
|
| 406 |
|
|
#define PWRDWN 0x04
|
| 407 |
|
|
#define DACENB 0x80
|
| 408 |
|
|
|
| 409 |
|
|
/* SYNTFCNTL register */
|
| 410 |
|
|
#define SYNT_FREQ 0x80
|
| 411 |
|
|
|
| 412 |
|
|
/* SYNTCNTL0 register */
|
| 413 |
|
|
#define PWRFREQ 0x01
|
| 414 |
|
|
#define CLKPHASE 0x08
|
| 415 |
|
|
#define LETYPE 0x10
|
| 416 |
|
|
#define RPIPEON 0x20
|
| 417 |
|
|
#define PWRSGN 0x40
|
| 418 |
|
|
#define OUTLOCK 0x80
|
| 419 |
|
|
|
| 420 |
|
|
/* SYNTCNTL1 register */
|
| 421 |
|
|
#define SLE0 0x01
|
| 422 |
|
|
#define SLE1 0x02
|
| 423 |
|
|
#define SLE2 0x04
|
| 424 |
|
|
#define LEMODE 0x08
|
| 425 |
|
|
#define LESEL 0x10
|
| 426 |
|
|
#define SCLK 0x20
|
| 427 |
|
|
#define SDATA 0x40
|
| 428 |
|
|
#define HPMODE_SYNT 0x80
|
| 429 |
|
|
|
| 430 |
|
|
/* SYNTCNTL2 register */
|
| 431 |
|
|
#define START_DONE 0x80
|
| 432 |
|
|
#define MSK_N 0x03 /* Mask on N field */
|
| 433 |
|
|
|
| 434 |
|
|
/* SYNTCNTL3 register */
|
| 435 |
|
|
#define RXPWRDNSEN 0x01
|
| 436 |
|
|
#define RXPWRUNSEN 0x02
|
| 437 |
|
|
#define TXPWRDNSEN 0x04
|
| 438 |
|
|
#define TXPWRUNSEN 0x08
|
| 439 |
|
|
#define SEQCNTL 0x10
|
| 440 |
|
|
#define ALIGN 0x20
|
| 441 |
|
|
#define PLLWORD 0x40
|
| 442 |
|
|
#define PRESEQ 0x80
|
| 443 |
|
|
|
| 444 |
|
|
/* RFSCAN register */
|
| 445 |
|
|
#define MSK_RF 0x0F /* Mask on RF field */
|
| 446 |
|
|
#define RFMAX 0x80
|
| 447 |
|
|
|
| 448 |
|
|
/* RSSIRANGE register */
|
| 449 |
|
|
#define MSK_VREFP 0x03 /* Mask on VREFP field */
|
| 450 |
|
|
#define MSK_VREFN 0x0C /* Mask on VREFN field */
|
| 451 |
|
|
|
| 452 |
|
|
/* RSSICNTL register */
|
| 453 |
|
|
#define MSK_MODE_RSSI 0x03 /* Mask on MODE field */
|
| 454 |
|
|
#define MARKFF 0x04
|
| 455 |
|
|
#define TXMARK 0x08
|
| 456 |
|
|
#define ALL_RSSI 0x10
|
| 457 |
|
|
#define RSSIACT 0x20
|
| 458 |
|
|
#define RSSIDIS 0x40
|
| 459 |
|
|
#define RSSIENB 0x80
|
| 460 |
|
|
|
| 461 |
|
|
/* RCCNTL register */
|
| 462 |
|
|
#define RCCNTL_ENABLE 0x80
|
| 463 |
|
|
|
| 464 |
|
|
|
| 465 |
|
|
/* ADCCNTL1 register */
|
| 466 |
|
|
#define ADCSTART 0x80
|
| 467 |
|
|
#define SCAN 0x40
|
| 468 |
|
|
#define ADCENB 0x80
|
| 469 |
|
|
#define MSK_ADCSEL 0x07
|
| 470 |
|
|
|
| 471 |
|
|
/* ADCCNTL2 register */
|
| 472 |
|
|
#define ADCOVER1 0x01
|
| 473 |
|
|
#define ADCOVER2 0x02
|
| 474 |
|
|
#define ADCDWN1 0x04
|
| 475 |
|
|
#define ADCDWN2 0x08
|
| 476 |
|
|
|
| 477 |
|
|
|
| 478 |
|
|
|
| 479 |
|
|
/** PLP BLOCK */
|
| 480 |
|
|
|
| 481 |
|
|
/* DCNTL0 register */
|
| 482 |
|
|
#define TMUXINT 0x01
|
| 483 |
|
|
#define MUTEIP 0x02
|
| 484 |
|
|
#define Q1Q2_PLP 0x04
|
| 485 |
|
|
#define TRANSP 0x08
|
| 486 |
|
|
#define CRYPTALL 0x10
|
| 487 |
|
|
#define TXSENSE 0x20
|
| 488 |
|
|
#define ZACT 0x40
|
| 489 |
|
|
#define PLPENB 0x80
|
| 490 |
|
|
|
| 491 |
|
|
/* DCNTL1 register */
|
| 492 |
|
|
#define ONECT 0x10
|
| 493 |
|
|
#define WOMODE 0x40
|
| 494 |
|
|
#define WOENB 0x80
|
| 495 |
|
|
#define MSK_RPIPE 0x07 /* mask on RPIPE field */
|
| 496 |
|
|
|
| 497 |
|
|
/* RXSYNCT register */
|
| 498 |
|
|
#define PRSIZE 0x04
|
| 499 |
|
|
#define PREEN 0x08
|
| 500 |
|
|
#define PRETYPE 0x40
|
| 501 |
|
|
#define PROLONG 0x80
|
| 502 |
|
|
|
| 503 |
|
|
#define MSK_SYCNT 0x30 /* mask on SYCNT field */
|
| 504 |
|
|
#define MSK_PTHR 0x03 /* mask on PTHR field */
|
| 505 |
|
|
|
| 506 |
|
|
/* CLOCK_CORR register */
|
| 507 |
|
|
#define SIGN 0x80
|
| 508 |
|
|
|
| 509 |
|
|
/* PRESYNC register */
|
| 510 |
|
|
#define PRESENB 0x80
|
| 511 |
|
|
|
| 512 |
|
|
#define MSK_PRES 0x0F /* mask on PRES field */
|
| 513 |
|
|
|
| 514 |
|
|
|
| 515 |
|
|
/* PLPALIN register */
|
| 516 |
|
|
#define SYNM 0x08
|
| 517 |
|
|
#define BITSLIP 0x10
|
| 518 |
|
|
#define SLOTFAIL 0x20
|
| 519 |
|
|
#define DFFAIL 0x40
|
| 520 |
|
|
#define LONGDF 0x80
|
| 521 |
|
|
#define MODE_PLPALIN 0x03 /* mask on PLP alignment mode */
|
| 522 |
|
|
|
| 523 |
|
|
/* SUSPCNTL register */
|
| 524 |
|
|
#define SUSPENB 0x01
|
| 525 |
|
|
|
| 526 |
|
|
/* TSTCNTL register */
|
| 527 |
|
|
#define DISBSCR 0x01
|
| 528 |
|
|
#define TX_TST 0x02
|
| 529 |
|
|
#define DATADIR 0x04
|
| 530 |
|
|
|
| 531 |
|
|
/* TSTDST register */
|
| 532 |
|
|
#define RDY 0x80
|
| 533 |
|
|
|
| 534 |
|
|
/** ENCRYPTION ENGINE */
|
| 535 |
|
|
|
| 536 |
|
|
/* EECNTL register */
|
| 537 |
|
|
/* Bit ENABLE already defined */
|
| 538 |
|
|
#define EECNTL_ENABLE 0x80
|
| 539 |
|
|
|
| 540 |
|
|
|
| 541 |
|
|
/** PAINT+ BLOCK */
|
| 542 |
|
|
|
| 543 |
|
|
/* PAINTCNTL register */
|
| 544 |
|
|
#define MUTEDIS0 0x0001
|
| 545 |
|
|
#define MUTEDIS1 0x0002
|
| 546 |
|
|
#define MEMLOOP0 0x0004
|
| 547 |
|
|
#define MEMLOOP1 0x0008
|
| 548 |
|
|
#define RATE0 0x0010
|
| 549 |
|
|
#define RATE1 0x0020
|
| 550 |
|
|
#define CHAN0ENB 0x0040
|
| 551 |
|
|
#define CHAN1ENB 0x0080
|
| 552 |
|
|
#define BG0ENABLE 0x0100
|
| 553 |
|
|
#define BG1ENABLE 0x0200
|
| 554 |
|
|
#define PADENABLE 0x2000
|
| 555 |
|
|
#define FORCE13 0x4000
|
| 556 |
|
|
#define PAINTENB 0x8000
|
| 557 |
|
|
|
| 558 |
|
|
|
| 559 |
|
|
/* PAINTPLLCNTL register */
|
| 560 |
|
|
#define MSK_MC 0x001F /* Mask on MC field */
|
| 561 |
|
|
#define MCSIGN 0x0020
|
| 562 |
|
|
#define MANUAL 0x0080
|
| 563 |
|
|
#define RANG0 0x0100
|
| 564 |
|
|
#define RANG1 0x0200
|
| 565 |
|
|
#define RANG2 0x0400
|
| 566 |
|
|
#define MSK_RANG 0x0700 /* Mask on RANG field */
|
| 567 |
|
|
#define FREEZD 0x1000
|
| 568 |
|
|
#define FREEZP 0x2000
|
| 569 |
|
|
#define PPFP 0x8000
|
| 570 |
|
|
|
| 571 |
|
|
/* PAINTPLLSTAT register */
|
| 572 |
|
|
#define MSK_DPHI 0x01FF /* Mask on DPHI field */
|
| 573 |
|
|
#define LOCKD 0x1000
|
| 574 |
|
|
#define LOCKP 0x2000
|
| 575 |
|
|
#define NOSIG 0x8000
|
| 576 |
|
|
|
| 577 |
|
|
/* HPPCMCNTL register */
|
| 578 |
|
|
#define LEN0 0x0001
|
| 579 |
|
|
#define LEN1 0x0002
|
| 580 |
|
|
#define LEN2 0x0004
|
| 581 |
|
|
#define MSK_LEN 0x0007 /* Mask on LEN field */
|
| 582 |
|
|
#define FREQ0 0x0010
|
| 583 |
|
|
#define FREQ1 0x0020
|
| 584 |
|
|
#define MSK_PCMFREQ 0x0030 /* Mask on FREQ field */
|
| 585 |
|
|
#define FSTYP0 0x0100
|
| 586 |
|
|
#define FSTYP1 0x0200
|
| 587 |
|
|
#define MSK_FSTYP 0x0300 /* Mask on FSTYP field */
|
| 588 |
|
|
#define IOD0 0x0400
|
| 589 |
|
|
#define IOD1 0x0800
|
| 590 |
|
|
#define MSK_IOD 0x0C00 /* Mask on FSTYP field */
|
| 591 |
|
|
#define IOCK 0x1000
|
| 592 |
|
|
#define MASTER 0x4000
|
| 593 |
|
|
#define PCMENB 0x8000
|
| 594 |
|
|
|
| 595 |
|
|
/* VBAFECNTL register */
|
| 596 |
|
|
#define MSK_VOLMIC 0x0007 /* Mask on VOLMIV field */
|
| 597 |
|
|
#define MICDIF 0x0010
|
| 598 |
|
|
#define ENBMICREF 0x0080
|
| 599 |
|
|
#define MODE0 0x0100
|
| 600 |
|
|
#define MODE1 0x0200
|
| 601 |
|
|
#define MODE2 0x0400
|
| 602 |
|
|
#define LOOP0 0x1000
|
| 603 |
|
|
#define LOOP1 0x2000
|
| 604 |
|
|
#define FLOAT 0x4000
|
| 605 |
|
|
#define VBAFENB 0x8000
|
| 606 |
|
|
|
| 607 |
|
|
/* VBAFEAMP register */
|
| 608 |
|
|
#define MSK_VOL1OUT 0x000F /* Mask on VOL1OUT field */
|
| 609 |
|
|
#define ENBCH1 0x0010
|
| 610 |
|
|
#define MSK_VOL2OUT 0x0F00 /* Mask on VOL2OUT field */
|
| 611 |
|
|
#define ENBCH2 0x1000
|
| 612 |
|
|
|
| 613 |
|
|
/* VBAFEPREAMP register */
|
| 614 |
|
|
#define MSK_VOLIN 0x000F /* Mask on VOLIN field */
|
| 615 |
|
|
#define MSK_ATT 0x0070 /* Mask on ATT field */
|
| 616 |
|
|
#define PRCNF0 0x0100
|
| 617 |
|
|
#define PRCNF1 0x0200
|
| 618 |
|
|
#define PRCNF2 0x0400
|
| 619 |
|
|
|
| 620 |
|
|
/* MPDCNTL register */
|
| 621 |
|
|
#define MPD_FREQ 0x0001
|
| 622 |
|
|
#define MPD_ENB 0x0080
|
| 623 |
|
|
|
| 624 |
|
|
/* MPDREADY register */
|
| 625 |
|
|
#define MPD_RDY 0x0001
|
| 626 |
|
|
|
| 627 |
|
|
/* G726CNTL0 register */
|
| 628 |
|
|
#define RXTONE0 0x0001
|
| 629 |
|
|
#define RXTONE1 0x0002
|
| 630 |
|
|
#define TXTONE0 0x0004
|
| 631 |
|
|
#define TXTONE1 0x0008
|
| 632 |
|
|
#define SCALE0 0x0010
|
| 633 |
|
|
#define SCALE1 0x0020
|
| 634 |
|
|
#define MSK_SCALE 0x0030 /* Mask on SCALE field */
|
| 635 |
|
|
|
| 636 |
|
|
/* G726CNTL1 register */
|
| 637 |
|
|
#define LAW 0x0001
|
| 638 |
|
|
#define UPCM 0x0002
|
| 639 |
|
|
#define G726_TXMUTE 0x0004
|
| 640 |
|
|
#define G726_RXMUTE 0x0008
|
| 641 |
|
|
#define SIDETONE 0x0010
|
| 642 |
|
|
#define SCA 0x0020
|
| 643 |
|
|
#define G726ENB 0x0080
|
| 644 |
|
|
|
| 645 |
|
|
/* G726CHANNEL register */
|
| 646 |
|
|
#define CHAN 0x0002
|
| 647 |
|
|
|
| 648 |
|
|
/* G726CHANENB register */
|
| 649 |
|
|
#define G726ENB0 0x0001
|
| 650 |
|
|
#define G726ENB1 0x0003
|
| 651 |
|
|
|
| 652 |
|
|
|
| 653 |
|
|
/** GENERAL REGISTERS BLOCK */
|
| 654 |
|
|
|
| 655 |
|
|
/* RINGCNTL register */
|
| 656 |
|
|
/* Bit ENABLE already defined */
|
| 657 |
|
|
#define RINGCNTL_ENABLE 0x80
|
| 658 |
|
|
#define FULL_BRIDGE 0x40
|
| 659 |
|
|
#define MSK_DELAY 0x30
|
| 660 |
|
|
#define RING_PADENB 0x08
|
| 661 |
|
|
#define MSK_LEVEL 0x07 /* mask on LEVEL field */
|
| 662 |
|
|
|
| 663 |
|
|
/* RSIER register (UART Interrupt enable register definition) */
|
| 664 |
|
|
#define LINE_STATUS_ENABLE 0x04
|
| 665 |
|
|
#define TX_INT_ENABLE 0x02
|
| 666 |
|
|
#define RX_INT_ENABLE 0x01
|
| 667 |
|
|
|
| 668 |
|
|
/* RSIIR register (UART Interrupt identification register definition) */
|
| 669 |
|
|
#define FIFO_ENABLE_MASK 0xC0
|
| 670 |
|
|
#define INT_ID_MASK 0x0E
|
| 671 |
|
|
#define PENDING_INT_FLAG 0x01
|
| 672 |
|
|
#define LINE_STATUS_INT 0x06 /* values for interrupt identification */
|
| 673 |
|
|
#define RX_INT 0x04
|
| 674 |
|
|
#define FIFO_TIMEOUT_INT 0x0C
|
| 675 |
|
|
#define TX_EMPTY_INT 0x02
|
| 676 |
|
|
|
| 677 |
|
|
/* RSFCR register (UART Tx/Rx FIFO control register definition) */
|
| 678 |
|
|
#define RX_LEVEL_MASK 0xC0
|
| 679 |
|
|
#define CLEAR_TX_FIFO 0x04
|
| 680 |
|
|
#define CLEAR_RX_FIFO 0x02
|
| 681 |
|
|
#define FIFO_ENABLE 0x01
|
| 682 |
|
|
#define _1_BYTE_RECEIVED 0x00 /* RX level values (Interrupt trigger ) */
|
| 683 |
|
|
#define _4_BYTE_RECEIVED 0x40
|
| 684 |
|
|
#define _8_BYTE_RECEIVED 0x80
|
| 685 |
|
|
#define _14_BYTE_RECEIVED 0xC0
|
| 686 |
|
|
|
| 687 |
|
|
/* RSLCR register (UART line control register definition) */
|
| 688 |
|
|
#define DIV_ENABLE 0x80
|
| 689 |
|
|
#define TX_BREAK_ENABLE 0x40
|
| 690 |
|
|
#define PARITY_ENABLE 0x08
|
| 691 |
|
|
#define PARITY_MASK 0x30
|
| 692 |
|
|
#define _1_STOP_BIT 0x00
|
| 693 |
|
|
#define _2_STOP_BIT 0x04
|
| 694 |
|
|
#define WORD_LENGTH_MASK 0x03
|
| 695 |
|
|
#define ODD_PARITY 0x00 /* possible value for the parity */
|
| 696 |
|
|
#define EVEN_PARITY 0x10
|
| 697 |
|
|
#define PARITY_EQUAL1 0x20
|
| 698 |
|
|
#define PARITY_EQUAL0 0x30
|
| 699 |
|
|
#define _5_BITS_CHAR 0x00 /* possible value for the word length */
|
| 700 |
|
|
#define _6_BITS_CHAR 0x01
|
| 701 |
|
|
#define _7_BITS_CHAR 0x02
|
| 702 |
|
|
#define _8_BITS_CHAR 0x03
|
| 703 |
|
|
|
| 704 |
|
|
/* RSLSR Register (UART line status register definition) */
|
| 705 |
|
|
#define RX_FIFO_ERROR 0x80
|
| 706 |
|
|
#define TXEMPTY 0x40
|
| 707 |
|
|
#define HOLD_EMPTY 0x20
|
| 708 |
|
|
#define BREAK 0x10
|
| 709 |
|
|
#define FRAME_ERROR 0x08
|
| 710 |
|
|
#define PARITY_ERROR 0x04
|
| 711 |
|
|
#define OVERRUN_ERROR 0x02
|
| 712 |
|
|
#define RX_READY 0x01
|
| 713 |
|
|
|
| 714 |
|
|
/* RSDLL Register (UART clock divider low register definition) */
|
| 715 |
|
|
/* note RSDLH is always 0x00 */
|
| 716 |
|
|
#define RS_4800 0x18
|
| 717 |
|
|
#define RS_9600 0x0C
|
| 718 |
|
|
#define RS_19200 0x06
|
| 719 |
|
|
#define RS_38400 0x03
|
| 720 |
|
|
#define RS_57600 0x02
|
| 721 |
|
|
#define RS_115200 0x01
|
| 722 |
|
|
|
| 723 |
|
|
/* RSCNT Register (UART control register definition) */
|
| 724 |
|
|
#define UART_PAD_ENABLE 0x02
|
| 725 |
|
|
|
| 726 |
|
|
/* PWMCNTL register */
|
| 727 |
|
|
#define PWMENB 0x80
|
| 728 |
|
|
#define MSK_PWMFREQ 0x03 /* mask on PWMFREQ field */
|
| 729 |
|
|
#define PWM1_PADENB 0x40
|
| 730 |
|
|
#define PWM0_PADENB 0x20
|
| 731 |
|
|
#define MIRROR 0x10
|
| 732 |
|
|
|
| 733 |
|
|
|
| 734 |
|
|
/* LCDEECNTL1 register */
|
| 735 |
|
|
/* Bit ENABLE already defined */
|
| 736 |
|
|
#define LCDEE_ENABLE 0x80
|
| 737 |
|
|
#define DA1_DA0 0x40
|
| 738 |
|
|
#define MSK_LCDEEFREQ 0x03 /* mask on LCDEEFREQ field */
|
| 739 |
|
|
#define LCDEE_PADENB 0x40
|
| 740 |
|
|
|
| 741 |
|
|
/* LCDEECNTL2 register */
|
| 742 |
|
|
#define SENDACK 0x01
|
| 743 |
|
|
#define RXACK 0x02
|
| 744 |
|
|
#define STOP 0x08
|
| 745 |
|
|
#define START 0x10
|
| 746 |
|
|
#define RX_LCDEE 0x20
|
| 747 |
|
|
#define TX_LCDEE 0x40
|
| 748 |
|
|
|
| 749 |
|
|
/* DIAGCNTL1 register */
|
| 750 |
|
|
#define DIAGL_PADENB 0x01
|
| 751 |
|
|
#define DIAGH_PADENB 0x02
|
| 752 |
|
|
|
| 753 |
|
|
/* DIAGCNTL2 register */
|
| 754 |
|
|
#define DLSEL 0x0F /* mask on DLSEL field */
|
| 755 |
|
|
#define DHSEL 0xF0 /* mask on DHSEL field */
|
| 756 |
|
|
|
| 757 |
|
|
/* KEYROW register */
|
| 758 |
|
|
#define MSK_ROW 0x1F /* mask on ROW field */
|
| 759 |
|
|
#define KEYRELEASE 0x80
|
| 760 |
|
|
|
| 761 |
|
|
/* CLKCNTL register */
|
| 762 |
|
|
#define MOSCDISABLE 0x02
|
| 763 |
|
|
#define OVERSAM 0x04
|
| 764 |
|
|
#define SQUARER 0x08
|
| 765 |
|
|
#define SWRESET 0x80
|
| 766 |
|
|
#define SWFLAG 0x80
|
| 767 |
|
|
#define TSTN_DISABLE 0x40
|
| 768 |
|
|
#define MODE55 0x10
|
| 769 |
|
|
|
| 770 |
|
|
/** THUMB and INTERFACES BLOCK */
|
| 771 |
|
|
|
| 772 |
|
|
/* CSCNTL0[6:0] registers */
|
| 773 |
|
|
#define MSK_SETUP 0x0007
|
| 774 |
|
|
#define SETUP_RD 0x0040
|
| 775 |
|
|
#define SETUP_HZ 0x0080
|
| 776 |
|
|
#define MSK_WIDTH 0x1F00
|
| 777 |
|
|
#define MSK_HZWS 0xE000
|
| 778 |
|
|
|
| 779 |
|
|
/* CSCNTL1[6:0] registers */
|
| 780 |
|
|
#define MSK_CSMODE 0x0003
|
| 781 |
|
|
#define MSK_HOLD 0x0070
|
| 782 |
|
|
#define HOLD_RD 0x0080
|
| 783 |
|
|
#define MSK_WIDTH_WR 0x0700
|
| 784 |
|
|
#define USE_WIDTH_WR 0x4000
|
| 785 |
|
|
#define WR_SHIFED 0x8000
|
| 786 |
|
|
|
| 787 |
|
|
#define CSMODE_8 0x0000
|
| 788 |
|
|
#define CSMODE_16_WHWL 0x0002
|
| 789 |
|
|
#define CSMODE_16_BHBL 0x0003
|
| 790 |
|
|
|
| 791 |
|
|
|
| 792 |
|
|
/* MUXADCNTL register */
|
| 793 |
|
|
#define MSK_AHOLD 0x0007
|
| 794 |
|
|
#define MSK_ALEWIDTH 0x0070
|
| 795 |
|
|
|
| 796 |
|
|
/* PORTCNTL register */
|
| 797 |
|
|
#define CS0_ 0x0001
|
| 798 |
|
|
#define CS1_ 0x0002
|
| 799 |
|
|
#define CS2_ 0x0004
|
| 800 |
|
|
#define CS3_ 0x0008
|
| 801 |
|
|
#define CS4_ 0x0010
|
| 802 |
|
|
#define CS5_ 0x0020
|
| 803 |
|
|
#define CS6_ 0x0040
|
| 804 |
|
|
#define DATA_H 0x0080
|
| 805 |
|
|
#define INT0 0x0100
|
| 806 |
|
|
#define INT1 0x0200
|
| 807 |
|
|
#define INT2 0x0400
|
| 808 |
|
|
#define INT3 0x0800
|
| 809 |
|
|
#define MSK_ADDRESS 0x7000
|
| 810 |
|
|
#define EXTMEM 0x8000
|
| 811 |
|
|
|
| 812 |
|
|
#define ADDRESS_128K 0x0000
|
| 813 |
|
|
#define ADDRESS_256K 0x1000
|
| 814 |
|
|
#define ADDRESS_512K 0x2000
|
| 815 |
|
|
#define ADDRESS_1M 0x3000
|
| 816 |
|
|
#define ADDRESS_2M 0x4000
|
| 817 |
|
|
|
| 818 |
|
|
|
| 819 |
|
|
/* CSGCNTL register */
|
| 820 |
|
|
#define CSSWITCH 0x0040
|
| 821 |
|
|
|
| 822 |
|
|
|
| 823 |
|
|
/* SLEEPCNTL register */
|
| 824 |
|
|
#define EXPIRED 0x01
|
| 825 |
|
|
#define SLEEP_ENABLE 0x80
|
| 826 |
|
|
|
| 827 |
|
|
/* WDCNTL register */
|
| 828 |
|
|
#define WDSTROKE 0x80
|
| 829 |
|
|
#define WDFLAG 0x80 /* same bit */
|
| 830 |
|
|
|
| 831 |
|
|
|
| 832 |
|
|
/* DCC register */
|
| 833 |
|
|
/* bit ENABLE=0x80 already defined */
|
| 834 |
|
|
#define DCC_ENABLE 0x80
|
| 835 |
|
|
|
| 836 |
|
|
|
| 837 |
|
|
/* TIMERCNTL[0:1] register */
|
| 838 |
|
|
/* bit ENABLE=0x80 already defined */
|
| 839 |
|
|
#define TIMER_ENABLE 0x80
|
| 840 |
|
|
#define RELOAD 0x0040
|
| 841 |
|
|
#define MSK_FREQ 0x0003 /* mask on FREQ field */
|
| 842 |
|
|
#define TIMER_13824kHz 0x0003
|
| 843 |
|
|
#define TIMER_864kHz 0x0002
|
| 844 |
|
|
#define TIMER_216kHz 0x0001
|
| 845 |
|
|
#define TIMER_27kHz 0x0000
|
| 846 |
|
|
|
| 847 |
|
|
|
| 848 |
|
|
/* INTMASKALL register */
|
| 849 |
|
|
#define MASKIRQ 0x80
|
| 850 |
|
|
#define MASKFIQ 0x40
|
| 851 |
|
|
|
| 852 |
|
|
/* INTEOI register */
|
| 853 |
|
|
#define EOI 0x80
|
| 854 |
|
|
|
| 855 |
|
|
/* INTMASK register */
|
| 856 |
|
|
/* INTSTAT register */
|
| 857 |
|
|
/* INTIS register */
|
| 858 |
|
|
|
| 859 |
|
|
#define PLP 0x0001
|
| 860 |
|
|
#define PCM 0x0002
|
| 861 |
|
|
#define SRX 0x0004
|
| 862 |
|
|
#define STX 0x0008
|
| 863 |
|
|
#define TMR0 0x0010
|
| 864 |
|
|
#define TMR1 0x0020
|
| 865 |
|
|
#define LCDEE 0x0100
|
| 866 |
|
|
#define KPAD 0x0200
|
| 867 |
|
|
#define TAD 0x0400
|
| 868 |
|
|
#define ADC 0x0800
|
| 869 |
|
|
#define EXT0 0x1000
|
| 870 |
|
|
#define EXT1 0x2000
|
| 871 |
|
|
#define EXT2 0x4000
|
| 872 |
|
|
#define EXT3 0x8000
|
| 873 |
|
|
|
| 874 |
|
|
/* INTCNTL[0:15] register */
|
| 875 |
|
|
#define MSK_PRIO 0x0007
|
| 876 |
|
|
#define RE 0x0008
|
| 877 |
|
|
#define RISING 0x0040
|
| 878 |
|
|
#define EDGE 0x0080
|
| 879 |
|
|
|
| 880 |
|
|
/* INTHPAI register */
|
| 881 |
|
|
#define AUTOACK 0x0080
|
| 882 |
|
|
|
| 883 |
|
|
|
| 884 |
|
|
/******************************************************************************
|
| 885 |
|
|
* Memory Mapping definition
|
| 886 |
|
|
******************************************************************************
|
| 887 |
|
|
*/
|
| 888 |
|
|
|
| 889 |
|
|
#define CSN0_BASE_ADR 0x00200000 /* Base Address of CSN0 */
|
| 890 |
|
|
#define CSN1_BASE_ADR 0x00400000 /* Base Address of CSN1 */
|
| 891 |
|
|
#define CSN2_BASE_ADR 0x00600000 /* Base Address of CSN2 */
|
| 892 |
|
|
#define CSN3_BASE_ADR 0x00800000 /* Base Address of CSN3 */
|
| 893 |
|
|
#define CSN4_BASE_ADR 0x00A00000 /* Base Address of CSN4 */
|
| 894 |
|
|
#define CSN5_BASE_ADR 0x00C00000 /* Base Address of CSN5 */
|
| 895 |
|
|
#define CSN6_BASE_ADR 0x00E00000 /* Base Address of CSN6 */
|
| 896 |
|
|
|
| 897 |
|
|
#define IRAM_BASE_ADR 0x00000000 /* Base Addr. of int. Data Memory */
|
| 898 |
|
|
#define SHRAM_BASE_ADR 0x00080000 /* Base Address of Share Memory */
|
| 899 |
|
|
#define REGS_BASE_ADR 0x000F0000 /* Base Address of registers */
|
| 900 |
|
|
#define RADRAM_BASE_ADR 0x000F0000 /* Base Address of registers */
|
| 901 |
|
|
|
| 902 |
|
|
|
| 903 |
|
|
/******************************************************************************
|
| 904 |
|
|
* Slot Control bloc
|
| 905 |
|
|
******************************************************************************
|
| 906 |
|
|
*/
|
| 907 |
|
|
|
| 908 |
|
|
#ifndef __asm__
|
| 909 |
|
|
/*** Slot Control Block structure ***/
|
| 910 |
|
|
typedef volatile struct /* normal Slot Control Block */
|
| 911 |
|
|
{
|
| 912 |
|
|
unsigned char RAD0;
|
| 913 |
|
|
unsigned char RAD1;
|
| 914 |
|
|
unsigned char MODE;
|
| 915 |
|
|
unsigned char CNTL0;
|
| 916 |
|
|
unsigned char CNTL1;
|
| 917 |
|
|
unsigned char CNTL2;
|
| 918 |
|
|
unsigned char STAT0;
|
| 919 |
|
|
unsigned char STAT1;
|
| 920 |
|
|
unsigned char STAT2;
|
| 921 |
|
|
unsigned char CRYPT;
|
| 922 |
|
|
unsigned char MUTE;
|
| 923 |
|
|
unsigned char INT_;
|
| 924 |
|
|
unsigned char AMSG;
|
| 925 |
|
|
unsigned char AHDR;
|
| 926 |
|
|
unsigned short APTR;
|
| 927 |
|
|
unsigned short IPTR;
|
| 928 |
|
|
unsigned short CfPTR;
|
| 929 |
|
|
unsigned short OtPTR;
|
| 930 |
|
|
unsigned char OFFCNTL;
|
| 931 |
|
|
unsigned char WINCNTL;
|
| 932 |
|
|
} LM_SCB;
|
| 933 |
|
|
|
| 934 |
|
|
typedef LM_SCB *LM_SCB_P; /* pointer to Slot Control Block */
|
| 935 |
|
|
#endif
|
| 936 |
|
|
|
| 937 |
|
|
/*** BIT MASKS for Slot Control Block parameters ***/
|
| 938 |
|
|
|
| 939 |
|
|
/* RAD0 parameter */
|
| 940 |
|
|
#define RC_RSSIENB 0x80 /* RSSI measurement control */
|
| 941 |
|
|
#define RC_ANTENNA2 0x08 /* antenna[2] selection */
|
| 942 |
|
|
#define RC_ANTENNA1 0x04 /* antenna[1] selection */
|
| 943 |
|
|
#define RC_ANTENNA0 0x02 /* antenna[0] selection */
|
| 944 |
|
|
#define RC_SYNOUT 0x01 /* synthesiser selection */
|
| 945 |
|
|
|
| 946 |
|
|
#define RC_ANTSEL 0x0E /* mask on RC antenna selection */
|
| 947 |
|
|
|
| 948 |
|
|
/* RAD1 parameter */
|
| 949 |
|
|
#define RC_RFC 0xF0 /* mask on RC RF carrier number */
|
| 950 |
|
|
#define RC_RFSCAN 0x08 /* RF carrier source selection */
|
| 951 |
|
|
#define RC_SYNLATCH 0x04 /* synthesizer #n Latch Enabled */
|
| 952 |
|
|
#define RC_SYN_TX 0x03 /* slot is TX (synthesizer data) */
|
| 953 |
|
|
#define RC_SYN_RX 0x02 /* slot is RX (synthesizer data) */
|
| 954 |
|
|
|
| 955 |
|
|
#define RC_SYNSLOT 0x03 /* mask on Synthesizer slot type */
|
| 956 |
|
|
|
| 957 |
|
|
/* MODE parameter */
|
| 958 |
|
|
#define AUTOB1 0x80
|
| 959 |
|
|
#define AUTOB0 0x40
|
| 960 |
|
|
#define P00 0x20
|
| 961 |
|
|
|
| 962 |
|
|
#define MSK_MODE 0x1F /* mask on SCB MODE field */
|
| 963 |
|
|
|
| 964 |
|
|
/* CNTL0 parameter */
|
| 965 |
|
|
#define LU7CH 0x80
|
| 966 |
|
|
|
| 967 |
|
|
#define MSK_BOFF 0x7F /* mask on BOFF field */
|
| 968 |
|
|
|
| 969 |
|
|
/* CNTL1 parameter */
|
| 970 |
|
|
#define TX 0x80
|
| 971 |
|
|
#define RESYNC 0x40
|
| 972 |
|
|
#define Q1 0x40 /* Q1/RESYNC mapped on same bit */
|
| 973 |
|
|
#define INHBST 0x20
|
| 974 |
|
|
#define Q2 0x20 /* Q2/INHBST mapped on same bit */
|
| 975 |
|
|
#define CTPACK 0x10
|
| 976 |
|
|
|
| 977 |
|
|
#define MSK_CTFLEN 0x0F /* mask on CTFLEN field */
|
| 978 |
|
|
|
| 979 |
|
|
/* CNTL2 parameter */
|
| 980 |
|
|
#define SLTEN 0x80
|
| 981 |
|
|
#define SINV 0x40
|
| 982 |
|
|
#define ALL 0x20
|
| 983 |
|
|
#define CO_CL 0x20 /* CO_CL/ALL mapped on same bit */
|
| 984 |
|
|
#define INTEN 0x10
|
| 985 |
|
|
#define SCOR1 0x08
|
| 986 |
|
|
#define SCOR0 0x04
|
| 987 |
|
|
#define BINTE 0x02
|
| 988 |
|
|
#define BINTU 0x01
|
| 989 |
|
|
|
| 990 |
|
|
#define MSK_SCOR 0x0C /* mask on SCOR field */
|
| 991 |
|
|
|
| 992 |
|
|
/* STAT0 parameter */
|
| 993 |
|
|
#define ZFAIL0 0x80
|
| 994 |
|
|
#define ZFAIL1 0x40
|
| 995 |
|
|
#define ZFAIL2 0x20
|
| 996 |
|
|
#define ZFAIL3 0x10
|
| 997 |
|
|
#define SCRD1 0x08
|
| 998 |
|
|
#define SCRD0 0x04
|
| 999 |
|
|
#define PRED1 0x02
|
| 1000 |
|
|
#define PRED0 0x01
|
| 1001 |
|
|
|
| 1002 |
|
|
#define MSK_ZFAIL 0xF0 /* mask on ZFAIL field */
|
| 1003 |
|
|
#define MSK_SCRD 0x0C /* mask on SCRD field */
|
| 1004 |
|
|
#define MSK_PRED 0x03 /* mask on PRED field */
|
| 1005 |
|
|
|
| 1006 |
|
|
/* STAT1 parameter */
|
| 1007 |
|
|
#define BCRC7 0x80
|
| 1008 |
|
|
#define BCRC6 0x40
|
| 1009 |
|
|
#define BCRC5 0x20
|
| 1010 |
|
|
#define BCRC4 0x10
|
| 1011 |
|
|
#define BCRC3 0x08
|
| 1012 |
|
|
#define BCRC2 0x04
|
| 1013 |
|
|
#define BCRC1 0x02
|
| 1014 |
|
|
#define BCRC0 0x01
|
| 1015 |
|
|
|
| 1016 |
|
|
/* STAT2 parameter */
|
| 1017 |
|
|
#define TMUX 0x80
|
| 1018 |
|
|
#define RADIO 0x40
|
| 1019 |
|
|
#define RFPI 0x20
|
| 1020 |
|
|
#define XCRC 0x10
|
| 1021 |
|
|
#define ACRC 0x08
|
| 1022 |
|
|
#define SYNC 0x04
|
| 1023 |
|
|
#define BCRC 0x02
|
| 1024 |
|
|
#define BCRC8 0x01
|
| 1025 |
|
|
|
| 1026 |
|
|
/* CRYPT parameter */
|
| 1027 |
|
|
#define LONG 0x80
|
| 1028 |
|
|
#define INIP 0x40
|
| 1029 |
|
|
#define ACRYPT 0x20
|
| 1030 |
|
|
#define BCRYPT 0x10
|
| 1031 |
|
|
|
| 1032 |
|
|
#define MSK_EETBL 0x0F /* mask on EETBL field */
|
| 1033 |
|
|
|
| 1034 |
|
|
/* MUTE parameter */
|
| 1035 |
|
|
#define NOTI 0x80
|
| 1036 |
|
|
#define XFAIL 0x40
|
| 1037 |
|
|
#define AFAIL 0x20
|
| 1038 |
|
|
#define NOSYNC 0x10 /*NOSYNC/TXMUTE mapped on same bit*/
|
| 1039 |
|
|
#define TXMUTE 0x10
|
| 1040 |
|
|
|
| 1041 |
|
|
#define MSK_CHAN 0x0F /* mask on CHAN field */
|
| 1042 |
|
|
|
| 1043 |
|
|
/* INT parameter */
|
| 1044 |
|
|
/* Bit RADIO is already defined */
|
| 1045 |
|
|
#define Q1Q2 0x80
|
| 1046 |
|
|
#define RFP_I 0x20
|
| 1047 |
|
|
#define X_CRC 0x10
|
| 1048 |
|
|
#define R_CRC 0x08
|
| 1049 |
|
|
#define SYNCFAIL 0x04
|
| 1050 |
|
|
#define ASYNCOK 0x02
|
| 1051 |
|
|
#define ZFIELD 0x01
|
| 1052 |
|
|
|
| 1053 |
|
|
/* AMSG parameter */
|
| 1054 |
|
|
#define PP_FP 0x80
|
| 1055 |
|
|
#define CT 0x40
|
| 1056 |
|
|
#define NT 0x20 /* NT/CTSEND mapped on same bit */
|
| 1057 |
|
|
#define CTSEND 0x20
|
| 1058 |
|
|
#define MTFIRST 0x10 /* MTFIRST/QT mapped on same bit */
|
| 1059 |
|
|
#define QT 0x10
|
| 1060 |
|
|
#define MT 0x08
|
| 1061 |
|
|
#define MTWAIT 0x04
|
| 1062 |
|
|
#define PT 0x02
|
| 1063 |
|
|
#define ESCAPE 0x01
|
| 1064 |
|
|
|
| 1065 |
|
|
/* WINCNTL parameter */
|
| 1066 |
|
|
#define LM_WIN_NONE 0x00 /* no sync window */
|
| 1067 |
|
|
#define LM_WIN_OPEN 0x3F /* wide open window size */
|
| 1068 |
|
|
#define MSK_WINSZ 0x3F
|
| 1069 |
|
|
|
| 1070 |
|
|
|
| 1071 |
|
|
|
| 1072 |
|
|
|
| 1073 |
|
|
|
| 1074 |
|
|
/*
|
| 1075 |
|
|
* Some macros to mask the VEGA+ interrupt sources
|
| 1076 |
|
|
******************************************************************************
|
| 1077 |
|
|
*/
|
| 1078 |
|
|
|
| 1079 |
|
|
#define LM_MaskPLP() (LM_Regs[INTMASK] |= PLP)
|
| 1080 |
|
|
#define LM_MaskPCM() (LM_Regs[INTMASK] |= PCM)
|
| 1081 |
|
|
|
| 1082 |
|
|
/* Vega+ product version */
|
| 1083 |
|
|
#define LM_MaskUART() (LM_Regs[INTMASK] |= SRX)
|
| 1084 |
|
|
#define LM_MaskSRX() (LM_Regs[RSIER] &= ~RX_INT_ENABLE)
|
| 1085 |
|
|
#define LM_MaskSTX() (LM_Regs[RSIER] &= ~TX_INT_ENABLE)
|
| 1086 |
|
|
#define LM_MaskUARTStatus() (LM_Regs[RSIER] &= ~LINE_STATUS_ENABLE)
|
| 1087 |
|
|
|
| 1088 |
|
|
|
| 1089 |
|
|
#define LM_MaskTMR0() (LM_Regs[INTMASK] |= TMR0)
|
| 1090 |
|
|
#define LM_MaskTMR1() (LM_Regs[INTMASK] |= TMR1)
|
| 1091 |
|
|
#define LM_MaskLCDEE() (LM_Regs[INTMASK] |= LCDEE)
|
| 1092 |
|
|
#define LM_MaskKPAD() (LM_Regs[INTMASK] |= KPAD)
|
| 1093 |
|
|
#define LM_MaskTAD() (LM_Regs[INTMASK] |= TAD)
|
| 1094 |
|
|
#define LM_MaskADC() (LM_Regs[INTMASK] |= ADC)
|
| 1095 |
|
|
#define LM_MaskEXT0() (LM_Regs[INTMASK] |= EXT0)
|
| 1096 |
|
|
#define LM_MaskEXT1() (LM_Regs[INTMASK] |= EXT1)
|
| 1097 |
|
|
#define LM_MaskEXT2() (LM_Regs[INTMASK] |= EXT2)
|
| 1098 |
|
|
#define LM_MaskEXT3() (LM_Regs[INTMASK] |= EXT3)
|
| 1099 |
|
|
|
| 1100 |
|
|
/* Some macros to ummask the VEGA+ interrupt sources */
|
| 1101 |
|
|
#define LM_UnMaskPLP() (LM_Regs[INTMASK] &= ~PLP)
|
| 1102 |
|
|
#define LM_UnMaskPCM() (LM_Regs[INTMASK] &= ~PCM)
|
| 1103 |
|
|
|
| 1104 |
|
|
/* Vega+ product version */
|
| 1105 |
|
|
#define LM_UnMaskUART() (LM_Regs[INTMASK] &= ~SRX)
|
| 1106 |
|
|
#define LM_UnMaskSRX() (LM_Regs[RSIER] |= RX_INT_ENABLE)
|
| 1107 |
|
|
#define LM_UnMaskSTX() (LM_Regs[RSIER] |= TX_INT_ENABLE)
|
| 1108 |
|
|
#define LM_UnMaskUARTStatus() (LM_Regs[RSIER] |= LINE_STATUS_ENABLE)
|
| 1109 |
|
|
|
| 1110 |
|
|
#define LM_UnMaskTMR0() (LM_Regs[INTMASK] &= ~TMR0)
|
| 1111 |
|
|
#define LM_UnMaskTMR1() (LM_Regs[INTMASK] &= ~TMR1)
|
| 1112 |
|
|
#define LM_UnMaskLCDEE() (LM_Regs[INTMASK] &= ~LCDEE)
|
| 1113 |
|
|
#define LM_UnMaskKPAD() (LM_Regs[INTMASK] &= ~KPAD)
|
| 1114 |
|
|
#define LM_UnMaskTAD() (LM_Regs[INTMASK] &= ~TAD)
|
| 1115 |
|
|
#define LM_UnMaskADC() (LM_Regs[INTMASK] &= ~ADC)
|
| 1116 |
|
|
#define LM_UnMaskEXT0() (LM_Regs[INTMASK] &= ~EXT0)
|
| 1117 |
|
|
#define LM_UnMaskEXT1() (LM_Regs[INTMASK] &= ~EXT1)
|
| 1118 |
|
|
#define LM_UnMaskEXT2() (LM_Regs[INTMASK] &= ~EXT2)
|
| 1119 |
|
|
#define LM_UnMaskEXT3() (LM_Regs[INTMASK] &= ~EXT3)
|
| 1120 |
|
|
|
| 1121 |
|
|
/* Some macros to Acknoledge the VEGA+ interrupt sources */
|
| 1122 |
|
|
#define LM_AckPLP() (LM_Regs[INTACK] |= PLP)
|
| 1123 |
|
|
#define LM_AckPCM() (LM_Regs[INTACK] |= PCM)
|
| 1124 |
|
|
#define LM_AckTMR0() (LM_Regs[INTACK] |= TMR0)
|
| 1125 |
|
|
#define LM_AckTMR1() (LM_Regs[INTACK] |= TMR1)
|
| 1126 |
|
|
#define LM_AckEXT0() (LM_Regs[INTACK] |= EXT0)
|
| 1127 |
|
|
#define LM_AckEXT1() (LM_Regs[INTACK] |= EXT1)
|
| 1128 |
|
|
#define LM_AckEXT2() (LM_Regs[INTACK] |= EXT2)
|
| 1129 |
|
|
#define LM_AckEXT3() (LM_Regs[INTACK] |= EXT3)
|
| 1130 |
|
|
|
| 1131 |
|
|
/*#define INIT_LMREGS_MAPPING() { LM_Regs = (unsigned long*)REGS_BASE_ADR; }*/
|
| 1132 |
|
|
|
| 1133 |
|
|
#endif /*__LMREGS_H__*/
|
