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[/] [or1k/] [trunk/] [rtems-20020807/] [c/] [src/] [lib/] [libbsp/] [i386/] [i386ex/] [start/] [80386ex.h] - Blame information for rev 1765

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1 1026 ivang
/*
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 *  Submitted by:
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 *
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 *    Erik Ivanenko
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 *    University of Toronto
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 *    erik.ivanenko@utoronto.ca
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 *
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 *  The license and distribution terms for this file may be
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 *  found in the file LICENSE in this distribution or at
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 *  http://www.OARcorp.com/rtems/license.html.
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 *
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 *  80386ex.h,v 1.1 1998/03/30 13:42:12 joel Exp
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 */
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/* REMAP ADDRESSING Registers */
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#define REMAPCFGH         0x0023
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#define REMAPCFGL         0x0022
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#define REMAPCFG          0x0022
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/* INTERRUPT CONTROL REGISTERS -- SLOT 15 ADDRESSES */
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#define ICW1M     0xF020
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#define ICW1S     0xF0A0
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#define ICW2M     0xF021
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#define ICW2S     0xF0A1
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#define ICW3M     0xF021
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#define ICW3S     0xF0A1
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#define ICW4M     0xF021
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#define ICW4S     0xF0A1
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#define OCW1M     0xF021
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#define OCW1S     0xF0A1
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#define OCW2M     0xF020
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#define OCW2S     0xF0A0
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#define OCW3M     0xF020
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#define OCW3S     0xF0A0
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/* INTERRUPT CONTROL REGISTERS -- SLOT 0 ADDRESSES */
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#define ICW1MDOS          0x0020
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#define ICW1SDOS          0x00A0
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#define ICW2MDOS          0x0021
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#define ICW2SDOS          0x00A1
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#define ICW3MDOS          0x0021
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#define ICW3SDOS          0x00A1
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#define ICW4MDOS          0x0021
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#define ICW4SDOS          0x00A1
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#define OCW1MDOS          0x0021
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#define OCW1SDOS          0x00A1
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#define OCW2MDOS          0x0020
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#define OCW2SDOS          0x00A0
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#define OCW3MDOS          0x0020
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#define OCW3SDOS          0x00A0
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/* CONFIGURATION Registers */
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#define DMACFG    0xF830
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#define INTCFG    0xF832
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#define TMRCFG    0xF834
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#define SIOCFG    0xF836
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#define P1CFG     0xF820
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#define P2CFG     0xF822
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#define P3CFG     0xF824
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#define PINCFG    0xF826
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/* WATCHDOG TIMER Registers */
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#define WDTRLDH   0xF4C0
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#define WDTRLDL   0xF4C2
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#define WDTCNTH   0xF4C4
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#define WDTCNTL   0xF4C6
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#define WDTCLR    0xF4C8
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#define WDTSTATUS    0xF4CA
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/* TIMER CONTROL REGISTERS -- SLOT 15 ADDRESSES */
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#define TMR0      0xF040
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#define TMR1      0xF041
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#define TMR2      0xF042
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#define TMRCON    0xF043
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/* TIMER CONTROL REGISTERS -- SLOT 0 ADDRESSES */
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#define TMR0DOS   0x0040
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#define TMR1DOS   0x0041
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#define TMR2DOS   0x0042
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#define TMRCONDOS    0x0043
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/* INPUT/OUTPUT PORT UNIT Registers */
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#define P1PIN     0xF860
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#define P1LTC     0xF862
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#define P1DIR     0xF864
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#define P2PIN     0xF868
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#define P2LTC     0xF86A
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#define P2DIR     0xF86C
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#define P3PIN     0xF870
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#define P3LTC     0xF872
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#define P3DIR     0xF874
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/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 15 ADDRESSES */
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#define RBR0      0xF4F8
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#define THR0      0xF4F8
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#define TBR0      0xF4F8
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#define DLL0      0xF4F8
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#define IER0      0xF4F9
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#define DLH0      0xF4F9
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#define IIR0      0xF4FA
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#define LCR0      0xF4FB
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#define MCR0      0xF4FC
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#define LSR0      0xF4FD
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#define MSR0      0xF4FE
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#define SCR0      0xF4FF
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/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 0 ADDRESSES */
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#define RBR0DOS   0x03F8
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#define THR0DOS   0x03F8
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#define TBR0DOS   0x03F8
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#define DLL0DOS   0x03F8
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#define IER0DOS   0x03F9
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#define DLH0DOS   0x03F9
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#define IIR0DOS   0x03FA
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#define LCR0DOS   0x03FB
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#define MCR0DOS   0x03FC
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#define LSR0DOS   0x03FD
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#define MSR0DOS   0x03FE
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#define SCR0DOS   0x03FF
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/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 15 ADDRESSES */
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#define RBR1      0xF8F8
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#define THR1      0xF8F8
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#define TBR1      0XF8F8
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#define DLL1      0xF8F8
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#define IER1      0xF8F9
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#define DLH1      0xF8F9
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#define IIR1      0xF8FA
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#define LCR1      0xF8FB
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#define MCR1      0xF8FC
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#define LSR1      0xF8FD
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#define MSR1      0xF8FE
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#define SCR1      0xF8FF
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/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 0 ADDRESSES */
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#define RBR1DOS   0x02F8
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#define THR1DOS   0x02F8
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#define TBR1DOS   0x02F8
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#define DLL1DOS   0x02F8
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#define IER1DOS   0x02F9
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#define DLH1DOS   0x02F9
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#define IIR1DOS   0x02FA
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#define LCR1DOS   0x02FB
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#define MCR1DOS   0x02FC
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#define LSR1DOS   0x02FD
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#define MSR1DOS   0x02FE
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#define SCR1DOS   0x02FF
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/* SYNCHRONOUS SERIAL CHANNEL REGISTERS */
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#define SSIOTBUF          0xF480
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#define SSIORBUF          0xF482
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#define SSIOBAUD          0xF484
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#define SSIOCON1          0xF486
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#define SSIOCON2          0xF488
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#define SSIOCTR   0xF48A
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/* CHIP SELECT UNIT Registers */
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#define CS0ADL    0xF400
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#define CS0ADH    0xF402
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#define CS0MSKL   0xF404
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#define CS0MSKH   0xF406
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#define CS1ADL    0xF408
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#define CS1ADH    0xF40A
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#define CS1MSKL   0xF40C
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#define CS1MSKH   0xF40E
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#define CS2ADL    0xF410
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#define CS2ADH    0xF412
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#define CS2MSKL   0xF414
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#define CS2MSKH   0xF416
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#define CS3ADL    0xF418
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#define CS3ADH    0xF41A
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#define CS3MSKL   0xF41C
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#define CS3MSKH   0xF41E
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#define CS4ADL    0xF420
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#define CS4ADH    0xF422
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#define CS4MSKL   0xF424
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#define CS4MSKH   0xF426
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#define CS5ADL    0xF428
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#define CS5ADH    0xF42A
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#define CS5MSKL   0xF42C
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#define CS5MSKH   0xF42E
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#define CS6ADL    0xF430
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#define CS6ADH    0xF432
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#define CS6MSKL   0xF434
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#define CS6MSKH   0xF436
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#define UCSADL    0xF438
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#define UCSADH    0xF43A
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#define UCSMSKL   0xF43C
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#define UCSMSKH   0xF43E
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/* REFRESH CONTROL UNIT Registers */
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#define RFSBAD    0xF4A0
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#define RFSCIR    0xF4A2
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#define RFSCON    0xF4A4
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#define RFSADD    0xF4A6
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/* POWER MANAGEMENT CONTROL Registers */
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#define PWRCON    0xF800
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#define CLKPRS    0xF804
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/* DMA UNIT REGISTERS -- SLOT 15 ADDRESSES */
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#define DMA0TAR   0xF000
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#define DMA0BYC   0xF001
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#define DMA1TAR   0xF002
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#define DMA1BYC   0xF003
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#define DMACMD1   0xF008
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#define DMASTS    0xF008
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#define DMASRR    0xF009
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#define DMAMSK    0xF00A
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#define DMAMOD1   0xF00B
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#define DMACLRBP          0xF00C
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#define DMACLR    0xF00D
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#define DMACLRMSK    0xF00E
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#define DMAGRPMSK    0xF00F
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#define DMA0REQL          0xF010
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#define DMA0REQH          0xF011
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#define DMA1REQL          0xF012
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#define DMA1REQH          0xF013
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#define DMABSR    0xF018
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#define DMACHR    0xF019
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#define DMAIS     0xF019
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#define DMACMD2   0xF01A
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#define DMAMOD2   0xF01B
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#define DMAIEN    0xF01C
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#define DMAOVFE   0xF01D
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#define DMACLRTC          0xF01E
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#define DMA1TARPL    0xF083
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#define DMA1TARPH    0xF085
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#define DMA0TARPH    0xF086
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#define DMA0TARPL    0xF087
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#define DMA0BYCH          0xF098
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#define DMA1BYCH          0xF099
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/* DMA UNIT REGISTERS -- SLOT 0 ADDRESSES */
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#define DMA0TARDOS        0x0000
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#define DMA0BYCDOS        0x0001
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#define DMA1TARDOS        0x0002
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#define DMA1BYCDOS        0x0003
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#define DMACMD1DOS        0x0008
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#define DMASTSDOS         0x0008
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#define DMASRRDOS         0x0009
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#define DMAMSKDOS         0x000A
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#define DMAMOD1DOS        0x000B
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#define DMACLRBPDOS  0x000C
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#define DMACLRDOS         0x000D
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#define DMACLRMSKDOS   0x000E
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#define DMAGRPMSKDOS   0x000F
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#define DMA1TARPLDOS   0x0083
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#define DMA0TARPLDOS   0x0087
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/* A20GATE AND FAST CPU RESET -- SLOT 15 ADDRESS */
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#define PORT92    0xF092
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/* A20GATE AND FAST CPU RESET -- SLOT 0 ADDRESS */
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#define PORT92DOS    0x0092
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/* end of include file */

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