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[/] [or1k/] [trunk/] [rtems-20020807/] [c/] [src/] [lib/] [libbsp/] [sparc/] [erc32/] [include/] [erc32.h] - Blame information for rev 1026

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1 1026 ivang
/*  erc32.h
2
 *
3
 *  This include file contains information pertaining to the ERC32.
4
 *  The ERC32 is a custom SPARC V7 implementation based on the Cypress
5
 *  601/602 chipset.  This CPU has a number of on-board peripherals and
6
 *  was developed by the European Space Agency to target space applications.
7
 *
8
 *  NOTE:  Other than where absolutely required, this version currently
9
 *         supports only the peripherals and bits used by the basic board
10
 *         support package. This includes at least significant pieces of
11
 *         the following items:
12
 *
13
 *           + UART Channels A and B
14
 *           + General Purpose Timer
15
 *           + Real Time Clock
16
 *           + Watchdog Timer (so it can be disabled)
17
 *           + Control Register (so powerdown mode can be enabled)
18
 *           + Memory Control Register
19
 *           + Interrupt Control
20
 *
21
 *  COPYRIGHT (c) 1989-1999.
22
 *  On-Line Applications Research Corporation (OAR).
23
 *
24
 *  The license and distribution terms for this file may be
25
 *  found in the file LICENSE in this distribution or at
26
 *  http://www.OARcorp.com/rtems/license.html.
27
 *
28
 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
29
 *  Research Corporation (OAR) under contract to the European Space
30
 *  Agency (ESA).
31
 *
32
 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
33
 *  European Space Agency.
34
 *
35
 *  erc32.h,v 1.2 2002/07/01 22:04:33 joel Exp
36
 */
37
 
38
#ifndef _INCLUDE_ERC32_h
39
#define _INCLUDE_ERC32_h
40
 
41
#include <rtems/score/sparc.h>
42
 
43
#ifdef __cplusplus
44
extern "C" {
45
#endif
46
 
47
/*
48
 *  Interrupt Sources
49
 *
50
 *  The interrupt source numbers directly map to the trap type and to
51
 *  the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
52
 *  and the Interrupt Pending Registers.
53
 */
54
 
55
#define ERC32_INTERRUPT_MASKED_ERRORS             1
56
#define ERC32_INTERRUPT_EXTERNAL_1                2
57
#define ERC32_INTERRUPT_EXTERNAL_2                3
58
#define ERC32_INTERRUPT_UART_A_RX_TX              4
59
#define ERC32_INTERRUPT_UART_B_RX_TX              5
60
#define ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR  6
61
#define ERC32_INTERRUPT_UART_ERROR                7
62
#define ERC32_INTERRUPT_DMA_ACCESS_ERROR          8
63
#define ERC32_INTERRUPT_DMA_TIMEOUT               9
64
#define ERC32_INTERRUPT_EXTERNAL_3               10
65
#define ERC32_INTERRUPT_EXTERNAL_4               11
66
#define ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER    12
67
#define ERC32_INTERRUPT_REAL_TIME_CLOCK          13
68
#define ERC32_INTERRUPT_EXTERNAL_5               14
69
#define ERC32_INTERRUPT_WATCHDOG_TIMEOUT         15
70
 
71
#ifndef ASM
72
 
73
/*
74
 *  Trap Types for on-chip peripherals
75
 *
76
 *  Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
77
 *
78
 *  NOTE: The priority level for each source corresponds to the least
79
 *        significant nibble of the trap type.
80
 */
81
 
82
#define ERC32_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10)
83
 
84
#define ERC32_TRAP_SOURCE( _trap ) ((_trap) - 0x10)
85
 
86
#define ERC32_Is_MEC_Trap( _trap ) \
87
  ( (_trap) >= ERC32_TRAP_TYPE( ERC32_INTERRUPT_MASKED_ERRORS ) && \
88
    (_trap) <= ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ) )
89
 
90
/*
91
 *  Structure for ERC32 memory mapped registers.
92
 *
93
 *  Source: Section 3.25.2 - Register Address Map
94
 *
95
 *  NOTE:  There is only one of these structures per CPU, its base address
96
 *         is 0x01f80000, and the variable MEC is placed there by the
97
 *         linkcmds file.
98
 */
99
 
100
typedef struct {
101
  volatile unsigned32  Control;                              /* offset 0x00 */
102
  volatile unsigned32  Software_Reset;                       /* offset 0x04 */
103
  volatile unsigned32  Power_Down;                           /* offset 0x08 */
104
  volatile unsigned32  Unimplemented_0;                      /* offset 0x0c */
105
  volatile unsigned32  Memory_Configuration;                 /* offset 0x10 */
106
  volatile unsigned32  IO_Configuration;                     /* offset 0x14 */
107
  volatile unsigned32  Wait_State_Configuration;             /* offset 0x18 */
108
  volatile unsigned32  Unimplemented_1;                      /* offset 0x1c */
109
  volatile unsigned32  Memory_Access_0;                      /* offset 0x20 */
110
  volatile unsigned32  Memory_Access_1;                      /* offset 0x24 */
111
  volatile unsigned32  Unimplemented_2[ 7 ];                 /* offset 0x28 */
112
  volatile unsigned32  Interrupt_Shape;                      /* offset 0x44 */
113
  volatile unsigned32  Interrupt_Pending;                    /* offset 0x48 */
114
  volatile unsigned32  Interrupt_Mask;                       /* offset 0x4c */
115
  volatile unsigned32  Interrupt_Clear;                      /* offset 0x50 */
116
  volatile unsigned32  Interrupt_Force;                      /* offset 0x54 */
117
  volatile unsigned32  Unimplemented_3[ 2 ];                 /* offset 0x58 */
118
                                                             /* offset 0x60 */
119
  volatile unsigned32  Watchdog_Program_and_Timeout_Acknowledge;
120
  volatile unsigned32  Watchdog_Trap_Door_Set;               /* offset 0x64 */
121
  volatile unsigned32  Unimplemented_4[ 6 ];                 /* offset 0x68 */
122
  volatile unsigned32  Real_Time_Clock_Counter;              /* offset 0x80 */
123
  volatile unsigned32  Real_Time_Clock_Scalar;               /* offset 0x84 */
124
  volatile unsigned32  General_Purpose_Timer_Counter;        /* offset 0x88 */
125
  volatile unsigned32  General_Purpose_Timer_Scalar;         /* offset 0x8c */
126
  volatile unsigned32  Unimplemented_5[ 2 ];                 /* offset 0x90 */
127
  volatile unsigned32  Timer_Control;                        /* offset 0x98 */
128
  volatile unsigned32  Unimplemented_6;                      /* offset 0x9c */
129
  volatile unsigned32  System_Fault_Status;                  /* offset 0xa0 */
130
  volatile unsigned32  First_Failing_Address;                /* offset 0xa4 */
131
  volatile unsigned32  First_Failing_Data;                   /* offset 0xa8 */
132
  volatile unsigned32  First_Failing_Syndrome_and_Check_Bits;/* offset 0xac */
133
  volatile unsigned32  Error_and_Reset_Status;               /* offset 0xb0 */
134
  volatile unsigned32  Error_Mask;                           /* offset 0xb4 */
135
  volatile unsigned32  Unimplemented_7[ 2 ];                 /* offset 0xb8 */
136
  volatile unsigned32  Debug_Control;                        /* offset 0xc0 */
137
  volatile unsigned32  Breakpoint;                           /* offset 0xc4 */
138
  volatile unsigned32  Watchpoint;                           /* offset 0xc8 */
139
  volatile unsigned32  Unimplemented_8;                      /* offset 0xcc */
140
  volatile unsigned32  Test_Control;                         /* offset 0xd0 */
141
  volatile unsigned32  Test_Data;                            /* offset 0xd4 */
142
  volatile unsigned32  Unimplemented_9[ 2 ];                 /* offset 0xd8 */
143
  volatile unsigned32  UART_Channel_A;                       /* offset 0xe0 */
144
  volatile unsigned32  UART_Channel_B;                       /* offset 0xe4 */
145
  volatile unsigned32  UART_Status;                          /* offset 0xe8 */
146
} ERC32_Register_Map;
147
 
148
#endif
149
 
150
/*
151
 *  The following constants are intended to be used ONLY in assembly
152
 *  language files.
153
 *
154
 *  NOTE:  The intended style of usage is to load the address of MEC
155
 *         into a register and then use these as displacements from
156
 *         that register.
157
 */
158
 
159
#ifdef ASM
160
 
161
#define  ERC32_MEC_CONTROL_OFFSET                                  0x00
162
#define  ERC32_MEC_SOFTWARE_RESET_OFFSET                           0x04
163
#define  ERC32_MEC_POWER_DOWN_OFFSET                               0x08
164
#define  ERC32_MEC_UNIMPLEMENTED_0_OFFSET                          0x0C
165
#define  ERC32_MEC_MEMORY_CONFIGURATION_OFFSET                     0x10
166
#define  ERC32_MEC_IO_CONFIGURATION_OFFSET                         0x14
167
#define  ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET                 0x18
168
#define  ERC32_MEC_UNIMPLEMENTED_1_OFFSET                          0x1C
169
#define  ERC32_MEC_MEMORY_ACCESS_0_OFFSET                          0x20
170
#define  ERC32_MEC_MEMORY_ACCESS_1_OFFSET                          0x24
171
#define  ERC32_MEC_UNIMPLEMENTED_2_OFFSET                          0x28
172
#define  ERC32_MEC_INTERRUPT_SHAPE_OFFSET                          0x44
173
#define  ERC32_MEC_INTERRUPT_PENDING_OFFSET                        0x48
174
#define  ERC32_MEC_INTERRUPT_MASK_OFFSET                           0x4C
175
#define  ERC32_MEC_INTERRUPT_CLEAR_OFFSET                          0x50
176
#define  ERC32_MEC_INTERRUPT_FORCE_OFFSET                          0x54
177
#define  ERC32_MEC_UNIMPLEMENTED_3_OFFSET                          0x58
178
#define  ERC32_MEC_WATCHDOG_PROGRAM_AND_TIMEOUT_ACKNOWLEDGE_OFFSET 0x60
179
#define  ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET                   0x64
180
#define  ERC32_MEC_UNIMPLEMENTED_4_OFFSET                          0x6C
181
#define  ERC32_MEC_REAL_TIME_CLOCK_COUNTER_OFFSET                  0x80
182
#define  ERC32_MEC_REAL_TIME_CLOCK_SCALAR_OFFSET                   0x84
183
#define  ERC32_MEC_GENERAL_PURPOSE_TIMER_COUNTER_OFFSET            0x88
184
#define  ERC32_MEC_GENERAL_PURPOSE_TIMER_SCALAR_OFFSET             0x8C
185
#define  ERC32_MEC_UNIMPLEMENTED_5_OFFSET                          0x90
186
#define  ERC32_MEC_TIMER_CONTROL_OFFSET                            0x98
187
#define  ERC32_MEC_UNIMPLEMENTED_6_OFFSET                          0x9C
188
#define  ERC32_MEC_SYSTEM_FAULT_STATUS_OFFSET                      0xA0
189
#define  ERC32_MEC_FIRST_FAILING_ADDRESS_OFFSET                    0xA4
190
#define  ERC32_MEC_FIRST_FAILING_DATA_OFFSET                       0xA8
191
#define  ERC32_MEC_FIRST_FAILING_SYNDROME_AND_CHECK_BITS_OFFSET    0xAC
192
#define  ERC32_MEC_ERROR_AND_RESET_STATUS_OFFSET                   0xB0
193
#define  ERC32_MEC_ERROR_MASK_OFFSET                               0xB4
194
#define  ERC32_MEC_UNIMPLEMENTED_7_OFFSET                          0xB8
195
#define  ERC32_MEC_DEBUG_CONTROL_OFFSET                            0xC0
196
#define  ERC32_MEC_BREAKPOINT_OFFSET                               0xC4
197
#define  ERC32_MEC_WATCHPOINT_OFFSET                               0xC8
198
#define  ERC32_MEC_UNIMPLEMENTED_8_OFFSET                          0xCC
199
#define  ERC32_MEC_TEST_CONTROL_OFFSET                             0xD0
200
#define  ERC32_MEC_TEST_DATA_OFFSET                                0xD4
201
#define  ERC32_MEC_UNIMPLEMENTED_9_OFFSET                          0xD8
202
#define  ERC32_MEC_UART_CHANNEL_A_OFFSET                           0xE0
203
#define  ERC32_MEC_UART_CHANNEL_B_OFFSET                           0xE4
204
#define  ERC32_MEC_UART_STATUS_OFFSET                              0xE8
205
 
206
#endif
207
 
208
/*
209
 *  The following defines the bits in the Configuration Register.
210
 */
211
 
212
#define ERC32_CONFIGURATION_POWER_DOWN_MASK               0x00000001
213
#define ERC32_CONFIGURATION_POWER_DOWN_ALLOWED            0x00000001
214
#define ERC32_CONFIGURATION_POWER_DOWN_DISABLED           0x00000000
215
 
216
#define ERC32_CONFIGURATION_SOFTWARE_RESET_MASK           0x00000002
217
#define ERC32_CONFIGURATION_SOFTWARE_RESET_ALLOWED        0x00000002
218
#define ERC32_CONFIGURATION_SOFTWARE_RESET_DISABLED       0x00000000
219
 
220
#define ERC32_CONFIGURATION_BUS_TIMEOUT_MASK              0x00000004
221
#define ERC32_CONFIGURATION_BUS_TIMEOUT_ENABLED           0x00000004
222
#define ERC32_CONFIGURATION_BUS_TIMEOUT_DISABLED          0x00000000
223
 
224
#define ERC32_CONFIGURATION_ACCESS_PROTECTION_MASK        0x00000008
225
#define ERC32_CONFIGURATION_ACCESS_PROTECTION_ENABLED     0x00000008
226
#define ERC32_CONFIGURATION_ACCESS_PROTECTION_DISABLED    0x00000000
227
 
228
 
229
/*
230
 *  The following defines the bits in the Memory Configuration Register.
231
 */
232
 
233
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_MASK  0x00001C00
234
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_256K  ( 0 << 10 )
235
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_512K  ( 1 << 10 )
236
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_1MB   ( 2 << 10 )
237
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_2MB   ( 3 << 10 )
238
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_4MB   ( 4 << 10 )
239
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_8MB   ( 5 << 10 )
240
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_16MB  ( 6 << 10 )
241
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB  ( 7 << 10 )
242
 
243
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK  0x001C0000
244
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K    ( 0 << 18 )
245
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K    ( 1 << 18 )
246
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K   ( 2 << 18 )
247
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_1M   ( 3 << 18 )
248
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_2M   ( 4 << 18 )
249
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M  ( 5 << 18 )
250
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M  ( 6 << 18 )
251
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M  ( 7 << 18 )
252
 
253
/*
254
 *  The following defines the bits in the Timer Control Register.
255
 */
256
 
257
#define ERC32_MEC_TIMER_CONTROL_GCR    0x00000001  /* 1 = reload at 0 */
258
                                               /* 0 = stop at 0 */
259
#define ERC32_MEC_TIMER_CONTROL_GCL    0x00000002  /* 1 = load and start */
260
                                               /* 0 = no function */
261
#define ERC32_MEC_TIMER_CONTROL_GSE    0x00000004  /* 1 = enable counting */
262
                                               /* 0 = hold scalar and counter */
263
#define ERC32_MEC_TIMER_CONTROL_GSL    0x00000008  /* 1 = load scalar and start */
264
                                               /* 0 = no function */
265
 
266
#define ERC32_MEC_TIMER_CONTROL_RTCCR  0x00000100  /* 1 = reload at 0 */
267
                                               /* 0 = stop at 0 */
268
#define ERC32_MEC_TIMER_CONTROL_RTCCL  0x00000200  /* 1 = load and start */
269
                                               /* 0 = no function */
270
#define ERC32_MEC_TIMER_CONTROL_RTCSE  0x00000400  /* 1 = enable counting */
271
                                               /* 0 = hold scalar and counter */
272
#define ERC32_MEC_TIMER_CONTROL_RTCSL  0x00000800  /* 1 = load scalar and start */
273
                                               /* 0 = no function */
274
 
275
/*
276
 *  The following defines the bits in the UART Control Registers.
277
 *
278
 */
279
 
280
#define ERC32_MEC_UART_CONTROL_RTD  0x000000FF /* RX/TX data */ 
281
 
282
/*
283
 *  The following defines the bits in the MEC UART Control Registers.
284
 */
285
 
286
#define ERC32_MEC_UART_STATUS_DR   0x00000001 /* Data Ready */
287
#define ERC32_MEC_UART_STATUS_TSE  0x00000002 /* TX Send Register Empty */
288
#define ERC32_MEC_UART_STATUS_THE  0x00000004 /* TX Hold Register Empty */
289
#define ERC32_MEC_UART_STATUS_FE   0x00000010 /* RX Framing Error */
290
#define ERC32_MEC_UART_STATUS_PE   0x00000020 /* RX Parity Error */
291
#define ERC32_MEC_UART_STATUS_OE   0x00000040 /* RX Overrun Error */
292
#define ERC32_MEC_UART_STATUS_CU   0x00000080 /* Clear Errors */
293
#define ERC32_MEC_UART_STATUS_TXE  0x00000006 /* TX Empty */
294
#define ERC32_MEC_UART_STATUS_CLRA 0x00000080 /* Clear UART A */
295
#define ERC32_MEC_UART_STATUS_CLRB 0x00800000 /* Clear UART B */
296
#define ERC32_MEC_UART_STATUS_ERRA 0x00000070 /* Error in UART A */
297
#define ERC32_MEC_UART_STATUS_ERRB 0x00700000 /* Error in UART B */
298
 
299
#define ERC32_MEC_UART_STATUS_DRA   (ERC32_MEC_UART_STATUS_DR  << 0)
300
#define ERC32_MEC_UART_STATUS_TSEA  (ERC32_MEC_UART_STATUS_TSE << 0)
301
#define ERC32_MEC_UART_STATUS_THEA  (ERC32_MEC_UART_STATUS_THE << 0)
302
#define ERC32_MEC_UART_STATUS_FEA   (ERC32_MEC_UART_STATUS_FE  << 0)
303
#define ERC32_MEC_UART_STATUS_PEA   (ERC32_MEC_UART_STATUS_PE  << 0)
304
#define ERC32_MEC_UART_STATUS_OEA   (ERC32_MEC_UART_STATUS_OE  << 0)
305
#define ERC32_MEC_UART_STATUS_CUA   (ERC32_MEC_UART_STATUS_CU  << 0)
306
#define ERC32_MEC_UART_STATUS_TXEA  (ERC32_MEC_UART_STATUS_TXE << 0)
307
 
308
#define ERC32_MEC_UART_STATUS_DRB   (ERC32_MEC_UART_STATUS_DR  << 16)
309
#define ERC32_MEC_UART_STATUS_TSEB  (ERC32_MEC_UART_STATUS_TSE << 16)
310
#define ERC32_MEC_UART_STATUS_THEB  (ERC32_MEC_UART_STATUS_THE << 16)
311
#define ERC32_MEC_UART_STATUS_FEB   (ERC32_MEC_UART_STATUS_FE  << 16)
312
#define ERC32_MEC_UART_STATUS_PEB   (ERC32_MEC_UART_STATUS_PE  << 16)
313
#define ERC32_MEC_UART_STATUS_OEB   (ERC32_MEC_UART_STATUS_OE  << 16)
314
#define ERC32_MEC_UART_STATUS_CUB   (ERC32_MEC_UART_STATUS_CU  << 16)
315
#define ERC32_MEC_UART_STATUS_TXEB  (ERC32_MEC_UART_STATUS_TXE << 16)
316
 
317
#ifndef ASM
318
 
319
/*
320
 *  This is used to manipulate the on-chip registers.
321
 *
322
 *  The following symbol must be defined in the linkcmds file and point
323
 *  to the correct location.
324
 */
325
 
326
extern ERC32_Register_Map ERC32_MEC;
327
 
328
/*
329
 *  Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
330
 *  and the Interrupt Pending Registers.
331
 *
332
 *  NOTE: For operations which are not atomic, this code disables interrupts
333
 *        to guarantee there are no intervening accesses to the same register.
334
 *        The operations which read the register, modify the value and then
335
 *        store the result back are vulnerable.
336
 */
337
 
338
#define ERC32_Clear_interrupt( _source ) \
339
  do { \
340
    ERC32_MEC.Interrupt_Clear = (1 << (_source)); \
341
  } while (0)
342
 
343
#define ERC32_Force_interrupt( _source ) \
344
  do { \
345
    unsigned32 _level; \
346
    \
347
    _level = sparc_disable_interrupts(); \
348
    ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \
349
    ERC32_MEC.Interrupt_Force = (1 << (_source)); \
350
    sparc_enable_interrupts( _level ); \
351
  } while (0)
352
 
353
#define ERC32_Is_interrupt_pending( _source ) \
354
  (ERC32_MEC.Interrupt_Pending & (1 << (_source)))
355
 
356
#define ERC32_Is_interrupt_masked( _source ) \
357
  (ERC32_MEC.Interrupt_Masked & (1 << (_source)))
358
 
359
#define ERC32_Mask_interrupt( _source ) \
360
  do { \
361
    unsigned32 _level; \
362
    \
363
    _level = sparc_disable_interrupts(); \
364
      ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \
365
    sparc_enable_interrupts( _level ); \
366
  } while (0)
367
 
368
#define ERC32_Unmask_interrupt( _source ) \
369
  do { \
370
    unsigned32 _level; \
371
    \
372
    _level = sparc_disable_interrupts(); \
373
      ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \
374
    sparc_enable_interrupts( _level ); \
375
  } while (0)
376
 
377
#define ERC32_Disable_interrupt( _source, _previous ) \
378
  do { \
379
    unsigned32 _level; \
380
    unsigned32 _mask = 1 << (_source); \
381
    \
382
    _level = sparc_disable_interrupts(); \
383
      (_previous) = ERC32_MEC.Interrupt_Mask; \
384
      ERC32_MEC.Interrupt_Mask = _previous | _mask; \
385
    sparc_enable_interrupts( _level ); \
386
    (_previous) &= _mask; \
387
  } while (0)
388
 
389
#define ERC32_Restore_interrupt( _source, _previous ) \
390
  do { \
391
    unsigned32 _level; \
392
    unsigned32 _mask = 1 << (_source); \
393
    \
394
    _level = sparc_disable_interrupts(); \
395
      ERC32_MEC.Interrupt_Mask = \
396
        (ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \
397
    sparc_enable_interrupts( _level ); \
398
  } while (0)
399
 
400
/*
401
 *  The following macros attempt to hide the fact that the General Purpose
402
 *  Timer and Real Time Clock Timer share the Timer Control Register.  Because
403
 *  the Timer Control Register is write only, we must mirror it in software
404
 *  and insure that writes to one timer do not alter the current settings
405
 *  and status of the other timer.
406
 *
407
 *  This code promotes the view that the two timers are completely independent.
408
 *  By exclusively using the routines below to access the Timer Control
409
 *  Register, the application can view the system as having a General Purpose
410
 *  Timer Control Register and a Real Time Clock Timer Control Register
411
 *  rather than the single shared value.
412
 *
413
 *  Each logical timer control register is organized as follows:
414
 *
415
 *    D0 - Counter Reload
416
 *          1 = reload counter at zero and restart
417
 *          0 = stop counter at zero
418
 *
419
 *    D1 - Counter Load
420
 *          1 = load counter with preset value and restart
421
 *          0 = no function
422
 *
423
 *    D2 - Enable
424
 *          1 = enable counting
425
 *          0 = hold scaler and counter
426
 *
427
 *    D3 - Scaler Load
428
 *          1 = load scalar with preset value and restart
429
 *          0 = no function
430
 *
431
 *  To insure the management of the mirror is atomic, we disable interrupts
432
 *  around updates.
433
 */
434
 
435
#define ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO     0x00000001
436
#define ERC32_MEC_TIMER_COUNTER_STOP_AT_ZERO       0x00000000
437
 
438
#define ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER       0x00000002
439
 
440
#define ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING    0x00000004
441
#define ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING   0x00000000
442
 
443
#define ERC32_MEC_TIMER_COUNTER_LOAD_SCALER        0x00000008
444
 
445
#define ERC32_MEC_TIMER_COUNTER_RELOAD_MASK        0x00000001
446
#define ERC32_MEC_TIMER_COUNTER_ENABLE_MASK        0x00000004
447
 
448
#define ERC32_MEC_TIMER_COUNTER_DEFINED_MASK       0x0000000F
449
#define ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK  0x00000005
450
 
451
extern unsigned32 _ERC32_MEC_Timer_Control_Mirror;
452
 
453
/*
454
 *  This macros manipulate the General Purpose Timer portion of the
455
 *  Timer Control register and promote the view that there are actually
456
 *  two independent Timer Control Registers.
457
 */
458
 
459
#define ERC32_MEC_Set_General_Purpose_Timer_Control( _value ) \
460
  do { \
461
    unsigned32 _level; \
462
    unsigned32 _control; \
463
    unsigned32 __value; \
464
    \
465
    __value = ((_value) & 0x0f); \
466
    _level = sparc_disable_interrupts(); \
467
      _control = _ERC32_MEC_Timer_Control_Mirror; \
468
      _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \
469
      _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
470
      _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \
471
      _control |= __value; \
472
      /* printf( "GPT 0x%x 0x%x 0x%x\n", _value, __value, _control );  */ \
473
      ERC32_MEC.Timer_Control = _control; \
474
    sparc_enable_interrupts( _level ); \
475
  } while ( 0 )
476
 
477
#define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \
478
  do { \
479
    (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
480
  } while ( 0 )
481
 
482
/*
483
 *  This macros manipulate the Real Timer Clock Timer portion of the
484
 *  Timer Control register and promote the view that there are actually
485
 *  two independent Timer Control Registers.
486
 */
487
 
488
#define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \
489
  do { \
490
    unsigned32 _level; \
491
    unsigned32 _control; \
492
    unsigned32 __value; \
493
    \
494
    __value = ((_value) & 0x0f) << 8; \
495
    _level = sparc_disable_interrupts(); \
496
      _control = _ERC32_MEC_Timer_Control_Mirror; \
497
      _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \
498
      _ERC32_MEC_Timer_Control_Mirror = _control | __value; \
499
      _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \
500
      _control |= __value; \
501
      /* printf( "RTC 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \
502
      ERC32_MEC.Timer_Control = _control; \
503
    sparc_enable_interrupts( _level ); \
504
  } while ( 0 )
505
 
506
#define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \
507
  do { \
508
    (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
509
  } while ( 0 )
510
 
511
 
512
#endif /* !ASM */
513
 
514
#ifdef __cplusplus
515
}
516
#endif
517
 
518
#endif /* !_INCLUDE_ERC32_h */
519
/* end of include file */
520
 

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