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/* erc32.h
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*
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* This include file contains information pertaining to the ERC32.
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* The ERC32 is a custom SPARC V7 implementation based on the Cypress
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* 601/602 chipset. This CPU has a number of on-board peripherals and
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* was developed by the European Space Agency to target space applications.
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*
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* NOTE: Other than where absolutely required, this version currently
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* supports only the peripherals and bits used by the basic board
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* support package. This includes at least significant pieces of
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* the following items:
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*
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* + UART Channels A and B
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* + General Purpose Timer
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* + Real Time Clock
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* + Watchdog Timer (so it can be disabled)
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* + Control Register (so powerdown mode can be enabled)
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* + Memory Control Register
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* + Interrupt Control
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* Ported to ERC32 implementation of the SPARC by On-Line Applications
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* Research Corporation (OAR) under contract to the European Space
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* Agency (ESA).
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*
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* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
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* European Space Agency.
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*
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* erc32.h,v 1.2 2002/07/01 22:04:33 joel Exp
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*/
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#ifndef _INCLUDE_ERC32_h
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#define _INCLUDE_ERC32_h
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#include <rtems/score/sparc.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Interrupt Sources
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*
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* The interrupt source numbers directly map to the trap type and to
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* the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
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* and the Interrupt Pending Registers.
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*/
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#define ERC32_INTERRUPT_MASKED_ERRORS 1
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#define ERC32_INTERRUPT_EXTERNAL_1 2
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#define ERC32_INTERRUPT_EXTERNAL_2 3
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#define ERC32_INTERRUPT_UART_A_RX_TX 4
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#define ERC32_INTERRUPT_UART_B_RX_TX 5
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#define ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR 6
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#define ERC32_INTERRUPT_UART_ERROR 7
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#define ERC32_INTERRUPT_DMA_ACCESS_ERROR 8
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#define ERC32_INTERRUPT_DMA_TIMEOUT 9
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#define ERC32_INTERRUPT_EXTERNAL_3 10
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#define ERC32_INTERRUPT_EXTERNAL_4 11
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#define ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER 12
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#define ERC32_INTERRUPT_REAL_TIME_CLOCK 13
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#define ERC32_INTERRUPT_EXTERNAL_5 14
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#define ERC32_INTERRUPT_WATCHDOG_TIMEOUT 15
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#ifndef ASM
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/*
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* Trap Types for on-chip peripherals
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*
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* Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
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*
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* NOTE: The priority level for each source corresponds to the least
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* significant nibble of the trap type.
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*/
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#define ERC32_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10)
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#define ERC32_TRAP_SOURCE( _trap ) ((_trap) - 0x10)
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#define ERC32_Is_MEC_Trap( _trap ) \
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( (_trap) >= ERC32_TRAP_TYPE( ERC32_INTERRUPT_MASKED_ERRORS ) && \
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(_trap) <= ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ) )
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/*
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* Structure for ERC32 memory mapped registers.
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*
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* Source: Section 3.25.2 - Register Address Map
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*
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* NOTE: There is only one of these structures per CPU, its base address
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* is 0x01f80000, and the variable MEC is placed there by the
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* linkcmds file.
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*/
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typedef struct {
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volatile unsigned32 Control; /* offset 0x00 */
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volatile unsigned32 Software_Reset; /* offset 0x04 */
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volatile unsigned32 Power_Down; /* offset 0x08 */
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volatile unsigned32 Unimplemented_0; /* offset 0x0c */
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volatile unsigned32 Memory_Configuration; /* offset 0x10 */
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volatile unsigned32 IO_Configuration; /* offset 0x14 */
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volatile unsigned32 Wait_State_Configuration; /* offset 0x18 */
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volatile unsigned32 Unimplemented_1; /* offset 0x1c */
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volatile unsigned32 Memory_Access_0; /* offset 0x20 */
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volatile unsigned32 Memory_Access_1; /* offset 0x24 */
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volatile unsigned32 Unimplemented_2[ 7 ]; /* offset 0x28 */
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volatile unsigned32 Interrupt_Shape; /* offset 0x44 */
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volatile unsigned32 Interrupt_Pending; /* offset 0x48 */
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volatile unsigned32 Interrupt_Mask; /* offset 0x4c */
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volatile unsigned32 Interrupt_Clear; /* offset 0x50 */
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volatile unsigned32 Interrupt_Force; /* offset 0x54 */
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volatile unsigned32 Unimplemented_3[ 2 ]; /* offset 0x58 */
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/* offset 0x60 */
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volatile unsigned32 Watchdog_Program_and_Timeout_Acknowledge;
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volatile unsigned32 Watchdog_Trap_Door_Set; /* offset 0x64 */
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volatile unsigned32 Unimplemented_4[ 6 ]; /* offset 0x68 */
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volatile unsigned32 Real_Time_Clock_Counter; /* offset 0x80 */
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volatile unsigned32 Real_Time_Clock_Scalar; /* offset 0x84 */
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volatile unsigned32 General_Purpose_Timer_Counter; /* offset 0x88 */
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volatile unsigned32 General_Purpose_Timer_Scalar; /* offset 0x8c */
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volatile unsigned32 Unimplemented_5[ 2 ]; /* offset 0x90 */
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volatile unsigned32 Timer_Control; /* offset 0x98 */
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volatile unsigned32 Unimplemented_6; /* offset 0x9c */
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volatile unsigned32 System_Fault_Status; /* offset 0xa0 */
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volatile unsigned32 First_Failing_Address; /* offset 0xa4 */
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volatile unsigned32 First_Failing_Data; /* offset 0xa8 */
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volatile unsigned32 First_Failing_Syndrome_and_Check_Bits;/* offset 0xac */
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volatile unsigned32 Error_and_Reset_Status; /* offset 0xb0 */
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volatile unsigned32 Error_Mask; /* offset 0xb4 */
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volatile unsigned32 Unimplemented_7[ 2 ]; /* offset 0xb8 */
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volatile unsigned32 Debug_Control; /* offset 0xc0 */
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volatile unsigned32 Breakpoint; /* offset 0xc4 */
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volatile unsigned32 Watchpoint; /* offset 0xc8 */
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volatile unsigned32 Unimplemented_8; /* offset 0xcc */
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volatile unsigned32 Test_Control; /* offset 0xd0 */
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volatile unsigned32 Test_Data; /* offset 0xd4 */
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volatile unsigned32 Unimplemented_9[ 2 ]; /* offset 0xd8 */
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volatile unsigned32 UART_Channel_A; /* offset 0xe0 */
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volatile unsigned32 UART_Channel_B; /* offset 0xe4 */
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volatile unsigned32 UART_Status; /* offset 0xe8 */
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} ERC32_Register_Map;
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#endif
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/*
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* The following constants are intended to be used ONLY in assembly
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* language files.
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*
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* NOTE: The intended style of usage is to load the address of MEC
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* into a register and then use these as displacements from
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* that register.
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*/
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#ifdef ASM
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#define ERC32_MEC_CONTROL_OFFSET 0x00
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#define ERC32_MEC_SOFTWARE_RESET_OFFSET 0x04
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#define ERC32_MEC_POWER_DOWN_OFFSET 0x08
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#define ERC32_MEC_UNIMPLEMENTED_0_OFFSET 0x0C
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#define ERC32_MEC_MEMORY_CONFIGURATION_OFFSET 0x10
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#define ERC32_MEC_IO_CONFIGURATION_OFFSET 0x14
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#define ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET 0x18
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#define ERC32_MEC_UNIMPLEMENTED_1_OFFSET 0x1C
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#define ERC32_MEC_MEMORY_ACCESS_0_OFFSET 0x20
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#define ERC32_MEC_MEMORY_ACCESS_1_OFFSET 0x24
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#define ERC32_MEC_UNIMPLEMENTED_2_OFFSET 0x28
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#define ERC32_MEC_INTERRUPT_SHAPE_OFFSET 0x44
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#define ERC32_MEC_INTERRUPT_PENDING_OFFSET 0x48
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#define ERC32_MEC_INTERRUPT_MASK_OFFSET 0x4C
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#define ERC32_MEC_INTERRUPT_CLEAR_OFFSET 0x50
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#define ERC32_MEC_INTERRUPT_FORCE_OFFSET 0x54
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#define ERC32_MEC_UNIMPLEMENTED_3_OFFSET 0x58
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#define ERC32_MEC_WATCHDOG_PROGRAM_AND_TIMEOUT_ACKNOWLEDGE_OFFSET 0x60
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#define ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET 0x64
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#define ERC32_MEC_UNIMPLEMENTED_4_OFFSET 0x6C
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#define ERC32_MEC_REAL_TIME_CLOCK_COUNTER_OFFSET 0x80
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#define ERC32_MEC_REAL_TIME_CLOCK_SCALAR_OFFSET 0x84
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#define ERC32_MEC_GENERAL_PURPOSE_TIMER_COUNTER_OFFSET 0x88
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#define ERC32_MEC_GENERAL_PURPOSE_TIMER_SCALAR_OFFSET 0x8C
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#define ERC32_MEC_UNIMPLEMENTED_5_OFFSET 0x90
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#define ERC32_MEC_TIMER_CONTROL_OFFSET 0x98
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#define ERC32_MEC_UNIMPLEMENTED_6_OFFSET 0x9C
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#define ERC32_MEC_SYSTEM_FAULT_STATUS_OFFSET 0xA0
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#define ERC32_MEC_FIRST_FAILING_ADDRESS_OFFSET 0xA4
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#define ERC32_MEC_FIRST_FAILING_DATA_OFFSET 0xA8
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#define ERC32_MEC_FIRST_FAILING_SYNDROME_AND_CHECK_BITS_OFFSET 0xAC
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#define ERC32_MEC_ERROR_AND_RESET_STATUS_OFFSET 0xB0
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#define ERC32_MEC_ERROR_MASK_OFFSET 0xB4
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#define ERC32_MEC_UNIMPLEMENTED_7_OFFSET 0xB8
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#define ERC32_MEC_DEBUG_CONTROL_OFFSET 0xC0
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#define ERC32_MEC_BREAKPOINT_OFFSET 0xC4
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#define ERC32_MEC_WATCHPOINT_OFFSET 0xC8
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#define ERC32_MEC_UNIMPLEMENTED_8_OFFSET 0xCC
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#define ERC32_MEC_TEST_CONTROL_OFFSET 0xD0
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#define ERC32_MEC_TEST_DATA_OFFSET 0xD4
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#define ERC32_MEC_UNIMPLEMENTED_9_OFFSET 0xD8
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#define ERC32_MEC_UART_CHANNEL_A_OFFSET 0xE0
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#define ERC32_MEC_UART_CHANNEL_B_OFFSET 0xE4
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#define ERC32_MEC_UART_STATUS_OFFSET 0xE8
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#endif
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/*
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* The following defines the bits in the Configuration Register.
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*/
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#define ERC32_CONFIGURATION_POWER_DOWN_MASK 0x00000001
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#define ERC32_CONFIGURATION_POWER_DOWN_ALLOWED 0x00000001
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#define ERC32_CONFIGURATION_POWER_DOWN_DISABLED 0x00000000
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#define ERC32_CONFIGURATION_SOFTWARE_RESET_MASK 0x00000002
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#define ERC32_CONFIGURATION_SOFTWARE_RESET_ALLOWED 0x00000002
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#define ERC32_CONFIGURATION_SOFTWARE_RESET_DISABLED 0x00000000
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#define ERC32_CONFIGURATION_BUS_TIMEOUT_MASK 0x00000004
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#define ERC32_CONFIGURATION_BUS_TIMEOUT_ENABLED 0x00000004
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#define ERC32_CONFIGURATION_BUS_TIMEOUT_DISABLED 0x00000000
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#define ERC32_CONFIGURATION_ACCESS_PROTECTION_MASK 0x00000008
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#define ERC32_CONFIGURATION_ACCESS_PROTECTION_ENABLED 0x00000008
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#define ERC32_CONFIGURATION_ACCESS_PROTECTION_DISABLED 0x00000000
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/*
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* The following defines the bits in the Memory Configuration Register.
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*/
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#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001C00
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#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_256K ( 0 << 10 )
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#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_512K ( 1 << 10 )
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#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_1MB ( 2 << 10 )
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#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_2MB ( 3 << 10 )
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#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_4MB ( 4 << 10 )
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#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_8MB ( 5 << 10 )
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#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_16MB ( 6 << 10 )
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#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB ( 7 << 10 )
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#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x001C0000
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#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K ( 0 << 18 )
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#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K ( 1 << 18 )
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#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K ( 2 << 18 )
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#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_1M ( 3 << 18 )
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#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_2M ( 4 << 18 )
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#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M ( 5 << 18 )
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#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M ( 6 << 18 )
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#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M ( 7 << 18 )
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/*
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* The following defines the bits in the Timer Control Register.
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*/
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#define ERC32_MEC_TIMER_CONTROL_GCR 0x00000001 /* 1 = reload at 0 */
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/* 0 = stop at 0 */
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#define ERC32_MEC_TIMER_CONTROL_GCL 0x00000002 /* 1 = load and start */
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/* 0 = no function */
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#define ERC32_MEC_TIMER_CONTROL_GSE 0x00000004 /* 1 = enable counting */
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/* 0 = hold scalar and counter */
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#define ERC32_MEC_TIMER_CONTROL_GSL 0x00000008 /* 1 = load scalar and start */
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/* 0 = no function */
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#define ERC32_MEC_TIMER_CONTROL_RTCCR 0x00000100 /* 1 = reload at 0 */
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/* 0 = stop at 0 */
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#define ERC32_MEC_TIMER_CONTROL_RTCCL 0x00000200 /* 1 = load and start */
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/* 0 = no function */
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#define ERC32_MEC_TIMER_CONTROL_RTCSE 0x00000400 /* 1 = enable counting */
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/* 0 = hold scalar and counter */
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#define ERC32_MEC_TIMER_CONTROL_RTCSL 0x00000800 /* 1 = load scalar and start */
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/* 0 = no function */
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/*
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* The following defines the bits in the UART Control Registers.
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*
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*/
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#define ERC32_MEC_UART_CONTROL_RTD 0x000000FF /* RX/TX data */
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/*
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* The following defines the bits in the MEC UART Control Registers.
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*/
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#define ERC32_MEC_UART_STATUS_DR 0x00000001 /* Data Ready */
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#define ERC32_MEC_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
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#define ERC32_MEC_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
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#define ERC32_MEC_UART_STATUS_FE 0x00000010 /* RX Framing Error */
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#define ERC32_MEC_UART_STATUS_PE 0x00000020 /* RX Parity Error */
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#define ERC32_MEC_UART_STATUS_OE 0x00000040 /* RX Overrun Error */
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#define ERC32_MEC_UART_STATUS_CU 0x00000080 /* Clear Errors */
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#define ERC32_MEC_UART_STATUS_TXE 0x00000006 /* TX Empty */
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#define ERC32_MEC_UART_STATUS_CLRA 0x00000080 /* Clear UART A */
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295 |
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#define ERC32_MEC_UART_STATUS_CLRB 0x00800000 /* Clear UART B */
|
296 |
|
|
#define ERC32_MEC_UART_STATUS_ERRA 0x00000070 /* Error in UART A */
|
297 |
|
|
#define ERC32_MEC_UART_STATUS_ERRB 0x00700000 /* Error in UART B */
|
298 |
|
|
|
299 |
|
|
#define ERC32_MEC_UART_STATUS_DRA (ERC32_MEC_UART_STATUS_DR << 0)
|
300 |
|
|
#define ERC32_MEC_UART_STATUS_TSEA (ERC32_MEC_UART_STATUS_TSE << 0)
|
301 |
|
|
#define ERC32_MEC_UART_STATUS_THEA (ERC32_MEC_UART_STATUS_THE << 0)
|
302 |
|
|
#define ERC32_MEC_UART_STATUS_FEA (ERC32_MEC_UART_STATUS_FE << 0)
|
303 |
|
|
#define ERC32_MEC_UART_STATUS_PEA (ERC32_MEC_UART_STATUS_PE << 0)
|
304 |
|
|
#define ERC32_MEC_UART_STATUS_OEA (ERC32_MEC_UART_STATUS_OE << 0)
|
305 |
|
|
#define ERC32_MEC_UART_STATUS_CUA (ERC32_MEC_UART_STATUS_CU << 0)
|
306 |
|
|
#define ERC32_MEC_UART_STATUS_TXEA (ERC32_MEC_UART_STATUS_TXE << 0)
|
307 |
|
|
|
308 |
|
|
#define ERC32_MEC_UART_STATUS_DRB (ERC32_MEC_UART_STATUS_DR << 16)
|
309 |
|
|
#define ERC32_MEC_UART_STATUS_TSEB (ERC32_MEC_UART_STATUS_TSE << 16)
|
310 |
|
|
#define ERC32_MEC_UART_STATUS_THEB (ERC32_MEC_UART_STATUS_THE << 16)
|
311 |
|
|
#define ERC32_MEC_UART_STATUS_FEB (ERC32_MEC_UART_STATUS_FE << 16)
|
312 |
|
|
#define ERC32_MEC_UART_STATUS_PEB (ERC32_MEC_UART_STATUS_PE << 16)
|
313 |
|
|
#define ERC32_MEC_UART_STATUS_OEB (ERC32_MEC_UART_STATUS_OE << 16)
|
314 |
|
|
#define ERC32_MEC_UART_STATUS_CUB (ERC32_MEC_UART_STATUS_CU << 16)
|
315 |
|
|
#define ERC32_MEC_UART_STATUS_TXEB (ERC32_MEC_UART_STATUS_TXE << 16)
|
316 |
|
|
|
317 |
|
|
#ifndef ASM
|
318 |
|
|
|
319 |
|
|
/*
|
320 |
|
|
* This is used to manipulate the on-chip registers.
|
321 |
|
|
*
|
322 |
|
|
* The following symbol must be defined in the linkcmds file and point
|
323 |
|
|
* to the correct location.
|
324 |
|
|
*/
|
325 |
|
|
|
326 |
|
|
extern ERC32_Register_Map ERC32_MEC;
|
327 |
|
|
|
328 |
|
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/*
|
329 |
|
|
* Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
|
330 |
|
|
* and the Interrupt Pending Registers.
|
331 |
|
|
*
|
332 |
|
|
* NOTE: For operations which are not atomic, this code disables interrupts
|
333 |
|
|
* to guarantee there are no intervening accesses to the same register.
|
334 |
|
|
* The operations which read the register, modify the value and then
|
335 |
|
|
* store the result back are vulnerable.
|
336 |
|
|
*/
|
337 |
|
|
|
338 |
|
|
#define ERC32_Clear_interrupt( _source ) \
|
339 |
|
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do { \
|
340 |
|
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ERC32_MEC.Interrupt_Clear = (1 << (_source)); \
|
341 |
|
|
} while (0)
|
342 |
|
|
|
343 |
|
|
#define ERC32_Force_interrupt( _source ) \
|
344 |
|
|
do { \
|
345 |
|
|
unsigned32 _level; \
|
346 |
|
|
\
|
347 |
|
|
_level = sparc_disable_interrupts(); \
|
348 |
|
|
ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \
|
349 |
|
|
ERC32_MEC.Interrupt_Force = (1 << (_source)); \
|
350 |
|
|
sparc_enable_interrupts( _level ); \
|
351 |
|
|
} while (0)
|
352 |
|
|
|
353 |
|
|
#define ERC32_Is_interrupt_pending( _source ) \
|
354 |
|
|
(ERC32_MEC.Interrupt_Pending & (1 << (_source)))
|
355 |
|
|
|
356 |
|
|
#define ERC32_Is_interrupt_masked( _source ) \
|
357 |
|
|
(ERC32_MEC.Interrupt_Masked & (1 << (_source)))
|
358 |
|
|
|
359 |
|
|
#define ERC32_Mask_interrupt( _source ) \
|
360 |
|
|
do { \
|
361 |
|
|
unsigned32 _level; \
|
362 |
|
|
\
|
363 |
|
|
_level = sparc_disable_interrupts(); \
|
364 |
|
|
ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \
|
365 |
|
|
sparc_enable_interrupts( _level ); \
|
366 |
|
|
} while (0)
|
367 |
|
|
|
368 |
|
|
#define ERC32_Unmask_interrupt( _source ) \
|
369 |
|
|
do { \
|
370 |
|
|
unsigned32 _level; \
|
371 |
|
|
\
|
372 |
|
|
_level = sparc_disable_interrupts(); \
|
373 |
|
|
ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \
|
374 |
|
|
sparc_enable_interrupts( _level ); \
|
375 |
|
|
} while (0)
|
376 |
|
|
|
377 |
|
|
#define ERC32_Disable_interrupt( _source, _previous ) \
|
378 |
|
|
do { \
|
379 |
|
|
unsigned32 _level; \
|
380 |
|
|
unsigned32 _mask = 1 << (_source); \
|
381 |
|
|
\
|
382 |
|
|
_level = sparc_disable_interrupts(); \
|
383 |
|
|
(_previous) = ERC32_MEC.Interrupt_Mask; \
|
384 |
|
|
ERC32_MEC.Interrupt_Mask = _previous | _mask; \
|
385 |
|
|
sparc_enable_interrupts( _level ); \
|
386 |
|
|
(_previous) &= _mask; \
|
387 |
|
|
} while (0)
|
388 |
|
|
|
389 |
|
|
#define ERC32_Restore_interrupt( _source, _previous ) \
|
390 |
|
|
do { \
|
391 |
|
|
unsigned32 _level; \
|
392 |
|
|
unsigned32 _mask = 1 << (_source); \
|
393 |
|
|
\
|
394 |
|
|
_level = sparc_disable_interrupts(); \
|
395 |
|
|
ERC32_MEC.Interrupt_Mask = \
|
396 |
|
|
(ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \
|
397 |
|
|
sparc_enable_interrupts( _level ); \
|
398 |
|
|
} while (0)
|
399 |
|
|
|
400 |
|
|
/*
|
401 |
|
|
* The following macros attempt to hide the fact that the General Purpose
|
402 |
|
|
* Timer and Real Time Clock Timer share the Timer Control Register. Because
|
403 |
|
|
* the Timer Control Register is write only, we must mirror it in software
|
404 |
|
|
* and insure that writes to one timer do not alter the current settings
|
405 |
|
|
* and status of the other timer.
|
406 |
|
|
*
|
407 |
|
|
* This code promotes the view that the two timers are completely independent.
|
408 |
|
|
* By exclusively using the routines below to access the Timer Control
|
409 |
|
|
* Register, the application can view the system as having a General Purpose
|
410 |
|
|
* Timer Control Register and a Real Time Clock Timer Control Register
|
411 |
|
|
* rather than the single shared value.
|
412 |
|
|
*
|
413 |
|
|
* Each logical timer control register is organized as follows:
|
414 |
|
|
*
|
415 |
|
|
* D0 - Counter Reload
|
416 |
|
|
* 1 = reload counter at zero and restart
|
417 |
|
|
* 0 = stop counter at zero
|
418 |
|
|
*
|
419 |
|
|
* D1 - Counter Load
|
420 |
|
|
* 1 = load counter with preset value and restart
|
421 |
|
|
* 0 = no function
|
422 |
|
|
*
|
423 |
|
|
* D2 - Enable
|
424 |
|
|
* 1 = enable counting
|
425 |
|
|
* 0 = hold scaler and counter
|
426 |
|
|
*
|
427 |
|
|
* D3 - Scaler Load
|
428 |
|
|
* 1 = load scalar with preset value and restart
|
429 |
|
|
* 0 = no function
|
430 |
|
|
*
|
431 |
|
|
* To insure the management of the mirror is atomic, we disable interrupts
|
432 |
|
|
* around updates.
|
433 |
|
|
*/
|
434 |
|
|
|
435 |
|
|
#define ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000001
|
436 |
|
|
#define ERC32_MEC_TIMER_COUNTER_STOP_AT_ZERO 0x00000000
|
437 |
|
|
|
438 |
|
|
#define ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER 0x00000002
|
439 |
|
|
|
440 |
|
|
#define ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING 0x00000004
|
441 |
|
|
#define ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING 0x00000000
|
442 |
|
|
|
443 |
|
|
#define ERC32_MEC_TIMER_COUNTER_LOAD_SCALER 0x00000008
|
444 |
|
|
|
445 |
|
|
#define ERC32_MEC_TIMER_COUNTER_RELOAD_MASK 0x00000001
|
446 |
|
|
#define ERC32_MEC_TIMER_COUNTER_ENABLE_MASK 0x00000004
|
447 |
|
|
|
448 |
|
|
#define ERC32_MEC_TIMER_COUNTER_DEFINED_MASK 0x0000000F
|
449 |
|
|
#define ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000005
|
450 |
|
|
|
451 |
|
|
extern unsigned32 _ERC32_MEC_Timer_Control_Mirror;
|
452 |
|
|
|
453 |
|
|
/*
|
454 |
|
|
* This macros manipulate the General Purpose Timer portion of the
|
455 |
|
|
* Timer Control register and promote the view that there are actually
|
456 |
|
|
* two independent Timer Control Registers.
|
457 |
|
|
*/
|
458 |
|
|
|
459 |
|
|
#define ERC32_MEC_Set_General_Purpose_Timer_Control( _value ) \
|
460 |
|
|
do { \
|
461 |
|
|
unsigned32 _level; \
|
462 |
|
|
unsigned32 _control; \
|
463 |
|
|
unsigned32 __value; \
|
464 |
|
|
\
|
465 |
|
|
__value = ((_value) & 0x0f); \
|
466 |
|
|
_level = sparc_disable_interrupts(); \
|
467 |
|
|
_control = _ERC32_MEC_Timer_Control_Mirror; \
|
468 |
|
|
_control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \
|
469 |
|
|
_ERC32_MEC_Timer_Control_Mirror = _control | _value; \
|
470 |
|
|
_control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \
|
471 |
|
|
_control |= __value; \
|
472 |
|
|
/* printf( "GPT 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \
|
473 |
|
|
ERC32_MEC.Timer_Control = _control; \
|
474 |
|
|
sparc_enable_interrupts( _level ); \
|
475 |
|
|
} while ( 0 )
|
476 |
|
|
|
477 |
|
|
#define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \
|
478 |
|
|
do { \
|
479 |
|
|
(_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
|
480 |
|
|
} while ( 0 )
|
481 |
|
|
|
482 |
|
|
/*
|
483 |
|
|
* This macros manipulate the Real Timer Clock Timer portion of the
|
484 |
|
|
* Timer Control register and promote the view that there are actually
|
485 |
|
|
* two independent Timer Control Registers.
|
486 |
|
|
*/
|
487 |
|
|
|
488 |
|
|
#define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \
|
489 |
|
|
do { \
|
490 |
|
|
unsigned32 _level; \
|
491 |
|
|
unsigned32 _control; \
|
492 |
|
|
unsigned32 __value; \
|
493 |
|
|
\
|
494 |
|
|
__value = ((_value) & 0x0f) << 8; \
|
495 |
|
|
_level = sparc_disable_interrupts(); \
|
496 |
|
|
_control = _ERC32_MEC_Timer_Control_Mirror; \
|
497 |
|
|
_control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \
|
498 |
|
|
_ERC32_MEC_Timer_Control_Mirror = _control | __value; \
|
499 |
|
|
_control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \
|
500 |
|
|
_control |= __value; \
|
501 |
|
|
/* printf( "RTC 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \
|
502 |
|
|
ERC32_MEC.Timer_Control = _control; \
|
503 |
|
|
sparc_enable_interrupts( _level ); \
|
504 |
|
|
} while ( 0 )
|
505 |
|
|
|
506 |
|
|
#define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \
|
507 |
|
|
do { \
|
508 |
|
|
(_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
|
509 |
|
|
} while ( 0 )
|
510 |
|
|
|
511 |
|
|
|
512 |
|
|
#endif /* !ASM */
|
513 |
|
|
|
514 |
|
|
#ifdef __cplusplus
|
515 |
|
|
}
|
516 |
|
|
#endif
|
517 |
|
|
|
518 |
|
|
#endif /* !_INCLUDE_ERC32_h */
|
519 |
|
|
/* end of include file */
|
520 |
|
|
|