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1026 |
ivang |
/*
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* Copyright (c) 1995, David Greenman
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* Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD: src/sys/dev/fxp/if_fxpreg.h,v 1.23.2.4 2001/08/31 02:17:02 jlemon Exp $
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*/
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#define FXP_VENDORID_INTEL 0x8086
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#define FXP_PCI_MMBA 0x10
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#define FXP_PCI_IOBA 0x14
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/*
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* Control/status registers.
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*/
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#define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */
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#define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */
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#define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */
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#define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */
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#define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */
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#define FXP_CSR_PORT 8 /* port (4 bytes) */
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#define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */
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#define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */
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#define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */
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#define FXP_CSR_FLOWCONTROL 0x19 /* flow control (2 bytes) */
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#define FXP_CSR_GENCONTROL 0x1C /* general control (1 byte) */
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/*
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* FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS:
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*
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* volatile u_int8_t :2,
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* scb_rus:4,
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* scb_cus:2;
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*/
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#define FXP_PORT_SOFTWARE_RESET 0
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#define FXP_PORT_SELFTEST 1
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#define FXP_PORT_SELECTIVE_RESET 2
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#define FXP_PORT_DUMP 3
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#define FXP_SCB_RUS_IDLE 0
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#define FXP_SCB_RUS_SUSPENDED 1
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#define FXP_SCB_RUS_NORESOURCES 2
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#define FXP_SCB_RUS_READY 4
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#define FXP_SCB_RUS_SUSP_NORBDS 9
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#define FXP_SCB_RUS_NORES_NORBDS 10
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#define FXP_SCB_RUS_READY_NORBDS 12
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#define FXP_SCB_CUS_IDLE 0
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#define FXP_SCB_CUS_SUSPENDED 1
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#define FXP_SCB_CUS_ACTIVE 2
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#define FXP_SCB_INTR_DISABLE 0x01 /* Disable all interrupts */
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#define FXP_SCB_INTR_SWI 0x02 /* Generate SWI */
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#define FXP_SCB_INTMASK_FCP 0x04
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#define FXP_SCB_INTMASK_ER 0x08
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#define FXP_SCB_INTMASK_RNR 0x10
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#define FXP_SCB_INTMASK_CNA 0x20
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#define FXP_SCB_INTMASK_FR 0x40
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#define FXP_SCB_INTMASK_CXTNO 0x80
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#define FXP_SCB_STATACK_FCP 0x01 /* Flow Control Pause */
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#define FXP_SCB_STATACK_ER 0x02 /* Early Receive */
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#define FXP_SCB_STATACK_SWI 0x04
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#define FXP_SCB_STATACK_MDI 0x08
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#define FXP_SCB_STATACK_RNR 0x10
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#define FXP_SCB_STATACK_CNA 0x20
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#define FXP_SCB_STATACK_FR 0x40
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#define FXP_SCB_STATACK_CXTNO 0x80
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#define FXP_SCB_COMMAND_CU_NOP 0x00
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#define FXP_SCB_COMMAND_CU_START 0x10
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#define FXP_SCB_COMMAND_CU_RESUME 0x20
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#define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40
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#define FXP_SCB_COMMAND_CU_DUMP 0x50
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#define FXP_SCB_COMMAND_CU_BASE 0x60
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#define FXP_SCB_COMMAND_CU_DUMPRESET 0x70
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#define FXP_SCB_COMMAND_RU_NOP 0
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#define FXP_SCB_COMMAND_RU_START 1
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#define FXP_SCB_COMMAND_RU_RESUME 2
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#define FXP_SCB_COMMAND_RU_ABORT 4
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#define FXP_SCB_COMMAND_RU_LOADHDS 5
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#define FXP_SCB_COMMAND_RU_BASE 6
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#define FXP_SCB_COMMAND_RU_RBDRESUME 7
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/*
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* Command block definitions
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*/
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struct fxp_cb_nop {
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void *fill[2];
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volatile u_int16_t cb_status;
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volatile u_int16_t cb_command;
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volatile u_int32_t link_addr;
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};
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struct fxp_cb_ias {
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void *fill[2];
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volatile u_int16_t cb_status;
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volatile u_int16_t cb_command;
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volatile u_int32_t link_addr;
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volatile u_int8_t macaddr[6];
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};
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/* I hate bit-fields :-( */
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struct fxp_cb_config {
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void *fill[2];
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volatile u_int16_t cb_status;
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volatile u_int16_t cb_command;
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volatile u_int32_t link_addr;
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volatile u_int byte_count:6,
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:2;
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volatile u_int rx_fifo_limit:4,
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tx_fifo_limit:3,
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:1;
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volatile u_int8_t adaptive_ifs;
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volatile u_int mwi_enable:1, /* 8,9 */
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type_enable:1, /* 8,9 */
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read_align_en:1, /* 8,9 */
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end_wr_on_cl:1, /* 8,9 */
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:4;
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volatile u_int rx_dma_bytecount:7,
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:1;
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volatile u_int tx_dma_bytecount:7,
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dma_mbce:1;
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volatile u_int late_scb:1, /* 7 */
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direct_dma_dis:1, /* 8,9 */
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tno_int_or_tco_en:1, /* 7,9 */
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ci_int:1,
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ext_txcb_dis:1, /* 8,9 */
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ext_stats_dis:1, /* 8,9 */
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keep_overrun_rx:1,
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save_bf:1;
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volatile u_int disc_short_rx:1,
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underrun_retry:2,
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:3,
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two_frames:1, /* 8,9 */
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dyn_tbd:1; /* 8,9 */
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volatile u_int mediatype:1, /* 7 */
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:6,
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csma_dis:1; /* 8,9 */
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volatile u_int tcp_udp_cksum:1, /* 9 */
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:3,
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vlan_tco:1, /* 8,9 */
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link_wake_en:1, /* 8,9 */
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arp_wake_en:1, /* 8 */
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mc_wake_en:1; /* 8 */
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volatile u_int :3,
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nsai:1,
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preamble_length:2,
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loopback:2;
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volatile u_int linear_priority:3, /* 7 */
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:5;
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volatile u_int linear_pri_mode:1, /* 7 */
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:3,
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interfrm_spacing:4;
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volatile u_int :8;
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volatile u_int :8;
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volatile u_int promiscuous:1,
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bcast_disable:1,
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wait_after_win:1, /* 8,9 */
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:1,
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ignore_ul:1, /* 8,9 */
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crc16_en:1, /* 9 */
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:1,
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crscdt:1;
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volatile u_int fc_delay_lsb:8; /* 8,9 */
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volatile u_int fc_delay_msb:8; /* 8,9 */
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volatile u_int stripping:1,
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padding:1,
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rcv_crc_xfer:1,
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long_rx_en:1, /* 8,9 */
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pri_fc_thresh:3, /* 8,9 */
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:1;
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volatile u_int ia_wake_en:1, /* 8 */
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magic_pkt_dis:1, /* 8,9,!9ER */
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tx_fc_dis:1, /* 8,9 */
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rx_fc_restop:1, /* 8,9 */
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rx_fc_restart:1, /* 8,9 */
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fc_filter:1, /* 8,9 */
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force_fdx:1,
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fdx_pin_en:1;
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volatile u_int :5,
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pri_fc_loc:1, /* 8,9 */
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multi_ia:1,
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:1;
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volatile u_int :3,
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mc_all:1,
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:4;
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};
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#define MAXMCADDR 80
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struct fxp_cb_mcs {
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struct fxp_cb_tx *next;
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struct mbuf *mb_head;
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volatile u_int16_t cb_status;
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volatile u_int16_t cb_command;
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volatile u_int32_t link_addr;
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volatile u_int16_t mc_cnt;
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volatile u_int8_t mc_addr[MAXMCADDR][6];
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};
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/*
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* Number of DMA segments in a TxCB. Note that this is carefully
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* chosen to make the total struct size an even power of two. It's
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* critical that no TxCB be split across a page boundry since
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* no attempt is made to allocate physically contiguous memory.
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*
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*/
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#ifdef __alpha__ /* XXX - should be conditional on pointer size */
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#define FXP_NTXSEG 28
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#else
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#define FXP_NTXSEG 29
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#endif
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struct fxp_tbd {
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volatile u_int32_t tb_addr;
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volatile u_int32_t tb_size;
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};
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struct fxp_cb_tx {
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struct fxp_cb_tx *next;
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struct mbuf *mb_head;
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volatile u_int16_t cb_status;
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volatile u_int16_t cb_command;
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volatile u_int32_t link_addr;
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volatile u_int32_t tbd_array_addr;
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volatile u_int16_t byte_count;
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volatile u_int8_t tx_threshold;
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volatile u_int8_t tbd_number;
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/*
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* The following structure isn't actually part of the TxCB,
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* unless the extended TxCB feature is being used. In this
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* case, the first two elements of the structure below are
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* fetched along with the TxCB.
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*/
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volatile struct fxp_tbd tbd[FXP_NTXSEG];
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};
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/*
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* Control Block (CB) definitions
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*/
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/* status */
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#define FXP_CB_STATUS_OK 0x2000
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#define FXP_CB_STATUS_C 0x8000
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/* commands */
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#define FXP_CB_COMMAND_NOP 0x0
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#define FXP_CB_COMMAND_IAS 0x1
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#define FXP_CB_COMMAND_CONFIG 0x2
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#define FXP_CB_COMMAND_MCAS 0x3
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#define FXP_CB_COMMAND_XMIT 0x4
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#define FXP_CB_COMMAND_RESRV 0x5
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#define FXP_CB_COMMAND_DUMP 0x6
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#define FXP_CB_COMMAND_DIAG 0x7
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/* command flags */
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#define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */
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#define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */
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#define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */
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#define FXP_CB_COMMAND_EL 0x8000 /* end of list */
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| 282 |
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/*
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* RFA definitions
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*/
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| 286 |
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struct fxp_rfa {
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volatile u_int16_t rfa_status;
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volatile u_int16_t rfa_control;
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volatile u_int8_t link_addr[4];
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volatile u_int8_t rbd_addr[4];
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volatile u_int16_t actual_size;
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volatile u_int16_t size;
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};
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| 294 |
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#define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */
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#define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */
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#define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */
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#define FXP_RFA_STATUS_TL 0x0020 /* type/length */
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#define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */
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#define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */
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#define FXP_RFA_STATUS_RNR 0x0200 /* no resources */
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#define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */
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#define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */
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#define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */
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#define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */
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| 305 |
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#define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */
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| 306 |
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#define FXP_RFA_CONTROL_H 0x10 /* header RFD */
|
| 307 |
|
|
#define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */
|
| 308 |
|
|
#define FXP_RFA_CONTROL_EL 0x8000 /* end of list */
|
| 309 |
|
|
|
| 310 |
|
|
/*
|
| 311 |
|
|
* Statistics dump area definitions
|
| 312 |
|
|
*/
|
| 313 |
|
|
struct fxp_stats {
|
| 314 |
|
|
volatile u_int32_t tx_good;
|
| 315 |
|
|
volatile u_int32_t tx_maxcols;
|
| 316 |
|
|
volatile u_int32_t tx_latecols;
|
| 317 |
|
|
volatile u_int32_t tx_underruns;
|
| 318 |
|
|
volatile u_int32_t tx_lostcrs;
|
| 319 |
|
|
volatile u_int32_t tx_deffered;
|
| 320 |
|
|
volatile u_int32_t tx_single_collisions;
|
| 321 |
|
|
volatile u_int32_t tx_multiple_collisions;
|
| 322 |
|
|
volatile u_int32_t tx_total_collisions;
|
| 323 |
|
|
volatile u_int32_t rx_good;
|
| 324 |
|
|
volatile u_int32_t rx_crc_errors;
|
| 325 |
|
|
volatile u_int32_t rx_alignment_errors;
|
| 326 |
|
|
volatile u_int32_t rx_rnr_errors;
|
| 327 |
|
|
volatile u_int32_t rx_overrun_errors;
|
| 328 |
|
|
volatile u_int32_t rx_cdt_errors;
|
| 329 |
|
|
volatile u_int32_t rx_shortframes;
|
| 330 |
|
|
volatile u_int32_t completion_status;
|
| 331 |
|
|
};
|
| 332 |
|
|
#define FXP_STATS_DUMP_COMPLETE 0xa005
|
| 333 |
|
|
#define FXP_STATS_DR_COMPLETE 0xa007
|
| 334 |
|
|
|
| 335 |
|
|
/*
|
| 336 |
|
|
* Serial EEPROM control register bits
|
| 337 |
|
|
*/
|
| 338 |
|
|
#define FXP_EEPROM_EESK 0x01 /* shift clock */
|
| 339 |
|
|
#define FXP_EEPROM_EECS 0x02 /* chip select */
|
| 340 |
|
|
#define FXP_EEPROM_EEDI 0x04 /* data in */
|
| 341 |
|
|
#define FXP_EEPROM_EEDO 0x08 /* data out */
|
| 342 |
|
|
|
| 343 |
|
|
/*
|
| 344 |
|
|
* Serial EEPROM opcodes, including start bit
|
| 345 |
|
|
*/
|
| 346 |
|
|
#define FXP_EEPROM_OPC_ERASE 0x4
|
| 347 |
|
|
#define FXP_EEPROM_OPC_WRITE 0x5
|
| 348 |
|
|
#define FXP_EEPROM_OPC_READ 0x6
|
| 349 |
|
|
|
| 350 |
|
|
/*
|
| 351 |
|
|
* Management Data Interface opcodes
|
| 352 |
|
|
*/
|
| 353 |
|
|
#define FXP_MDI_WRITE 0x1
|
| 354 |
|
|
#define FXP_MDI_READ 0x2
|
| 355 |
|
|
|
| 356 |
|
|
/*
|
| 357 |
|
|
* PHY device types
|
| 358 |
|
|
*/
|
| 359 |
|
|
#define FXP_PHY_DEVICE_MASK 0x3f00
|
| 360 |
|
|
#define FXP_PHY_SERIAL_ONLY 0x8000
|
| 361 |
|
|
#define FXP_PHY_NONE 0
|
| 362 |
|
|
#define FXP_PHY_82553A 1
|
| 363 |
|
|
#define FXP_PHY_82553C 2
|
| 364 |
|
|
#define FXP_PHY_82503 3
|
| 365 |
|
|
#define FXP_PHY_DP83840 4
|
| 366 |
|
|
#define FXP_PHY_80C240 5
|
| 367 |
|
|
#define FXP_PHY_80C24 6
|
| 368 |
|
|
#define FXP_PHY_82555 7
|
| 369 |
|
|
#define FXP_PHY_DP83840A 10
|
| 370 |
|
|
#define FXP_PHY_82555B 11
|
