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/*  cpu_asm.s
 *
 *  This file contains all assembly code for the Intel i386 implementation
 *  of RDBG.
 *
 * rdbg_cpu_asm.S,v 1.4 2002/04/18 22:24:27 joel Exp
 *
 */
 
#include 
#include 
#include 
 
        BEGIN_CODE
 
/*
 *  void copyback_data_cache_and_invalidate_instr_cache(addr, size)
 *
 *  This routine performs a copy of the data cache
 *  and invalidate the instruction cache
 */
 
        .p2align  5
        PUBLIC_VAR (copyback_data_cache_and_invalidate_instr_cache)
 
SYM (copyback_data_cache_and_invalidate_instr_cache):
        /* make sure the data changed is in the cache */
        sync
        /* r3 address to handle, r4 length in bytes */
        addi    r6, r0, PPC_CACHE_ALIGNMENT
        /* r5 = last address to handle */
        add     r5,r3,r4
        /* r3 = cache_align(r3, PPC_CACHE_ALIGNMENT) */
        subi    r0,r6,1
        andc    r3,r3,r0
        /* R4 = R3 = copy of first address */
        mr      r4,r3
        /*
         * Copyback data cache
         */
1:      cmplw   r4,r5    /* r4 >= r5 then done */
        dcbst   0,r4     /* flush (data cache bloc store) */
        add     r4,r4,r6 /* r4 = next cache line addr */
        blt     1b       /* end r4 >= r5 then done */
        sync            /* Wait for all dcbst to complete on bus */
        /*
         * invalidate instruction cache
         */
        /* R4 = fisrt address */
        mr      r4,r3
2:      cmplw   r4,r5    /* r4 >= r5 then done */
        icbi    0,r4     /* invalidate (instruction cache bloc invalidate) */
        add     r4,r4,r6 /* r4 = next cache line addr */
        blt     2b       /* end r4 >= r5 then done */
        sync             /* Wait for all icbi to complete on bus */
        isync
        blr
 
 
/*
 * void enterRdbg(void)
 *
 * This function perform a call to the exception SYSTEM call
 * It is used :
 *   1 - in the user code, to simulate a Breakpoint.
 *       (with justSaveContext = 0)
 *   2 - in the RDBG code, to push a ctx in the list.
 *       (with justSaveContext = 1)
 *
 * In most of case, it will be use as described in 1.
 * The 2nd possibility will be used by RDBG to obtain
 * its own ctx
 */
 
        PUBLIC_VAR (enterRdbg)
 
SYM (enterRdbg):
        sc
        blr
 
END_CODE
 
END

Line No.	Rev	Author	Line
1	1026	ivang	`/* cpu_asm.s`
2			`*`
3			`* This file contains all assembly code for the Intel i386 implementation`
4			`* of RDBG.`
5			`*`
6			`* rdbg_cpu_asm.S,v 1.4 2002/04/18 22:24:27 joel Exp`
7			`*`
8			`*/`
9
10			`#include`
11			`#include`
12			`#include`
13
14			`BEGIN_CODE`
15
16			`/*`
17			`* void copyback_data_cache_and_invalidate_instr_cache(addr, size)`
18			`*`
19			`* This routine performs a copy of the data cache`
20			`* and invalidate the instruction cache`
21			`*/`
22
23			`.p2align 5`
24			`PUBLIC_VAR (copyback_data_cache_and_invalidate_instr_cache)`
25
26			`SYM (copyback_data_cache_and_invalidate_instr_cache):`
27			`/* make sure the data changed is in the cache */`
28			`sync`
29			`/* r3 address to handle, r4 length in bytes */`
30			`addi r6, r0, PPC_CACHE_ALIGNMENT`
31			`/* r5 = last address to handle */`
32			`add r5,r3,r4`
33			`/* r3 = cache_align(r3, PPC_CACHE_ALIGNMENT) */`
34			`subi r0,r6,1`
35			`andc r3,r3,r0`
36			`/* R4 = R3 = copy of first address */`
37			`mr r4,r3`
38			`/*`
39			`* Copyback data cache`
40			`*/`
41			`1: cmplw r4,r5 /* r4 >= r5 then done */`
42			`dcbst 0,r4 /* flush (data cache bloc store) */`
43			`add r4,r4,r6 /* r4 = next cache line addr */`
44			`blt 1b /* end r4 >= r5 then done */`
45			`sync /* Wait for all dcbst to complete on bus */`
46			`/*`
47			`* invalidate instruction cache`
48			`*/`
49			`/* R4 = fisrt address */`
50			`mr r4,r3`
51			`2: cmplw r4,r5 /* r4 >= r5 then done */`
52			`icbi 0,r4 /* invalidate (instruction cache bloc invalidate) */`
53			`add r4,r4,r6 /* r4 = next cache line addr */`
54			`blt 2b /* end r4 >= r5 then done */`
55			`sync /* Wait for all icbi to complete on bus */`
56			`isync`
57			`blr`
58
59
60			`/*`
61			`* void enterRdbg(void)`
62			`*`
63			`* This function perform a call to the exception SYSTEM call`
64			`* It is used :`
65			`* 1 - in the user code, to simulate a Breakpoint.`
66			`* (with justSaveContext = 0)`
67			`* 2 - in the RDBG code, to push a ctx in the list.`
68			`* (with justSaveContext = 1)`
69			`*`
70			`* In most of case, it will be use as described in 1.`
71			`* The 2nd possibility will be used by RDBG to obtain`
72			`* its own ctx`
73			`*/`
74
75			`PUBLIC_VAR (enterRdbg)`
76
77			`SYM (enterRdbg):`
78			`sc`
79			`blr`
80
81			`END_CODE`
82
83			`END`

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[/] [or1k/] [trunk/] [rtems-20020807/] [c/] [src/] [librdbg/] [src/] [powerpc/] [rdbg_cpu_asm.S] - Blame information for rev 1765