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#if 0
 
; /* @(#)amd.ah 1.1 96/05/23 08:56:58, TEI */
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;                Initialization values for registers after RESET
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
:  /* amd.ah,v 1.3 2000/09/22 20:34:15 joel Exp */
;* File information and includes.
 
#endif
        .file   "amd.ah"
        .ident  "@(#)amd.ah     1.1 96/05/23 08:56:58, TEI"
 
 
 
;
;* AMD PROCESSOR SPECIFIC VALUES...
;
 
;
;* Processor revision levels...
;
 
; PRL values: 31-28   27-24
; Am29000       0        x
; Am29005       1       x
; Am29050       2       x
; Am29035       3       x
; Am29030       4       x
; Am29200       5       x
; Am29205       5       1x
; Am29240       6       0
; Manx          7       0
; Cougar        8       0
 
 
        .equ    AM29000_PRL,    0x00
 
        .equ    AM29005_PRL,    0x10
 
        .equ    AM29050_PRL,    0x20
 
        .equ    AM29035_PRL,    0x30
 
        .equ    AM29030_PRL,    0x40
 
        .equ    AM29200_PRL,    0x50
 
        .equ    AM29205_PRL,    0x58
 
        .equ    AM29240_PRL,    0x60
 
        .equ    AM29040_PRL,    0x70
 
        .equ    MANX_PRL,       0x70
 
        .equ    COUGAR_PRL,     0x80
 
;
;* data structures sizes.
;
        .equ    CFGINFO_SIZE,   16*4
 
        .equ    PGMINFO_SIZE,   16*4
 
        .equ    VARARGS_SPACE,  16*4
 
        .equ    WINDOWSIZE,     0x80
;
;* Am29027 Mode registers
;
 
        .equ    Am29027Mode1, 0x0fc00820
 
        .equ    Am29027Mode2, 0x00001375
 
 
 
;* Processor Based Equates and Defines
 
        .equ    SIG_SYNC,       -1
 
        .equ    ENABLE,         (SM)
 
        .equ    DISABLE,        (ENABLE | DI | DA)
 
        .equ    DISABLE_FZ,     (FZ | ENABLE | DI | DA)
 
        .equ    CLR_TRAP,       (FZ | DA)
 
        .equ    InitOPS,        (TD | SM | (3<
 
        .equ    InitCPS,        (TD | SM | (0<
 
        .equ    InitCPS1,       (TD | SM | (0<
 
        .equ    CPS_TMR,        (SM | (0<
 
        .equ    CPS_INT0,       (TD | SM | (0<
 
        .equ    CPS_TMRINT0,    (SM | (0<
 
        .equ    InitCFG,        0x0
 
        .equ    InitRBP,        (B0|B1|B2|B3|B4|B5)
 
        .equ    TMC_VALUE,      0xFFFFFF
 
        .equ    TMR_VALUE,      (IE | TMC_VALUE)
 
 
 
 
 
 
;* 29205 specific (internal) peripheral initialization constants.
 
; Current Processor Status (CPS) Register.
; Old Processor Status Register (OPS).
 
        .equ    DA,     0x00001
        .equ    DI,     0x00002
        .equ    IMShift,0x2
        .equ    SM,     0x00010
        .equ    PI,     0x00020
        .equ    PD,     0x00040
        .equ    WM,     0x00080
        .equ    RE,     0x00100
        .equ    LK,     0x00200
        .equ    FZ,     0x00400
        .equ    TU,     0x00800
        .equ    TP,     0x01000
        .equ    TE,     0x02000
        .equ    IP,     0x04000
        .equ    CA,     0x08000
        .equ    MM,     0x10000
        .equ    TD,     0x20000
 
; Configuration Register (CFG)
 
        .equ    CD,     0x01
        .equ    CP,     0x02
        .equ    BO,     0x04
        .equ    RV,     0x08
        .equ    VF,     0x10
        .equ    DW,     0x20
        .equ    CO,     0x40
        .equ    EE,     0x80
        .equ    IDShift,        8
        .equ    CFG_ID, 0x100
        .equ    ILShift,        9
        .equ    CFG_ILMask,     0x600
        .equ    DDShift,        11
        .equ    CFG_DD, 0x800
        .equ    DLShift,        12
        .equ    CFG_DLMask,     0x3000
        .equ    PCEShift,       14
        .equ    CFG_PCE,        0x4000
        .equ    PMBShift,       16
        .equ    D16,    0x8000
        .equ    TBOShift,       23
        .equ    PRLShift, 24
 
; Channel Control Register (CHC)
 
        .equ    CV, 0x1
        .equ    NN, 0x2
        .equ    TRShift, 2
        .equ    TF, 0x400
        .equ    PER, 0x800
        .equ    LA, 0x1000
        .equ    ST, 0x2000
        .equ    ML, 0x4000
        .equ    LS, 0x8000
        .equ    CRShift, 16
        .equ    CNTLShift, 24
        .equ    CEShift, 31
        .equ    WBERShift, 31
 
; Register Bank Protect (RBP)
        .equ    B0, 0x1
        .equ    B1, 0x2
        .equ    B2, 0x4
        .equ    B3, 0x8
        .equ    B4, 0x10
        .equ    B5, 0x20
        .equ    B6, 0x40
        .equ    B7, 0x80
        .equ    B8, 0x100
        .equ    B9, 0x200
        .equ    B10, 0x400
        .equ    B11, 0x800
        .equ    B12, 0x1000
        .equ    B13, 0x2000
        .equ    B14, 0x4000
        .equ    B15, 0x8000
 
; Timer Counter
 
        .equ    TCVMask, 0xffffff
 
; Timer Reload Register
 
        .equ    IE, 0x1000000
        .equ    IN, 0x2000000
        .equ    OV, 0x4000000
        .equ    TRVMAsk, 0xffffff
 
; MMU Configuration
 
        .equ    PSShift, 8
        .equ    PS0Shift, 8
        .equ    PS1Shift, 12
 
; LRU Recommendation (LRU)
        .equ    LRUMask, 0xff
 
; Reason Vector (RSN)
        .equ    RSNMask, 0xff
 
; Region Mapping Address (RMA0 | RMA1)
        .equ    PBAMask,0xffff
        .equ    VBAShift, 16
 
; Region Mapping Control (RMC0 | RMC1)
        .equ    TIDMask, 0xff
        .equ    RMC_UE, 0x100
        .equ    RMC_UW, 0x200
        .equ    RMC_UR, 0x400
        .equ    RMC_SE, 0x800
        .equ    RMC_SW, 0x1000
        .equ    RMC_SR, 0x2000
        .equ    RMC_VE, 0x4000
        .equ    RMC_IO, 0x10000
        .equ    RGSShift, 17
        .equ    RMC_PGMShift, 22
 
; Instruction breakpoint Control (IBC0 | IBC1)
        .equ    BPIDMask, 0xff
        .equ    BTE, 0x100
        .equ    BRM, 0x200
        .equ    IBC_BSY, 0x400
        .equ    BEN, 0x800
        .equ    BHO, 0x1000
 
; Cache Data Register (CDR)
        .equ    CDR_US, 0x1
        .equ    P, 0x2
        .equ    CDR_V, 0x4
        .equ    IATAGShift, 20
 
; Cache Interface Register (CIR)
        .equ    CPTRShift, 2
        .equ    CIR_RW, 0x1000000
        .equ    FSELShift, 28
 
; Indirect Pointer A, B, C (IPA, IPB, IPC)
        .equ    IPShift, 2
 
; ALU Status (ALU)
        .equ    FCMask, 0x1F
        .equ    BPShift, 5
        .equ    C, 0x80
        .equ    Z, 0x100
        .equ    N, 0x200
        .equ    ALU_V, 0x400
        .equ    DF, 0x800
 
; Byte Pointer
        .equ    BPMask, 0x3
 
; Load/Store Count Remaining (CR)
        .equ    CRMask, 0xff
 
; Floating Point Environment (FPE)
        .equ    NM, 0x1
        .equ    RM, 0x2
        .equ    VM, 0x4
        .equ    UM, 0x8
        .equ    XM, 0x10
        .equ    DM, 0x20
        .equ    FRMShift, 6
        .equ    FF, 0x100
        .equ    ACFShift, 9
 
; Integer Environment (INTE)
        .equ    MO, 0x1
        .equ    DO, 0x2
 
; Floating Point Status (FPS)
        .equ    NS, 0x1
        .equ    RS, 0x2
        .equ    VS, 0x4
        .equ    FPS_US, 0x8
        .equ    XS, 0x10
        .equ    DS, 0x20
        .equ    NT, 0x100
        .equ    RT, 0x200
        .equ    VT, 0x400
        .equ    UT, 0x800
        .equ    XT, 0x1000
        .equ    DT, 0x2000
 
; Exception Opcode (EXOP)
        .equ    IOPMask, 0xff
 
; TLB Entry Word 0
;       .equ    TIDMask, 0xff   already defined above
        .equ    TLB_UE, 0x100
        .equ    TLB_UW, 0x200
        .equ    TLB_UR, 0x400
        .equ    TLB_SE, 0x800
        .equ    TLB_SW, 0x1000
        .equ    TLB_SR, 0x2000
        .equ    TLB_VE, 0x4000
        .equ    VTAGShift, 15
 
; TLB Entry Word 1
        .equ    TLB_IO, 0x1
        .equ    U, 0x2
        .equ    TLB_PGMShift, 6
        .equ    RPNShift, 10
 
; Am29200 ROM Control bits.
        .equ    RMCT_DW0Shift, 29
        .equ    RMCT_DW1Shift, 21
        .equ    RMCT_DW2Shift, 13
        .equ    RMCT_DW3Shift, 5
 
; Am29200 DRAM Control bits.
        .equ    DW3, (1<<18)
        .equ    DW2, (1<<22)
        .equ    DW1, (1<<26)
        .equ    DW0, (1<<30)
 
        ; Internal peripheral address assignments.
        .equ    RMCT, 0x80000000
        .equ    RMCF, 0x80000004
        .equ    DRCT, 0x80000008
        .equ    DRCF, 0x8000000C
        .equ    DRM0, 0x80000010
        .equ    DRM1, 0x80000014
        .equ    DRM2, 0x80000018
        .equ    DRM3, 0x8000001C
        .equ    PIACT0, 0x80000020
        .equ    PIACT1, 0x80000020
        .equ    ICT, 0x80000028
        .equ    DMCT0, 0x80000030
        .equ    DMAD0, 0x80000034
        .ifdef  revA
        .equ    TAD0, 0x80000036
        .equ    TCN0, 0x8000003A
        .else
        .equ    TAD0, 0x80000070        ; default
        .equ    TCN0, 0x8000003C        ; default
        .endif
        .equ    DMCN0, 0x80000038
        .equ    DMCT1, 0x80000040
        .equ    DMAD1, 0x80000044
        .equ    DMCN1, 0x80000048
        .equ    SPCT, 0x80000080
        .equ    SPST, 0x80000084
        .equ    SPTH, 0x80000088
        .equ    SPRB, 0x8000008C
        .equ    BAUD, 0x80000090
        .equ    PPCT, 0x800000C0
        .equ    PPST, 0x800000C1
        .equ    PPDT, 0x800000C4
        .equ    POCT, 0x800000D0
        .equ    PIN, 0x800000D4
        .equ    POUT, 0x800000D8
        .equ    POEN, 0x800000DC
        .equ    VCT, 0x800000E0
        .equ    TOP, 0x800000E4
        .equ    SIDE, 0x800000E8
        .equ    VDT, 0x800000EC
 
        ; Interrupt Controller Register bits.
        .equ    TXDI,   (1<<5)
        .equ    RXDI,   (1<<6)
        .equ    RXSI,   (1<<7)
        .equ    PPI,    (1<<11)
        .equ    DMA1I,  (1<<13)
        .equ    DMA0I,  (1<<14)
        .equ    IOPIMask,       (0xFF<<16)
        .equ    VDI,    (1<<27)
        .equ    ICT200_I,  (TXDI|RXDI|RXSI|PPI|DMA1I|DMA0I|IOPIMask|VDI)
        .equ    ICT205_I,  (TXDI|RXDI|RXSI|PPI|DMA1I|DMA0I|IOPIMask|VDI)
 
        ; Serial port Initialization bits
        .equ    NO_PARITY,      0
 
 
        ; SPST bits
        .equ    THREShift, 22
 
;* REGISTER Addresses
 
        .equ    ROMCntlRegAddr,         0x80000000
 
        .equ    ROMCfgRegAddr,          0x80000004
 
        .equ    DRAMCntlRegAddr,        0x80000008
 
        .equ    DRAMCfgRegAddr,         0x8000000C
 
        .equ    DRAMMap0RegAddr,        0x80000010
 
        .equ    DRAMMap1RegAddr,        0x80000014
 
        .equ    DRAMMap2RegAddr,        0x80000018
 
        .equ    DRAMMap3RegAddr,        0x8000001C
 
        .equ    PIACntl0RegAddr,        0x80000020
 
        .equ    PIACntl1RegAddr,        0x80000024
 
        .equ    INTRCntlRegAddr,        0x80000028
 
        .equ    DMACntl0RegAddr,        0x80000030
 
        .equ    DMACntl1RegAddr,        0x80000040
 
        .equ    SERPortCntlRegAddr,     0x80000080
 
        .equ    SERPortStatRegAddr,     0x80000084
 
        .equ    SERPortTHLDRegAddr,     0x80000088
 
        .equ    SERPortRbufRegAddr,     0x8000008C
 
        .equ    SERPortBaudRegAddr,     0x80000090
 
        .equ    PARPortCntlRegAddr,     0x800000C0
 
        .equ    PIOCntlRegAddr,         0x800000D0
 
        .equ    PIOInpRegAddr,          0x800000D4
 
        .equ    PIOOutRegAddr,          0x800000D8
 
        .equ    PIOOutEnaRegAddr,       0x800000DC
 
        .equ    VCTCntlRegAddr,         0x800000E0
 
;
;* Control constants
;
 
;* AM29030 Timer related constants.
 
        .equ    TMR_IE,                 0x01000000
 
        .equ    TMR_IN,                 0x02000000
 
        .equ    TMR_OV,                 0x04000000
 
        .equ    TMC_INITCNT,            1613
 
;
;* System initialization values.
;
 
        .equ    __os_version,           0x0001          ;
 
        .equ    STACKSize,              0x8000          ;
 
        .equ    PGMExecMode,            0x0000          ;
 
        .equ    TSTCK_OFST,             28 * 4
 
        .equ    CSTCK_OFST,             29 * 4
 
        .equ    TMSTCK_OFST,            30 * 4
 
        .equ    CMSTCK_OFST,            31 * 4
 
        .equ    CTXSW_OK,               0xA55A          ; ctx switch ok
 
        .set    NV_STARTOFST,           0x20            ; 32 bytes
 
        .set    NV_BAUDOFST,            0x00            ; 00 bytes
 
        .set    reg_cir,                29
 
        .set    reg_cdr,                30
 
        .equ    MSG_BUFSIZE,            0x1000          ; serial buffer size
 
        .equ    ILLOPTRAP,              0
 
        .equ    UATRAP,                 1
 
        .equ    PVTRAP,                 5
 
        .equ    UITLBMISSTRAP,          8
 
        .equ    UDTLBMISSTRAP,          9
 
        .equ    TIMERTRAP,              14
 
        .equ    TRACETRAP,              15
 
        .equ    XLINXTRAP,              16
 
        .equ    SERIALTRAP,             17
 
        .equ    SLOWTMRTRAP,            18
 
        .equ    PORTTRAP,               19
 
        .equ    SVSCTRAP,               80
 
        .equ    SVSCTRAP1,              81
 
        .equ    V_CACHETRAP,            66              ;
 
        .equ    V_SETSERVICE,           67              ;
 
        .equ    INIT_TIMER,             100
 
        .equ    DISABLE_TIMER,          101
 
        .equ    GET_TIMER,              102
 
        .equ    CLEAR_TIMER,            103
 
        .equ    V_SPILL,                64
 
        .equ    V_FILL,                 65
 
        .equ    SIGDFL,                 105

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[/] [or1k/] [trunk/] [rtems-20020807/] [cpukit/] [score/] [cpu/] [a29k/] [amd.ah] - Blame information for rev 1026

Line No.	Rev	Author	Line
1	1026	ivang	`#if 0`
2
3			`; /* @(#)amd.ah 1.1 96/05/23 08:56:58, TEI */`
4			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
5			`; Initialization values for registers after RESET`
6			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
7			`;`
8			`: /* amd.ah,v 1.3 2000/09/22 20:34:15 joel Exp */`
9			`;* File information and includes.`
10
11			`#endif`
12			`.file "amd.ah"`
13			`.ident "@(#)amd.ah 1.1 96/05/23 08:56:58, TEI"`
14
15
16
17			`;`
18			`;* AMD PROCESSOR SPECIFIC VALUES...`
19			`;`
20
21			`;`
22			`;* Processor revision levels...`
23			`;`
24
25			`; PRL values: 31-28 27-24`
26			`; Am29000 0 x`
27			`; Am29005 1 x`
28			`; Am29050 2 x`
29			`; Am29035 3 x`
30			`; Am29030 4 x`
31			`; Am29200 5 x`
32			`; Am29205 5 1x`
33			`; Am29240 6 0`
34			`; Manx 7 0`
35			`; Cougar 8 0`
36
37
38			`.equ AM29000_PRL, 0x00`
39
40			`.equ AM29005_PRL, 0x10`
41
42			`.equ AM29050_PRL, 0x20`
43
44			`.equ AM29035_PRL, 0x30`
45
46			`.equ AM29030_PRL, 0x40`
47
48			`.equ AM29200_PRL, 0x50`
49
50			`.equ AM29205_PRL, 0x58`
51
52			`.equ AM29240_PRL, 0x60`
53
54			`.equ AM29040_PRL, 0x70`
55
56			`.equ MANX_PRL, 0x70`
57
58			`.equ COUGAR_PRL, 0x80`
59
60			`;`
61			`;* data structures sizes.`
62			`;`
63			`.equ CFGINFO_SIZE, 16*4`
64
65			`.equ PGMINFO_SIZE, 16*4`
66
67			`.equ VARARGS_SPACE, 16*4`
68
69			`.equ WINDOWSIZE, 0x80`
70			`;`
71			`;* Am29027 Mode registers`
72			`;`
73
74			`.equ Am29027Mode1, 0x0fc00820`
75
76			`.equ Am29027Mode2, 0x00001375`
77
78
79
80			`;* Processor Based Equates and Defines`
81
82			`.equ SIG_SYNC, -1`
83
84			`.equ ENABLE, (SM)`
85
86			`.equ DISABLE, (ENABLE \| DI \| DA)`
87
88			`.equ DISABLE_FZ, (FZ \| ENABLE \| DI \| DA)`
89
90			`.equ CLR_TRAP, (FZ \| DA)`
91
92			`.equ InitOPS, (TD \| SM \| (3<`
93
94			`.equ InitCPS, (TD \| SM \| (0<`
95
96			`.equ InitCPS1, (TD \| SM \| (0<`
97
98			`.equ CPS_TMR, (SM \| (0<`
99
100			`.equ CPS_INT0, (TD \| SM \| (0<`
101
102			`.equ CPS_TMRINT0, (SM \| (0<`
103
104			`.equ InitCFG, 0x0`
105
106			`.equ InitRBP, (B0\|B1\|B2\|B3\|B4\|B5)`
107
108			`.equ TMC_VALUE, 0xFFFFFF`
109
110			`.equ TMR_VALUE, (IE \| TMC_VALUE)`
111
112
113
114
115
116
117			`;* 29205 specific (internal) peripheral initialization constants.`
118
119			`; Current Processor Status (CPS) Register.`
120			`; Old Processor Status Register (OPS).`
121
122			`.equ DA, 0x00001`
123			`.equ DI, 0x00002`
124			`.equ IMShift,0x2`
125			`.equ SM, 0x00010`
126			`.equ PI, 0x00020`
127			`.equ PD, 0x00040`
128			`.equ WM, 0x00080`
129			`.equ RE, 0x00100`
130			`.equ LK, 0x00200`
131			`.equ FZ, 0x00400`
132			`.equ TU, 0x00800`
133			`.equ TP, 0x01000`
134			`.equ TE, 0x02000`
135			`.equ IP, 0x04000`
136			`.equ CA, 0x08000`
137			`.equ MM, 0x10000`
138			`.equ TD, 0x20000`
139
140			`; Configuration Register (CFG)`
141
142			`.equ CD, 0x01`
143			`.equ CP, 0x02`
144			`.equ BO, 0x04`
145			`.equ RV, 0x08`
146			`.equ VF, 0x10`
147			`.equ DW, 0x20`
148			`.equ CO, 0x40`
149			`.equ EE, 0x80`
150			`.equ IDShift, 8`
151			`.equ CFG_ID, 0x100`
152			`.equ ILShift, 9`
153			`.equ CFG_ILMask, 0x600`
154			`.equ DDShift, 11`
155			`.equ CFG_DD, 0x800`
156			`.equ DLShift, 12`
157			`.equ CFG_DLMask, 0x3000`
158			`.equ PCEShift, 14`
159			`.equ CFG_PCE, 0x4000`
160			`.equ PMBShift, 16`
161			`.equ D16, 0x8000`
162			`.equ TBOShift, 23`
163			`.equ PRLShift, 24`
164
165			`; Channel Control Register (CHC)`
166
167			`.equ CV, 0x1`
168			`.equ NN, 0x2`
169			`.equ TRShift, 2`
170			`.equ TF, 0x400`
171			`.equ PER, 0x800`
172			`.equ LA, 0x1000`
173			`.equ ST, 0x2000`
174			`.equ ML, 0x4000`
175			`.equ LS, 0x8000`
176			`.equ CRShift, 16`
177			`.equ CNTLShift, 24`
178			`.equ CEShift, 31`
179			`.equ WBERShift, 31`
180
181			`; Register Bank Protect (RBP)`
182			`.equ B0, 0x1`
183			`.equ B1, 0x2`
184			`.equ B2, 0x4`
185			`.equ B3, 0x8`
186			`.equ B4, 0x10`
187			`.equ B5, 0x20`
188			`.equ B6, 0x40`
189			`.equ B7, 0x80`
190			`.equ B8, 0x100`
191			`.equ B9, 0x200`
192			`.equ B10, 0x400`
193			`.equ B11, 0x800`
194			`.equ B12, 0x1000`
195			`.equ B13, 0x2000`
196			`.equ B14, 0x4000`
197			`.equ B15, 0x8000`
198
199			`; Timer Counter`
200
201			`.equ TCVMask, 0xffffff`
202
203			`; Timer Reload Register`
204
205			`.equ IE, 0x1000000`
206			`.equ IN, 0x2000000`
207			`.equ OV, 0x4000000`
208			`.equ TRVMAsk, 0xffffff`
209
210			`; MMU Configuration`
211
212			`.equ PSShift, 8`
213			`.equ PS0Shift, 8`
214			`.equ PS1Shift, 12`
215
216			`; LRU Recommendation (LRU)`
217			`.equ LRUMask, 0xff`
218
219			`; Reason Vector (RSN)`
220			`.equ RSNMask, 0xff`
221
222			`; Region Mapping Address (RMA0 \| RMA1)`
223			`.equ PBAMask,0xffff`
224			`.equ VBAShift, 16`
225
226			`; Region Mapping Control (RMC0 \| RMC1)`
227			`.equ TIDMask, 0xff`
228			`.equ RMC_UE, 0x100`
229			`.equ RMC_UW, 0x200`
230			`.equ RMC_UR, 0x400`
231			`.equ RMC_SE, 0x800`
232			`.equ RMC_SW, 0x1000`
233			`.equ RMC_SR, 0x2000`
234			`.equ RMC_VE, 0x4000`
235			`.equ RMC_IO, 0x10000`
236			`.equ RGSShift, 17`
237			`.equ RMC_PGMShift, 22`
238
239			`; Instruction breakpoint Control (IBC0 \| IBC1)`
240			`.equ BPIDMask, 0xff`
241			`.equ BTE, 0x100`
242			`.equ BRM, 0x200`
243			`.equ IBC_BSY, 0x400`
244			`.equ BEN, 0x800`
245			`.equ BHO, 0x1000`
246
247			`; Cache Data Register (CDR)`
248			`.equ CDR_US, 0x1`
249			`.equ P, 0x2`
250			`.equ CDR_V, 0x4`
251			`.equ IATAGShift, 20`
252
253			`; Cache Interface Register (CIR)`
254			`.equ CPTRShift, 2`
255			`.equ CIR_RW, 0x1000000`
256			`.equ FSELShift, 28`
257
258			`; Indirect Pointer A, B, C (IPA, IPB, IPC)`
259			`.equ IPShift, 2`
260
261			`; ALU Status (ALU)`
262			`.equ FCMask, 0x1F`
263			`.equ BPShift, 5`
264			`.equ C, 0x80`
265			`.equ Z, 0x100`
266			`.equ N, 0x200`
267			`.equ ALU_V, 0x400`
268			`.equ DF, 0x800`
269
270			`; Byte Pointer`
271			`.equ BPMask, 0x3`
272
273			`; Load/Store Count Remaining (CR)`
274			`.equ CRMask, 0xff`
275
276			`; Floating Point Environment (FPE)`
277			`.equ NM, 0x1`
278			`.equ RM, 0x2`
279			`.equ VM, 0x4`
280			`.equ UM, 0x8`
281			`.equ XM, 0x10`
282			`.equ DM, 0x20`
283			`.equ FRMShift, 6`
284			`.equ FF, 0x100`
285			`.equ ACFShift, 9`
286
287			`; Integer Environment (INTE)`
288			`.equ MO, 0x1`
289			`.equ DO, 0x2`
290
291			`; Floating Point Status (FPS)`
292			`.equ NS, 0x1`
293			`.equ RS, 0x2`
294			`.equ VS, 0x4`
295			`.equ FPS_US, 0x8`
296			`.equ XS, 0x10`
297			`.equ DS, 0x20`
298			`.equ NT, 0x100`
299			`.equ RT, 0x200`
300			`.equ VT, 0x400`
301			`.equ UT, 0x800`
302			`.equ XT, 0x1000`
303			`.equ DT, 0x2000`
304
305			`; Exception Opcode (EXOP)`
306			`.equ IOPMask, 0xff`
307
308			`; TLB Entry Word 0`
309			`; .equ TIDMask, 0xff already defined above`
310			`.equ TLB_UE, 0x100`
311			`.equ TLB_UW, 0x200`
312			`.equ TLB_UR, 0x400`
313			`.equ TLB_SE, 0x800`
314			`.equ TLB_SW, 0x1000`
315			`.equ TLB_SR, 0x2000`
316			`.equ TLB_VE, 0x4000`
317			`.equ VTAGShift, 15`
318
319			`; TLB Entry Word 1`
320			`.equ TLB_IO, 0x1`
321			`.equ U, 0x2`
322			`.equ TLB_PGMShift, 6`
323			`.equ RPNShift, 10`
324
325			`; Am29200 ROM Control bits.`
326			`.equ RMCT_DW0Shift, 29`
327			`.equ RMCT_DW1Shift, 21`
328			`.equ RMCT_DW2Shift, 13`
329			`.equ RMCT_DW3Shift, 5`
330
331			`; Am29200 DRAM Control bits.`
332			`.equ DW3, (1<<18)`
333			`.equ DW2, (1<<22)`
334			`.equ DW1, (1<<26)`
335			`.equ DW0, (1<<30)`
336
337			`; Internal peripheral address assignments.`
338			`.equ RMCT, 0x80000000`
339			`.equ RMCF, 0x80000004`
340			`.equ DRCT, 0x80000008`
341			`.equ DRCF, 0x8000000C`
342			`.equ DRM0, 0x80000010`
343			`.equ DRM1, 0x80000014`
344			`.equ DRM2, 0x80000018`
345			`.equ DRM3, 0x8000001C`
346			`.equ PIACT0, 0x80000020`
347			`.equ PIACT1, 0x80000020`
348			`.equ ICT, 0x80000028`
349			`.equ DMCT0, 0x80000030`
350			`.equ DMAD0, 0x80000034`
351			`.ifdef revA`
352			`.equ TAD0, 0x80000036`
353			`.equ TCN0, 0x8000003A`
354			`.else`
355			`.equ TAD0, 0x80000070 ; default`
356			`.equ TCN0, 0x8000003C ; default`
357			`.endif`
358			`.equ DMCN0, 0x80000038`
359			`.equ DMCT1, 0x80000040`
360			`.equ DMAD1, 0x80000044`
361			`.equ DMCN1, 0x80000048`
362			`.equ SPCT, 0x80000080`
363			`.equ SPST, 0x80000084`
364			`.equ SPTH, 0x80000088`
365			`.equ SPRB, 0x8000008C`
366			`.equ BAUD, 0x80000090`
367			`.equ PPCT, 0x800000C0`
368			`.equ PPST, 0x800000C1`
369			`.equ PPDT, 0x800000C4`
370			`.equ POCT, 0x800000D0`
371			`.equ PIN, 0x800000D4`
372			`.equ POUT, 0x800000D8`
373			`.equ POEN, 0x800000DC`
374			`.equ VCT, 0x800000E0`
375			`.equ TOP, 0x800000E4`
376			`.equ SIDE, 0x800000E8`
377			`.equ VDT, 0x800000EC`
378
379			`; Interrupt Controller Register bits.`
380			`.equ TXDI, (1<<5)`
381			`.equ RXDI, (1<<6)`
382			`.equ RXSI, (1<<7)`
383			`.equ PPI, (1<<11)`
384			`.equ DMA1I, (1<<13)`
385			`.equ DMA0I, (1<<14)`
386			`.equ IOPIMask, (0xFF<<16)`
387			`.equ VDI, (1<<27)`
388			`.equ ICT200_I, (TXDI\|RXDI\|RXSI\|PPI\|DMA1I\|DMA0I\|IOPIMask\|VDI)`
389			`.equ ICT205_I, (TXDI\|RXDI\|RXSI\|PPI\|DMA1I\|DMA0I\|IOPIMask\|VDI)`
390
391			`; Serial port Initialization bits`
392			`.equ NO_PARITY, 0`
393
394
395			`; SPST bits`
396			`.equ THREShift, 22`
397
398			`;* REGISTER Addresses`
399
400			`.equ ROMCntlRegAddr, 0x80000000`
401
402			`.equ ROMCfgRegAddr, 0x80000004`
403
404			`.equ DRAMCntlRegAddr, 0x80000008`
405
406			`.equ DRAMCfgRegAddr, 0x8000000C`
407
408			`.equ DRAMMap0RegAddr, 0x80000010`
409
410			`.equ DRAMMap1RegAddr, 0x80000014`
411
412			`.equ DRAMMap2RegAddr, 0x80000018`
413
414			`.equ DRAMMap3RegAddr, 0x8000001C`
415
416			`.equ PIACntl0RegAddr, 0x80000020`
417
418			`.equ PIACntl1RegAddr, 0x80000024`
419
420			`.equ INTRCntlRegAddr, 0x80000028`
421
422			`.equ DMACntl0RegAddr, 0x80000030`
423
424			`.equ DMACntl1RegAddr, 0x80000040`
425
426			`.equ SERPortCntlRegAddr, 0x80000080`
427
428			`.equ SERPortStatRegAddr, 0x80000084`
429
430			`.equ SERPortTHLDRegAddr, 0x80000088`
431
432			`.equ SERPortRbufRegAddr, 0x8000008C`
433
434			`.equ SERPortBaudRegAddr, 0x80000090`
435
436			`.equ PARPortCntlRegAddr, 0x800000C0`
437
438			`.equ PIOCntlRegAddr, 0x800000D0`
439
440			`.equ PIOInpRegAddr, 0x800000D4`
441
442			`.equ PIOOutRegAddr, 0x800000D8`
443
444			`.equ PIOOutEnaRegAddr, 0x800000DC`
445
446			`.equ VCTCntlRegAddr, 0x800000E0`
447
448			`;`
449			`;* Control constants`
450			`;`
451
452			`;* AM29030 Timer related constants.`
453
454			`.equ TMR_IE, 0x01000000`
455
456			`.equ TMR_IN, 0x02000000`
457
458			`.equ TMR_OV, 0x04000000`
459
460			`.equ TMC_INITCNT, 1613`
461
462			`;`
463			`;* System initialization values.`
464			`;`
465
466			`.equ __os_version, 0x0001 ;`
467
468			`.equ STACKSize, 0x8000 ;`
469
470			`.equ PGMExecMode, 0x0000 ;`
471
472			`.equ TSTCK_OFST, 28 * 4`
473
474			`.equ CSTCK_OFST, 29 * 4`
475
476			`.equ TMSTCK_OFST, 30 * 4`
477
478			`.equ CMSTCK_OFST, 31 * 4`
479
480			`.equ CTXSW_OK, 0xA55A ; ctx switch ok`
481
482			`.set NV_STARTOFST, 0x20 ; 32 bytes`
483
484			`.set NV_BAUDOFST, 0x00 ; 00 bytes`
485
486			`.set reg_cir, 29`
487
488			`.set reg_cdr, 30`
489
490			`.equ MSG_BUFSIZE, 0x1000 ; serial buffer size`
491
492			`.equ ILLOPTRAP, 0`
493
494			`.equ UATRAP, 1`
495
496			`.equ PVTRAP, 5`
497
498			`.equ UITLBMISSTRAP, 8`
499
500			`.equ UDTLBMISSTRAP, 9`
501
502			`.equ TIMERTRAP, 14`
503
504			`.equ TRACETRAP, 15`
505
506			`.equ XLINXTRAP, 16`
507
508			`.equ SERIALTRAP, 17`
509
510			`.equ SLOWTMRTRAP, 18`
511
512			`.equ PORTTRAP, 19`
513
514			`.equ SVSCTRAP, 80`
515
516			`.equ SVSCTRAP1, 81`
517
518			`.equ V_CACHETRAP, 66 ;`
519
520			`.equ V_SETSERVICE, 67 ;`
521
522			`.equ INIT_TIMER, 100`
523
524			`.equ DISABLE_TIMER, 101`
525
526			`.equ GET_TIMER, 102`
527
528			`.equ CLEAR_TIMER, 103`
529
530			`.equ V_SPILL, 64`
531
532			`.equ V_FILL, 65`
533
534			`.equ SIGDFL, 105`