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/*
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* This file contains all assembly code for the i960 port of RTEMS.
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* cpu_asm.S,v 1.8 2001/01/03 16:32:23 joel Exp
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*/
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.data
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_ISR_reg_save:
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.word 0
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.text
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/*
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* Format of i960ca Register structure
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*/
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.set REG_R0_PFP , 0 # (r0) Previous Frame Pointer
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.set REG_R1_SP , REG_R0_PFP+4 # (r1) Stack Pointer
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.set REG_PC , REG_R1_SP+4 # (pc) Processor Controls
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.set REG_G8 , REG_PC+4 # (g8) Global Register 8
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.set REG_G9 , REG_G8+4 # (g9) Global Register 9
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.set REG_G10 , REG_G9+4 # (g10) Global Register 10
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.set REG_G11 , REG_G10+4 # (g11) Global Register 11
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.set REG_G12 , REG_G11+4 # (g12) Global Register 12
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.set REG_G13 , REG_G12+4 # (g13) Global Register 13
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.set REG_G14 , REG_G13+4 # (g14) Global Register 14
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.set REG_G15_FP , REG_G14+4 # (g15) Global Register 15
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.set SIZE_REGS , REG_G15_FP+4 # size of cpu_context_registers
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# structure
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/*
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* void _CPU_Context_switch( run_context, heir_context )
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*
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* This routine performs a normal non-FP context.
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*/
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.align 4
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.globl __CPU_Context_switch
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__CPU_Context_switch:
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modpc 0,0,g2 # get old intr level (PC)
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st g2,REG_PC(g0) # save pc
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stq g8,REG_G8(g0) # save g8-g11
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stq g12,REG_G12(g0) # save g12-g15
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stl pfp,REG_R0_PFP(g0) # save pfp, sp
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restore: flushreg # flush register cache
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ldconst 0x001f0000,g2 # g2 = PC mask
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ld REG_PC(g1),g3 # thread->Regs.pc = pc;
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ldq REG_G12(g1),g12 # restore g12-g15
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ldl REG_R0_PFP(g1),pfp # restore pfp, sp
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ldq REG_G8(g1),g8 # restore g8-g11
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modpc 0,g2,g3 # restore PC register
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ret
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/*
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* void _CPU_Context_restore( new_context )
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*
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* This routine performs a normal non-FP context.
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*/
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.globl __CPU_Context_restore
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__CPU_Context_restore:
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mov g0,g1 # g0 = _Thread_executing
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b restore
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/*PAGE
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* void _CPU_Context_save_fp_context( &fp_context_ptr )
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* void _CPU_Context_restore_fp_context( &fp_context_ptr )
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*
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* There is currently no hardware floating point for the i960.
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*/
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.globl __CPU_Context_save_fp
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.globl __CPU_Context_restore_fp
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__CPU_Context_save_fp:
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__CPU_Context_restore_fp:
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#if ( I960_HAS_FPU == 1 )
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#error "Floating point support for i960 family has been implemented!!!"
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#endif
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ret
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/*PAGE
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* void __ISR_Handler()
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*
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* This routine provides the RTEMS interrupt management.
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*
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* Input parameters: NONE
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*
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* Output parameters: NONE
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*
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* NOTE:
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* Upon entry, the supervisor stack will contain a stack frame
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* back to the interrupted thread and the interrupt stack will contain
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* an interrupt stack frame. If dispatching is enabled, this
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* is the outer most interrupt, and (a context switch is necessary or
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* the current thread has signals), then set up the supervisor stack to
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* transfer control to the interrupt dispatcher.
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*/
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.globl __ISR_Handler
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__ISR_Handler:
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#ldconst 1,r8
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#modpc 0,r8,r8 # enable tracing
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# r4 = &_Thread_Dispatch_disable_level
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ld __Thread_Dispatch_disable_level,r4
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movl g0,r8 # save g0-g1
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ld -16+8(fp),g0 # g0 = vector number
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movl g2,r10 # save g2-g3
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ld __ISR_Nest_level,r5 # r5 = &_Isr_nest_level
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mov g14,r7 # save g14
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lda 0,g14 # NOT Branch and Link
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movl g4,r12 # save g4-g5
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lda 1(r4),r4 # increment dispatch disable level
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movl g6,r14 # save g6-g7
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ld __ISR_Vector_table,g1 # g1 = base of vector table
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stq g8, _ISR_reg_save # save g8-g11
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stl g12, _ISR_reg_save+16 # save g12-g13
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ld (g1)[g0*4],g1 # g1 = Users handler
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addo 1,r5,r5 # increment ISR level
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st r4,__Thread_Dispatch_disable_level
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# one ISR nest level deeper
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subo 1,r4,r4 # decrement dispatch disable level
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st r5,__ISR_Nest_level # disable multitasking
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subo 1,r5,r5 # decrement ISR nest level
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callx (g1) # invoke user ISR
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# unnest multitasking
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st r5,__ISR_Nest_level # one less ISR nest level
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cmpobne.f 0,r4,exit # If dispatch disabled, exit
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ldl -16(fp),g0 # g0 = threads PC reg
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# g1 = threads AC reg
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ld __Context_Switch_necessary,r6
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# r6 = Is thread switch necessary?
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bbs.f 13,g0,exit # not outer level, then exit
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cmpobne.f 0,r6,bframe # Switch necessary?
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ld __ISR_Signals_to_thread_executing,g2
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# signals sent to Run_thread
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# while in interrupt handler?
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cmpobe.f 0,g2,exit # No, then exit
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bframe: mov 0,g2
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st g2,__ISR_Signals_to_thread_executing
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ldconst 0x1f0000,g2 # g2 = intr disable mask
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mov g2,g3 # g3 = new intr level
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modpc 0,g2,g3 # set new level
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andnot 7,pfp,r4 # r4 = pfp without ret type
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flushreg # flush registers
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# push _Isr_dispatch ret frame
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# build ISF in r4-r6
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ldconst 64,g2 # g2 = size of stack frame
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ld 4(r4),g3 # g3 = previous sp
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addo g2,g3,r5 # r5 = _Isr_dispatch SP
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lda __ISR_Dispatch,r6 # r6 = _Isr_dispatch entry
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stt r4,(g3) # set _Isr_dispatch ret info
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st g1,16(g3) # set r4 = AC for ISR disp
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or 7,g3,pfp # pfp to _Isr_dispatch
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flushreg
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b exit1
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exit: st r4,__Thread_Dispatch_disable_level
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exit1: mov r7,g14 # restore g14
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movq r8,g0 # restore g0-g3
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movq r12,g4 # restore g4-g7
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ldq _ISR_reg_save, g8 # restore g8-g11
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ldl _ISR_reg_save+16, g12 # restore g12-g13
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ret
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/*PAGE
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*
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* void __ISR_Dispatch()
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*
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* Entry point from the outermost interrupt service routine exit.
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* The current stack is the supervisor mode stack.
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*/
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.globl __ISR_Dispatch
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__ISR_Dispatch:
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mov g14,r7
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mov 0,g14
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movq g0,r8
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movq g4,r12
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call __Thread_Dispatch
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ldconst -1,r5 # r5 = reload mask
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modac r5,r4,r4 # restore threads AC register
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mov r7,g14
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movq r8,g0
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movq r12,g4
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ret
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