OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [rtems-20020807/] [doc/] [supplements/] [hppa1_1/] [memmodel.t] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1026 ivang
@c
2
@c  COPYRIGHT (c) 1988-2002.
3
@c  On-Line Applications Research Corporation (OAR).
4
@c  All rights reserved.
5
@c
6
@c  memmodel.t,v 1.6 2002/01/17 21:47:46 joel Exp
7
@c
8
 
9
@chapter Memory Model
10
 
11
@section Introduction
12
 
13
A processor may support any combination of memory
14
models ranging from pure physical addressing to complex demand
15
paged virtual memory systems.  RTEMS supports a flat memory
16
model which ranges contiguously over the processor's allowable
17
address space.  RTEMS does not support segmentation or virtual
18
memory of any kind.  The appropriate memory model for RTEMS
19
provided by the targeted processor and related characteristics
20
of that model are described in this chapter.
21
 
22
@section Flat Memory Model
23
 
24
RTEMS supports applications in which the application
25
and the executive execute within a single thirty-two bit address
26
space.  Thus RTEMS and the application share a common four
27
gigabyte address space within a single space.  The PA-RISC
28
automatically converts every address from a logical to a
29
physical address each time it is used.  The PA-RISC uses
30
information provided in the page table to perform this
31
translation.  The following protection levels are assumed:
32
 
33
@itemize @bullet
34
@item a single code segment at protection level (0) which
35
contains all application and executive code.
36
 
37
@item a single data segment at protection level zero (0) which
38
contains all application and executive data.
39
@end itemize
40
 
41
The PA-RISC space registers and associated stack --
42
including the stack pointer r27 -- must be initialized when the
43
initialize_executive directive is invoked.  RTEMS treats the
44
space registers as system resources shared by all tasks and does
45
not modify or context switch them.
46
 
47
This memory model supports a flat 32-bit address
48
space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4
49
gigabytes).  Each address is represented by a 32-bit value and
50
memory is addressable.  The address may be used to reference a
51
single byte, half-word (2-bytes), or word (4 bytes).
52
 
53
RTEMS does not require that logical addresses map
54
directly to physical addresses, although it is desirable in many
55
applications to do so.  RTEMS does not need any additional
56
information when physical addresses do not map directly to
57
physical addresses.  By not requiring that logical addresses map
58
directly to physical addresses, the memory space of an RTEMS
59
space can be separated from that of a ROM monitor.  For example,
60
a ROM monitor may load application programs into a separate
61
logical address space from itself.
62
 
63
RTEMS assumes that the space registers contain the
64
selector for the single data segment when a directive is
65
invoked.   This assumption is especially important when
66
developing interrupt service routines.
67
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.