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@c
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@c COPYRIGHT (c) 1988-2002.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c bsp.t,v 1.7 2002/01/17 21:47:46 joel Exp
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@c
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@chapter Board Support Packages
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@section Introduction
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An RTEMS Board Support Package (BSP) must be designed
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to support a particular processor and target board combination.
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This chapter presents a discussion of i960CA specific BSP
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issues. For more information on developing a BSP, refer to the
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chapter titled Board Support Packages in the RTEMS
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Applications User's Guide.
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@section System Reset
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An RTEMS based application is initiated when the
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i960CA processor is reset. When the i960CA is reset, the
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processor reads an Initial Memory Image (IMI) to establish its
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state. The IMI consists of the Initialization Boot Record (IBR)
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and the Process Control Block (PRCB) from an Initial Memory
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Image (IMI) at location 0xFFFFFF00. The IBR contains the
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initial bus configuration data, the address of the first
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instruction to execute after reset, the address of the PRCB, and
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the checksum used by the processor's self-test.
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@section Processor Initialization
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The PRCB contains the base addresses for system data
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structures, and initial configuration information for the core
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and integrated peripherals. In particular, the PRCB contains
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the initial contents of the Arithmetic Control (AC) Register as
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well as the base addresses of the Interrupt Vector Table, System
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Procedure Entry Table, Fault Entry Table, and the Control Table.
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In addition, the PRCB is used to configure the depth of the
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instruction and register caches and the actions when certain
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types of faults are encountered.
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The Process Controls (PC) Register is initialized to
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0xC01F2002 which sets the i960CA's interrupt level to 0x1F (31
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decimal). In addition, the Interrupt Mask (IMSK) Register
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(alternately referred to as Special Function Register 1 or sf1)
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is set to 0x00000000 to mask all external and DMA interrupt
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sources. Thus, all interrupts are disabled when the first
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instruction is executed.
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For more information regarding the i960CA's data
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structures and their contents, refer to Intel's i960CA User's
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Manual.
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