1 |
1026 |
ivang |
@c
|
2 |
|
|
@c COPYRIGHT (c) 1988-2002.
|
3 |
|
|
@c On-Line Applications Research Corporation (OAR).
|
4 |
|
|
@c All rights reserved.
|
5 |
|
|
@c
|
6 |
|
|
@c cpumodel.t,v 1.7 2002/01/17 21:47:46 joel Exp
|
7 |
|
|
@c
|
8 |
|
|
|
9 |
|
|
@chapter CPU Model Dependent Features
|
10 |
|
|
|
11 |
|
|
@section Introduction
|
12 |
|
|
|
13 |
|
|
Microprocessors are generally classified into
|
14 |
|
|
families with a variety of CPU models or implementations within
|
15 |
|
|
that family. Within a processor family, there is a high level
|
16 |
|
|
of binary compatibility. This family may be based on either an
|
17 |
|
|
architectural specification or on maintaining compatibility with
|
18 |
|
|
a popular processor. Recent microprocessor families such as the
|
19 |
|
|
PowerPC, SPARC, and PA-RISC are based on an architectural specification
|
20 |
|
|
which is independent or any particular CPU model or
|
21 |
|
|
implementation. Older families such as the M68xxx and the iX86
|
22 |
|
|
evolved as the manufacturer strived to produce higher
|
23 |
|
|
performance processor models which maintained binary
|
24 |
|
|
compatibility with older models.
|
25 |
|
|
|
26 |
|
|
RTEMS takes advantage of the similarity of the
|
27 |
|
|
various models within a CPU family. Although the models do vary
|
28 |
|
|
in significant ways, the high level of compatibility makes it
|
29 |
|
|
possible to share the bulk of the CPU dependent executive code
|
30 |
|
|
across the entire family.
|
31 |
|
|
|
32 |
|
|
@section CPU Model Feature Flags
|
33 |
|
|
|
34 |
|
|
Each processor family supported by RTEMS has a
|
35 |
|
|
list of features which vary between CPU models
|
36 |
|
|
within a family. For example, the most common model dependent
|
37 |
|
|
feature regardless of CPU family is the presence or absence of a
|
38 |
|
|
floating point unit or coprocessor. When defining the list of
|
39 |
|
|
features present on a particular CPU model, one simply notes
|
40 |
|
|
that floating point hardware is or is not present and defines a
|
41 |
|
|
single constant appropriately. Conditional compilation is
|
42 |
|
|
utilized to include the appropriate source code for this CPU
|
43 |
|
|
model's feature set. It is important to note that this means
|
44 |
|
|
that RTEMS is thus compiled using the appropriate feature set
|
45 |
|
|
and compilation flags optimal for this CPU model used. The
|
46 |
|
|
alternative would be to generate a binary which would execute on
|
47 |
|
|
all family members using only the features which were always
|
48 |
|
|
present.
|
49 |
|
|
|
50 |
|
|
This section presents the set of features which vary
|
51 |
|
|
across PowerPC implementations and are of importance to RTEMS.
|
52 |
|
|
The set of CPU model feature macros are defined in the file
|
53 |
|
|
c/src/exec/score/cpu/ppc/ppc.h based upon the particular CPU
|
54 |
|
|
model defined on the compilation command line.
|
55 |
|
|
|
56 |
|
|
@subsection CPU Model Name
|
57 |
|
|
|
58 |
|
|
The macro CPU_MODEL_NAME is a string which designates
|
59 |
|
|
the name of this CPU model. For example, for the PowerPC 603e
|
60 |
|
|
model, this macro is set to the string "PowerPC 603e".
|
61 |
|
|
|
62 |
|
|
@subsection Floating Point Unit
|
63 |
|
|
|
64 |
|
|
The macro PPC_HAS_FPU is set to 1 to indicate that this CPU model
|
65 |
|
|
has a hardware floating point unit and 0 otherwise.
|
66 |
|
|
|
67 |
|
|
@subsection Alignment
|
68 |
|
|
|
69 |
|
|
The macro PPC_ALIGNMENT is set to the PowerPC model's worst case alignment
|
70 |
|
|
requirement for data types on a byte boundary. This value is used
|
71 |
|
|
to derive the alignment restrictions for memory allocated from
|
72 |
|
|
regions and partitions.
|
73 |
|
|
|
74 |
|
|
@subsection Cache Alignment
|
75 |
|
|
|
76 |
|
|
The macro PPC_CACHE_ALIGNMENT is set to the line size of the cache. It is
|
77 |
|
|
used to align the entry point of critical routines so that as much code
|
78 |
|
|
as possible can be retrieved with the initial read into cache. This
|
79 |
|
|
is done for the interrupt handler as well as the context switch routines.
|
80 |
|
|
|
81 |
|
|
In addition, the "shortcut" data structure used by the PowerPC implementation
|
82 |
|
|
to ease access to data elements frequently accessed by RTEMS routines
|
83 |
|
|
implemented in assembly language is aligned using this value.
|
84 |
|
|
|
85 |
|
|
@subsection Maximum Interrupts
|
86 |
|
|
|
87 |
|
|
The macro PPC_INTERRUPT_MAX is set to the number of exception sources
|
88 |
|
|
supported by this PowerPC model.
|
89 |
|
|
|
90 |
|
|
@subsection Has Double Precision Floating Point
|
91 |
|
|
|
92 |
|
|
The macro PPC_HAS_DOUBLE is set to 1 to indicate that the PowerPC model
|
93 |
|
|
has support for double precision floating point numbers. This is
|
94 |
|
|
important because the floating point registers need only be four bytes
|
95 |
|
|
wide (not eight) if double precision is not supported.
|
96 |
|
|
|
97 |
|
|
@subsection Critical Interrupts
|
98 |
|
|
|
99 |
|
|
The macro PPC_HAS_RFCI is set to 1 to indicate that the PowerPC model
|
100 |
|
|
has the Critical Interrupt capability as defined by the IBM 403 models.
|
101 |
|
|
|
102 |
|
|
@subsection Use Multiword Load/Store Instructions
|
103 |
|
|
|
104 |
|
|
The macro PPC_USE_MULTIPLE is set to 1 to indicate that multiword load and
|
105 |
|
|
store instructions should be used to perform context switch operations.
|
106 |
|
|
The relative efficiency of multiword load and store instructions versus
|
107 |
|
|
an equivalent set of single word load and store instructions varies based
|
108 |
|
|
upon the PowerPC model.
|
109 |
|
|
|
110 |
|
|
@subsection Instruction Cache Size
|
111 |
|
|
|
112 |
|
|
The macro PPC_I_CACHE is set to the size in bytes of the instruction cache.
|
113 |
|
|
|
114 |
|
|
@subsection Data Cache Size
|
115 |
|
|
|
116 |
|
|
The macro PPC_D_CACHE is set to the size in bytes of the data cache.
|
117 |
|
|
|
118 |
|
|
@subsection Debug Model
|
119 |
|
|
|
120 |
|
|
The macro PPC_DEBUG_MODEL is set to indicate the debug support features
|
121 |
|
|
present in this CPU model. The following debug support feature sets
|
122 |
|
|
are currently supported:
|
123 |
|
|
|
124 |
|
|
@table @b
|
125 |
|
|
|
126 |
|
|
@item @code{PPC_DEBUG_MODEL_STANDARD}
|
127 |
|
|
indicates that the single-step trace enable (SE) and branch trace
|
128 |
|
|
enable (BE) bits in the MSR are supported by this CPU model.
|
129 |
|
|
|
130 |
|
|
@item @code{PPC_DEBUG_MODEL_SINGLE_STEP_ONLY}
|
131 |
|
|
indicates that only the single-step trace enable (SE) bit in the MSR
|
132 |
|
|
is supported by this CPU model.
|
133 |
|
|
|
134 |
|
|
@item @code{PPC_DEBUG_MODEL_IBM4xx}
|
135 |
|
|
indicates that the debug exception enable (DE) bit in the MSR is supported
|
136 |
|
|
by this CPU model. At this time, this particular debug feature set
|
137 |
|
|
has only been seen in the IBM 4xx series.
|
138 |
|
|
|
139 |
|
|
@end table
|
140 |
|
|
|
141 |
|
|
@subsection Low Power Model
|
142 |
|
|
|
143 |
|
|
The macro PPC_LOW_POWER_MODE is set to indicate the low power model
|
144 |
|
|
supported by this CPU model. The following low power modes are currently
|
145 |
|
|
supported.
|
146 |
|
|
|
147 |
|
|
@table @b
|
148 |
|
|
|
149 |
|
|
@item @code{PPC_LOW_POWER_MODE_NONE}
|
150 |
|
|
indicates that this CPU model has no low power mode support.
|
151 |
|
|
|
152 |
|
|
@item @code{PPC_LOW_POWER_MODE_STANDARD}
|
153 |
|
|
indicates that this CPU model follows the low power model defined for
|
154 |
|
|
the PPC603e.
|
155 |
|
|
|
156 |
|
|
@end table
|