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@c  COPYRIGHT (c) 1988-2002.

@c  On-Line Applications Research Corporation (OAR).

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@c  preface.texi,v 1.5 2002/01/17 21:47:47 joel Exp

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@ifinfo

@node Preface, CPU Model Dependent Features, Top, Top

@end ifinfo

@unnumbered Preface

The Real Time Executive for Multiprocessor Systems

(RTEMS) is designed to be portable across multiple processor

architectures.  However, the nature of real-time systems makes

it essential that the application designer understand certain

processor dependent implementation details.  These processor

dependencies include calling convention, board support package

issues, interrupt processing, exact RTEMS memory requirements,

performance data, header files, and the assembly language

interface to the executive.

This document discusses the SPARC architecture

dependencies in this port of RTEMS.  Currently, only

implementations of SPARC Version 7 are supported by RTEMS.

It is highly recommended that the SPARC RTEMS

application developer obtain and become familiar with the

documentation for the processor being used as well as the

specification for the revision of the SPARC architecture which

corresponds to that processor.

@subheading SPARC Architecture Documents

For information on the SPARC architecture, refer to

the following documents available from SPARC International, Inc.

(http://www.sparc.com):

@itemize @bullet

@item SPARC Standard Version 7.

@item SPARC Standard Version 8.

@item SPARC Standard Version 9.

@end itemize

@subheading ERC32 Specific Information

The European Space Agency's ERC32 is a three chip

computing core implementing a SPARC V7 processor and associated

support circuitry for embedded space applications. The integer

and floating-point units (90C601E & 90C602E) are based on the

Cypress 7C601 and 7C602, with additional error-detection and

recovery functions. The memory controller (MEC) implements

system support functions such as address decoding, memory

interface, DMA interface, UARTs, timers, interrupt control,

write-protection, memory reconfiguration and error-detection.

The core is designed to work at 25MHz, but using space qualified

memories limits the system frequency to around 15 MHz, resulting

in a performance of 10 MIPS and 2 MFLOPS.

Information on the ERC32 and a number of development

support tools, such as the SPARC Instruction Simulator (SIS),

are freely available on the Internet.  The following documents

and SIS are available via anonymous ftp or pointing your web

browser at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32.

@itemize @bullet

@item ERC32 System Design Document

@item MEC Device Specification

@end itemize

Additionally, the SPARC RISC User's Guide from Matra

MHS documents the functionality of the integer and floating

point units including the instruction set information.  To

obtain this document as well as ERC32 components and VHDL models

contact:

@example

Matra MHS SA

3 Avenue du Centre, BP 309,

78054 St-Quentin-en-Yvelines,

Cedex, France

VOICE: +31-1-30607087

FAX: +31-1-30640693

@end example

Amar Guennon (amar.guennon@@matramhs.fr) is familiar with the ERC32.