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[/] [or1k/] [trunk/] [uclinux/] [uC-libc/] [include/] [asm/] [m5307dma.h] - Blame information for rev 1778

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1 199 simons 
#ifndef _M5307_DMA_H
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#define _M5307_DMA_H 1
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/irq.h>
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#define MAX_DMA_CHANNELS 4
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/*
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*DMA Address Definitions
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*/
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#define MCF5307_DMA_SAR         (MCF_MBAR+0x300)  /*Source Address Register Channel */
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#define MCF5307_DMA_DAR         (MCF_MBAR+0x304)  /*Destination Address Register Channel*/
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#define MCF5307_DMA_DCR         (MCF_MBAR+0x308)  /*DMA Controll Register Channel*/
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#define MCF5307_DMA_BCR         (MCF_MBAR+0x30C)  /*Byte Count Register Channel*/
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#define MCF5307_DMA_SR          (MCF_MBAR+0x310)  /*Status Register Channel*/
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#define MCF5307_DMA_IVR         (MCF_MBAR+0x314)  /*InterruptVectorRegister Channel*/
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/*
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*DMA Controll Register Definition
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*/
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#define MCF5307_DMA_DCR_INT             (0x8000) /* Interrupt on Completion     */
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#define MCF5307_DMA_DCR_EEXT            (0x4000) /* Enable External Request     */
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#define MCF5307_DMA_DCR_CS              (0x2000) /* Cycle Steal                 */
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#define MCF5307_DMA_DCR_AA              (0x1000) /* Auto Align                  */
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#define MCF5307_DMA_DCR_BWC_DMA         (0x0000) /* Bandwidth: DMA Priority     */
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#define MCF5307_DMA_DCR_BWC_512         (0x0200) /* Bandwidth:   512 Bytes      */
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#define MCF5307_DMA_DCR_BWC_1024        (0x0400) /* Bandwidth:  1024 Bytes      */
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#define MCF5307_DMA_DCR_BWC_2048        (0x0600) /* Bandwidth:  2048 Bytes      */
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#define MCF5307_DMA_DCR_BWC_4096        (0x0800) /* Bandwidth:  4096 Bytes      */
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#define MCF5307_DMA_DCR_BWC_8192        (0x0a00) /* Bandwidth:  8192 Bytes      */
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#define MCF5307_DMA_DCR_BWC_16384       (0x0c00) /* Bandwidth: 16384 Bytes      */
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#define MCF5307_DMA_DCR_BWC_32768       (0x0e00) /* Bandwidth: 32768 Bytes      */
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#define MCF5307_DMA_DCR_SAA             (0x0100) /* Single Address Access       */
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#define MCF5307_DMA_DCR_SRW             (0x0080) /* Forces MRW Signal High      */
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#define MCF5307_DMA_DCR_SINC            (0x0040) /* Source Increment            */
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#define MCF5307_DMA_DCR_SSIZE_LONG      (0x0000) /* Source Size:  Longword      */
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#define MCF5307_DMA_DCR_SSIZE_BYTE      (0x0010) /* Source Size:  Byte          */
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#define MCF5307_DMA_DCR_SSIZE_WORD      (0x0020) /* Source Size:  Word          */
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#define MCF5307_DMA_DCR_SSIZE_LINE      (0x0030) /* Source Size:  Line          */
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#define MCF5307_DMA_DCR_DINC            (0x0008) /* Destination Increment       */
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#define MCF5307_DMA_DCR_DSIZE_LONG      (0x0000) /* Destination Size:  Longword */
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#define MCF5307_DMA_DCR_DSIZE_BYTE      (0x0002) /* Destination Size:  Byte     */
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#define MCF5307_DMA_DCR_DSIZE_WORD      (0x0004) /* Destination Size:  Word     */
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#define MCF5307_DMA_DCR_DSIZE_LINE      (0x0006) /* Destination Size:  Line          */
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#define MCF5307_DMA_DCR_START           (0x0001) /* Start Transfer                      */
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/*
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*DMA Status Register Definitions
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*/
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#define MCF5307_DMA_DSR_CE              (0x40)  /* Configuration Error          */
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#define MCF5307_DMA_DSR_BES             (0x20)  /* Bus Error on Source          */
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#define MCF5307_DMA_DSR_BED             (0x10)  /* Bus Error on Destination     */
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#define MCF5307_DMA_DSR_REQ             (0x04)  /* Request                                      */
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#define MCF5307_DMA_DSR_BSY             (0x02)  /* Busy                                         */
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#define MCF5307_DMA_DSR_DONE            (0x01)  /* Transaction Done                     */
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#define DMA_STATE_BUSY                  1
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#define DMA_STATE_IDLE                  0
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#define DMA_STATE_CONFIGURATION_ERROR   -1
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#define DMA_STATE_SOURCE_ERROR          -2
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#define DMA_STATE_DESTINATION_ERROR     -3
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struct dma_mcf
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{
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        const char *devname;
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        unsigned char* source;
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        unsigned char* dest;
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        unsigned short count;
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        unsigned short creg;  /*16 bit controllregister use the defines above*/
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        void (*handler) (int, void *, struct pt_regs *);
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        unsigned int irq_vector;
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        unsigned int irq_level;
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        unsigned long irq_flags;
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};
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static __inline__ int dma_init(int channel)
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{
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        int err;
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        if ((err = request_dma(channel, 0)) != 0) return err;
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        *(unsigned char*) (MCF_MBAR + MCFSIM_MPARK) |= 0x80; /* DMA BUS
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        MASTER with highest priority*/
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        return err;
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}
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static __inline__ void dma_set(int channel, struct dma_mcf dma)
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{
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        *(unsigned int*) (MCF5307_DMA_SAR + (0x40 * channel)) = dma.source;
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        *(unsigned int*) (MCF5307_DMA_DAR + (0x40 * channel)) = dma.dest;
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        *(unsigned short*) (MCF5307_DMA_BCR + (0x40 * channel)) = dma.count;
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        if ((dma.creg & MCF5307_DMA_DCR_INT) !=0)                /* DMA generates a Interrupt on complrtion*/
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                {                                       /* Now configure the Interrupt handler*/
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                *(unsigned short*) (MCF5307_DMA_IVR + (0x40 * channel)) = dma.irq_vector;
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                if (request_irq(dma.irq_vector,dma.handler,dma.irq_flags,
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                dma.devname, 0) !=0)
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                                printk("request irq fail\n");
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                *(volatile unsigned char*)(MCF_MBAR + 0x52 + channel) = dma.irq_level | MCFSIM_ICR_AUTOVEC;    /* set MBUS IRQ-Level and autovector */
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                mcf_setimr(mcf_getimr() & ~(0x4000 << channel));
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                printk("maskreg%X\n",mcf_getimr());
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                }
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        *(unsigned short*) (MCF5307_DMA_DCR + (0x40 * channel)) = dma.creg;
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}
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static __inline__ unsigned char dma_busy(unsigned char channel)
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{
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        if ((*(unsigned char*) (MCF5307_DMA_SR + (0x40 * channel)) & MCF5307_DMA_DSR_BSY)!=0) return(0x1);
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        return 0;
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}
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static __inline__ void dma_done(unsigned char channel)
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{
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        *(unsigned char*) (MCF5307_DMA_SR + (0x40 * channel)) = MCF5307_DMA_DSR_DONE;
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}
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static __inline__ void dma_clear(unsigned char channel)
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{
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        *(unsigned short*) (MCF5307_DMA_DCR + (0x40 * channel)) = 0x0000;
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}
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static __inline__ unsigned char dma_get_status(unsigned char dsr)
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{
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        if ((dsr & MCF5307_DMA_DSR_CE) != 0) return(DMA_STATE_CONFIGURATION_ERROR);
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        if ((dsr & MCF5307_DMA_DSR_BES) !=0) return(DMA_STATE_SOURCE_ERROR);
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        if ((dsr & MCF5307_DMA_DSR_BED) !=0) return(DMA_STATE_DESTINATION_ERROR);
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        return 0;
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}
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extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
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extern void free_dma(unsigned int dmanr);       /* release it again */
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#endif /* _M5307_DMA_H */

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