| 1 |
199 |
simons |
/* $Id: scc.h,v 1.1.1.1 2001-09-10 07:43:50 simons Exp $ */
|
| 2 |
|
|
|
| 3 |
|
|
#ifndef _SCC_H
|
| 4 |
|
|
#define _SCC_H
|
| 5 |
|
|
|
| 6 |
|
|
#include <linux/if_ether.h>
|
| 7 |
|
|
|
| 8 |
|
|
/* selection of hardware types */
|
| 9 |
|
|
|
| 10 |
|
|
#define PA0HZP 0x00 /* hardware type for PA0HZP SCC card and compatible */
|
| 11 |
|
|
#define EAGLE 0x01 /* hardware type for EAGLE card */
|
| 12 |
|
|
#define PC100 0x02 /* hardware type for PC100 card */
|
| 13 |
|
|
#define PRIMUS 0x04 /* hardware type for PRIMUS-PC (DG9BL) card */
|
| 14 |
|
|
#define DRSI 0x08 /* hardware type for DRSI PC*Packet card */
|
| 15 |
|
|
#define BAYCOM 0x10 /* hardware type for BayCom (U)SCC */
|
| 16 |
|
|
|
| 17 |
|
|
/* Paranoia check... */
|
| 18 |
|
|
|
| 19 |
|
|
#define SCC_PARANOIA_CHECK /* tell the user if something is going wrong */
|
| 20 |
|
|
|
| 21 |
|
|
/* TTY ioctl() commands */
|
| 22 |
|
|
|
| 23 |
|
|
#define TIOCSCCCFG _IOW('Z', 0, sizeof(struct scc_hw_config)) /* set hardware parameters */
|
| 24 |
|
|
#define TIOCSCCINI _IO('Z', 1) /* init driver */
|
| 25 |
|
|
#define TIOCSCCCHANINI _IOW('Z', 2, sizeof(struct scc_modem)) /* init channel */
|
| 26 |
|
|
#define TIOCSCCSMEM _IOW('Z', 3, sizeof(struct scc_mem_config)) /* adjust buffer pools */
|
| 27 |
|
|
#define TIOCSCCGKISS _IOWR('Z', 4, sizeof(struct scc_kiss_cmd)) /* get kiss parameter */
|
| 28 |
|
|
#define TIOCSCCSKISS _IOW('Z', 5, sizeof(struct scc_kiss_cmd)) /* set kiss parameter */
|
| 29 |
|
|
#define TIOCSCCGSTAT _IOR('Z', 6, sizeof(struct scc_stat)) /* get scc status */
|
| 30 |
|
|
|
| 31 |
|
|
/* old TTY ioctl() commands */
|
| 32 |
|
|
|
| 33 |
|
|
#define TIOCSCCCFG_OLD 0x2200
|
| 34 |
|
|
#define TIOCSCCINI_OLD 0x2201
|
| 35 |
|
|
#define TIOCCHANINI_OLD 0x2202
|
| 36 |
|
|
#define TIOCCHANMEM_OLD 0x2210
|
| 37 |
|
|
#define TIOCSKISS_OLD 0x2282
|
| 38 |
|
|
#define TIOCGKISS_OLD 0x2283
|
| 39 |
|
|
#define TIOCSCCSTAT_OLD 0x2284
|
| 40 |
|
|
|
| 41 |
|
|
/* DEV ioctl() commands */
|
| 42 |
|
|
|
| 43 |
|
|
enum SCC_IOCTL_CMD {
|
| 44 |
|
|
SIOCSCCRESERVED=SIOCDEVPRIVATE,
|
| 45 |
|
|
SIOCSCCCFG,
|
| 46 |
|
|
SIOCSCCINI,
|
| 47 |
|
|
SIOCSCCCHANINI,
|
| 48 |
|
|
SIOCSCCSMEM,
|
| 49 |
|
|
SIOCSCCGKISS,
|
| 50 |
|
|
SIOCSCCSKISS,
|
| 51 |
|
|
SIOCSCCGSTAT
|
| 52 |
|
|
};
|
| 53 |
|
|
|
| 54 |
|
|
/* magic number */
|
| 55 |
|
|
|
| 56 |
|
|
#define SCC_MAGIC 0x8530 /* ;-) */
|
| 57 |
|
|
|
| 58 |
|
|
/* KISS protocol flags */
|
| 59 |
|
|
#define FEND 192
|
| 60 |
|
|
#define FESC 219
|
| 61 |
|
|
#define TFEND 220
|
| 62 |
|
|
#define TFESC 221
|
| 63 |
|
|
|
| 64 |
|
|
/* KISS state machine */
|
| 65 |
|
|
|
| 66 |
|
|
enum SCC_KISS_STATES {
|
| 67 |
|
|
KISS_IDLE,
|
| 68 |
|
|
KISS_DATA,
|
| 69 |
|
|
KISS_ESCAPE,
|
| 70 |
|
|
KISS_RXFRAME
|
| 71 |
|
|
};
|
| 72 |
|
|
|
| 73 |
|
|
/* Device parameter control (from WAMPES) */
|
| 74 |
|
|
|
| 75 |
|
|
enum SCC_KISS_PARAMS {
|
| 76 |
|
|
PARAM_TXDELAY=1,
|
| 77 |
|
|
PARAM_PERSIST,
|
| 78 |
|
|
PARAM_SLOTTIME,
|
| 79 |
|
|
PARAM_TXTAIL,
|
| 80 |
|
|
PARAM_FULLDUP,
|
| 81 |
|
|
PARAM_SOFTDCD, /* was: PARAM_HW */
|
| 82 |
|
|
PARAM_MUTE, /* ??? */
|
| 83 |
|
|
PARAM_DTR,
|
| 84 |
|
|
PARAM_RTS,
|
| 85 |
|
|
PARAM_SPEED,
|
| 86 |
|
|
PARAM_ENDDELAY, /* ??? */
|
| 87 |
|
|
PARAM_GROUP,
|
| 88 |
|
|
PARAM_IDLE,
|
| 89 |
|
|
PARAM_MIN,
|
| 90 |
|
|
PARAM_MAXKEY,
|
| 91 |
|
|
PARAM_WAIT,
|
| 92 |
|
|
PARAM_MAXDEFER,
|
| 93 |
|
|
PARAM_TX,
|
| 94 |
|
|
PARAM_HWEVENT=31,
|
| 95 |
|
|
PARAM_RETURN=255 /* reset kiss mode */
|
| 96 |
|
|
};
|
| 97 |
|
|
|
| 98 |
|
|
/* fulldup parameter */
|
| 99 |
|
|
|
| 100 |
|
|
enum SCC_KISS_DUPLEX_MODES {
|
| 101 |
|
|
KISS_DUPLEX_HALF, /* normal CSMA operation */
|
| 102 |
|
|
KISS_DUPLEX_FULL, /* fullduplex, key down trx after transmission */
|
| 103 |
|
|
KISS_DUPLEX_LINK, /* fullduplex, key down trx after 'idletime' sec */
|
| 104 |
|
|
KISS_DUPLEX_OPTIMA, /* fullduplex, let the protocol layer control the hw */
|
| 105 |
|
|
};
|
| 106 |
|
|
|
| 107 |
|
|
/* misc. parameters */
|
| 108 |
|
|
|
| 109 |
|
|
#define TIMER_OFF 65535U /* to switch off timers */
|
| 110 |
|
|
#define NO_SUCH_PARAM 65534U /* param not implemented */
|
| 111 |
|
|
|
| 112 |
|
|
/* HWEVENT parameter */
|
| 113 |
|
|
|
| 114 |
|
|
enum SCC_HWEV_PARAMETERS {
|
| 115 |
|
|
HWEV_DCD_ON,
|
| 116 |
|
|
HWEV_DCD_OFF,
|
| 117 |
|
|
HWEV_ALL_SENT
|
| 118 |
|
|
};
|
| 119 |
|
|
|
| 120 |
|
|
/* channel grouping */
|
| 121 |
|
|
|
| 122 |
|
|
#define RXGROUP 0x100 /* if set, only tx when all channels clear */
|
| 123 |
|
|
#define TXGROUP 0x200 /* if set, don't transmit simultaneously */
|
| 124 |
|
|
|
| 125 |
|
|
/* Tx/Rx clock sources */
|
| 126 |
|
|
|
| 127 |
|
|
enum SCC_CLK_SOURCES {
|
| 128 |
|
|
CLK_DPLL, /* normal halfduplex operation */
|
| 129 |
|
|
CLK_EXTERNAL, /* external clocking (G3RUH/DF9IC modems) */
|
| 130 |
|
|
CLK_DIVIDER /* Rx = DPLL, Tx = divider (fullduplex with */
|
| 131 |
|
|
/* modems without clock regeneration */
|
| 132 |
|
|
};
|
| 133 |
|
|
|
| 134 |
|
|
/* Tx state */
|
| 135 |
|
|
|
| 136 |
|
|
enum SCC_TX_STATES {
|
| 137 |
|
|
TXS_IDLE, /* Transmitter off, no data pending */
|
| 138 |
|
|
TXS_BUSY, /* waiting for permission to send / tailtime */
|
| 139 |
|
|
TXS_ACTIVE, /* Transmitter on, sending data */
|
| 140 |
|
|
TXS_NEWFRAME, /* reset CRC and send (next) frame */
|
| 141 |
|
|
TXS_IDLE2, /* Transmitter on, no data pending */
|
| 142 |
|
|
TXS_WAIT, /* Waiting for Mintime to expire */
|
| 143 |
|
|
TXS_TIMEOUT /* We had a transmission timeout */
|
| 144 |
|
|
};
|
| 145 |
|
|
|
| 146 |
|
|
enum SCC_TX_KEY {TX_OFF, TX_ON}; /* command for scc_key_trx() */
|
| 147 |
|
|
|
| 148 |
|
|
/* Buffer management */
|
| 149 |
|
|
|
| 150 |
|
|
#define BT_RECEIVE 1 /* buffer allocated by receive */
|
| 151 |
|
|
#define BT_TRANSMIT 2 /* buffer allocated by transmit */
|
| 152 |
|
|
|
| 153 |
|
|
#define NULLBUF (struct mbuf *)0
|
| 154 |
|
|
#define NULLBUFP (struct mbuf **)0
|
| 155 |
|
|
|
| 156 |
|
|
|
| 157 |
|
|
typedef unsigned short io_port; /* type definition for an 'io port address' */
|
| 158 |
|
|
typedef unsigned short ioaddr; /* old def */
|
| 159 |
|
|
|
| 160 |
|
|
#ifdef SCC_DELAY
|
| 161 |
|
|
#define Inb(port) inb_p(port)
|
| 162 |
|
|
#define Outb(port, val) outb_p(val, port)
|
| 163 |
|
|
#else
|
| 164 |
|
|
#define Inb(port) inb(port)
|
| 165 |
|
|
#define Outb(port, val) outb(val, port)
|
| 166 |
|
|
#endif
|
| 167 |
|
|
|
| 168 |
|
|
#define TIMER_OFF 65535U
|
| 169 |
|
|
|
| 170 |
|
|
/* Basic message buffer structure */
|
| 171 |
|
|
|
| 172 |
|
|
struct mbuf {
|
| 173 |
|
|
struct mbuf *next; /* Link to next buffer */
|
| 174 |
|
|
struct mbuf *prev; /* Link to previous buffer */
|
| 175 |
|
|
|
| 176 |
|
|
int cnt; /* Number of bytes stored in buffer */
|
| 177 |
|
|
unsigned char *rw_ptr; /* read-write pointer */
|
| 178 |
|
|
unsigned char data[0]; /* anchor for allocated buffer */
|
| 179 |
|
|
};
|
| 180 |
|
|
|
| 181 |
|
|
/* SCC channel control structure for KISS */
|
| 182 |
|
|
|
| 183 |
|
|
struct scc_kiss {
|
| 184 |
|
|
unsigned char txdelay; /* Transmit Delay 10 ms/cnt */
|
| 185 |
|
|
unsigned char persist; /* Persistence (0-255) as a % */
|
| 186 |
|
|
unsigned char slottime; /* Delay to wait on persistence hit */
|
| 187 |
|
|
unsigned char tailtime; /* Delay after last byte written */
|
| 188 |
|
|
unsigned char fulldup; /* Full Duplex mode 0=CSMA 1=DUP 2=ALWAYS KEYED */
|
| 189 |
|
|
unsigned char waittime; /* Waittime before any transmit attempt */
|
| 190 |
|
|
unsigned int maxkeyup; /* Maximum time to transmit (seconds) */
|
| 191 |
|
|
unsigned char mintime; /* Minimal offtime after MAXKEYUP timeout (seconds) */
|
| 192 |
|
|
unsigned int idletime; /* Maximum idle time in ALWAYS KEYED mode (seconds) */
|
| 193 |
|
|
unsigned int maxdefer; /* Timer for CSMA channel busy limit */
|
| 194 |
|
|
unsigned char tx_inhibit; /* Transmit is not allowed when set */
|
| 195 |
|
|
unsigned char group; /* Group ID for AX.25 TX interlocking */
|
| 196 |
|
|
unsigned char mode; /* 'normal' or 'hwctrl' mode (unused) */
|
| 197 |
|
|
|
| 198 |
|
|
unsigned char softdcd; /* Use DPLL instead of DCD pin for carrier detect */
|
| 199 |
|
|
};
|
| 200 |
|
|
|
| 201 |
|
|
|
| 202 |
|
|
/* SCC statistical information */
|
| 203 |
|
|
|
| 204 |
|
|
struct scc_stat {
|
| 205 |
|
|
long rxints; /* Receiver interrupts */
|
| 206 |
|
|
long txints; /* Transmitter interrupts */
|
| 207 |
|
|
long exints; /* External/status interrupts */
|
| 208 |
|
|
long spints; /* Special receiver interrupts */
|
| 209 |
|
|
|
| 210 |
|
|
long txframes; /* Packets sent */
|
| 211 |
|
|
long rxframes; /* Number of Frames Actually Received */
|
| 212 |
|
|
long rxerrs; /* CRC Errors */
|
| 213 |
|
|
long txerrs; /* KISS errors */
|
| 214 |
|
|
|
| 215 |
|
|
unsigned int nospace; /* "Out of buffers" */
|
| 216 |
|
|
unsigned int rx_over; /* Receiver Overruns */
|
| 217 |
|
|
unsigned int tx_under; /* Transmitter Underruns */
|
| 218 |
|
|
|
| 219 |
|
|
unsigned int tx_state; /* Transmitter state */
|
| 220 |
|
|
|
| 221 |
|
|
char tx_kiss_state; /* state of the kiss interpreter */
|
| 222 |
|
|
char rx_kiss_state; /* state of the kiss encoder */
|
| 223 |
|
|
|
| 224 |
|
|
int tx_queued; /* tx frames enqueued */
|
| 225 |
|
|
int rx_queued; /* rx frames enqueued */
|
| 226 |
|
|
|
| 227 |
|
|
unsigned int rxbuffers; /* allocated rx_buffers */
|
| 228 |
|
|
unsigned int txbuffers; /* allocated tx_buffers */
|
| 229 |
|
|
unsigned int bufsize; /* used buffersize */
|
| 230 |
|
|
|
| 231 |
|
|
unsigned char is_netdev;/* If set: act as network instead of character device */
|
| 232 |
|
|
};
|
| 233 |
|
|
|
| 234 |
|
|
|
| 235 |
|
|
struct scc_modem {
|
| 236 |
|
|
long speed; /* Line speed, bps */
|
| 237 |
|
|
char clocksrc; /* 0 = DPLL, 1 = external, 2 = divider */
|
| 238 |
|
|
char nrz; /* NRZ instead of NRZI */
|
| 239 |
|
|
};
|
| 240 |
|
|
|
| 241 |
|
|
struct scc_kiss_cmd {
|
| 242 |
|
|
int command; /* one of the KISS-Commands defined above */
|
| 243 |
|
|
unsigned param; /* KISS-Param */
|
| 244 |
|
|
};
|
| 245 |
|
|
|
| 246 |
|
|
struct scc_hw_config {
|
| 247 |
|
|
io_port data_a; /* data port channel A */
|
| 248 |
|
|
io_port ctrl_a; /* control port channel A */
|
| 249 |
|
|
io_port data_b; /* data port channel B */
|
| 250 |
|
|
io_port ctrl_b; /* control port channel B */
|
| 251 |
|
|
io_port vector_latch; /* INTACK-Latch (#) */
|
| 252 |
|
|
io_port special; /* special function port */
|
| 253 |
|
|
|
| 254 |
|
|
int irq; /* irq */
|
| 255 |
|
|
long clock; /* clock */
|
| 256 |
|
|
char option; /* command for function port */
|
| 257 |
|
|
|
| 258 |
|
|
char brand; /* hardware type */
|
| 259 |
|
|
char escc; /* use ext. features of a 8580/85180/85280 */
|
| 260 |
|
|
};
|
| 261 |
|
|
|
| 262 |
|
|
/* (#) only one INTACK latch allowed. */
|
| 263 |
|
|
|
| 264 |
|
|
|
| 265 |
|
|
struct scc_mem_config {
|
| 266 |
|
|
unsigned int rxbuffers;
|
| 267 |
|
|
unsigned int txbuffers;
|
| 268 |
|
|
unsigned int bufsize;
|
| 269 |
|
|
};
|
| 270 |
|
|
|
| 271 |
|
|
|
| 272 |
|
|
/* SCC channel structure */
|
| 273 |
|
|
|
| 274 |
|
|
struct scc_channel {
|
| 275 |
|
|
int magic; /* magic word */
|
| 276 |
|
|
|
| 277 |
|
|
int init; /* channel exists? */
|
| 278 |
|
|
struct tty_struct *tty; /* link to tty control structure */
|
| 279 |
|
|
char tty_opened; /* No. of open() calls... */
|
| 280 |
|
|
char throttled; /* driver is throttled */
|
| 281 |
|
|
|
| 282 |
|
|
struct device *dev; /* link to device control structure */
|
| 283 |
|
|
struct enet_statistics dev_stat;
|
| 284 |
|
|
/* device statistics */
|
| 285 |
|
|
|
| 286 |
|
|
char brand; /* manufacturer of the board */
|
| 287 |
|
|
long clock; /* used clock */
|
| 288 |
|
|
|
| 289 |
|
|
io_port ctrl; /* I/O address of CONTROL register */
|
| 290 |
|
|
io_port data; /* I/O address of DATA register */
|
| 291 |
|
|
io_port special; /* I/O address of special function port */
|
| 292 |
|
|
int irq; /* Number of Interrupt */
|
| 293 |
|
|
|
| 294 |
|
|
char option;
|
| 295 |
|
|
char enhanced; /* Enhanced SCC support */
|
| 296 |
|
|
|
| 297 |
|
|
unsigned char wreg[16]; /* Copy of last written value in WRx */
|
| 298 |
|
|
unsigned char status; /* Copy of R0 at last external interrupt */
|
| 299 |
|
|
|
| 300 |
|
|
struct scc_kiss kiss; /* control structure for KISS params */
|
| 301 |
|
|
struct scc_stat stat; /* statistical information */
|
| 302 |
|
|
struct scc_modem modem; /* modem information */
|
| 303 |
|
|
|
| 304 |
|
|
char mempool; /* pool empty or allocated? */
|
| 305 |
|
|
struct mbuf *rx_buffer_pool; /* free buffers for rx/tx frames are */
|
| 306 |
|
|
struct mbuf *tx_buffer_pool; /* linked in these ring chains */
|
| 307 |
|
|
|
| 308 |
|
|
struct mbuf *rx_queue; /* chain of received frames */
|
| 309 |
|
|
struct mbuf *tx_queue; /* chain of frames due to transmit */
|
| 310 |
|
|
struct mbuf *rx_bp; /* pointer to frame currently received */
|
| 311 |
|
|
struct mbuf *tx_bp; /* pointer to frame currently transmitted */
|
| 312 |
|
|
|
| 313 |
|
|
struct mbuf *kiss_decode_bp; /* frame we are receiving from tty */
|
| 314 |
|
|
struct mbuf *kiss_encode_bp; /* frame we are sending to tty */
|
| 315 |
|
|
|
| 316 |
|
|
/* Timer */
|
| 317 |
|
|
|
| 318 |
|
|
struct timer_list tx_t; /* tx timer for this channel */
|
| 319 |
|
|
struct timer_list tx_wdog;
|
| 320 |
|
|
/* tx watchdogs */
|
| 321 |
|
|
struct timer_list rx_t; /* rx timer */
|
| 322 |
|
|
};
|
| 323 |
|
|
|
| 324 |
|
|
|
| 325 |
|
|
/* 8530 Serial Communications Controller Register definitions */
|
| 326 |
|
|
#define FLAG 0x7e
|
| 327 |
|
|
|
| 328 |
|
|
/* Write Register 0 */
|
| 329 |
|
|
#define R0 0 /* Register selects */
|
| 330 |
|
|
#define R1 1
|
| 331 |
|
|
#define R2 2
|
| 332 |
|
|
#define R3 3
|
| 333 |
|
|
#define R4 4
|
| 334 |
|
|
#define R5 5
|
| 335 |
|
|
#define R6 6
|
| 336 |
|
|
#define R7 7
|
| 337 |
|
|
#define R8 8
|
| 338 |
|
|
#define R9 9
|
| 339 |
|
|
#define R10 10
|
| 340 |
|
|
#define R11 11
|
| 341 |
|
|
#define R12 12
|
| 342 |
|
|
#define R13 13
|
| 343 |
|
|
#define R14 14
|
| 344 |
|
|
#define R15 15
|
| 345 |
|
|
|
| 346 |
|
|
#define NULLCODE 0 /* Null Code */
|
| 347 |
|
|
#define POINT_HIGH 0x8 /* Select upper half of registers */
|
| 348 |
|
|
#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
|
| 349 |
|
|
#define SEND_ABORT 0x18 /* HDLC Abort */
|
| 350 |
|
|
#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
|
| 351 |
|
|
#define RES_Tx_P 0x28 /* Reset TxINT Pending */
|
| 352 |
|
|
#define ERR_RES 0x30 /* Error Reset */
|
| 353 |
|
|
#define RES_H_IUS 0x38 /* Reset highest IUS */
|
| 354 |
|
|
|
| 355 |
|
|
#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
|
| 356 |
|
|
#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
|
| 357 |
|
|
#define RES_EOM_L 0xC0 /* Reset EOM latch */
|
| 358 |
|
|
|
| 359 |
|
|
/* Write Register 1 */
|
| 360 |
|
|
|
| 361 |
|
|
#define EXT_INT_ENAB 0x1 /* Ext Int Enable */
|
| 362 |
|
|
#define TxINT_ENAB 0x2 /* Tx Int Enable */
|
| 363 |
|
|
#define PAR_SPEC 0x4 /* Parity is special condition */
|
| 364 |
|
|
|
| 365 |
|
|
#define RxINT_DISAB 0 /* Rx Int Disable */
|
| 366 |
|
|
#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
|
| 367 |
|
|
#define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
|
| 368 |
|
|
#define INT_ERR_Rx 0x18 /* Int on error only */
|
| 369 |
|
|
|
| 370 |
|
|
#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
|
| 371 |
|
|
#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
|
| 372 |
|
|
#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
|
| 373 |
|
|
|
| 374 |
|
|
/* Write Register 2 (Interrupt Vector) */
|
| 375 |
|
|
|
| 376 |
|
|
/* Write Register 3 */
|
| 377 |
|
|
|
| 378 |
|
|
#define RxENABLE 0x1 /* Rx Enable */
|
| 379 |
|
|
#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
|
| 380 |
|
|
#define ADD_SM 0x4 /* Address Search Mode (SDLC) */
|
| 381 |
|
|
#define RxCRC_ENAB 0x8 /* Rx CRC Enable */
|
| 382 |
|
|
#define ENT_HM 0x10 /* Enter Hunt Mode */
|
| 383 |
|
|
#define AUTO_ENAB 0x20 /* Auto Enables */
|
| 384 |
|
|
#define Rx5 0x0 /* Rx 5 Bits/Character */
|
| 385 |
|
|
#define Rx7 0x40 /* Rx 7 Bits/Character */
|
| 386 |
|
|
#define Rx6 0x80 /* Rx 6 Bits/Character */
|
| 387 |
|
|
#define Rx8 0xc0 /* Rx 8 Bits/Character */
|
| 388 |
|
|
|
| 389 |
|
|
/* Write Register 4 */
|
| 390 |
|
|
|
| 391 |
|
|
#define PAR_ENA 0x1 /* Parity Enable */
|
| 392 |
|
|
#define PAR_EVEN 0x2 /* Parity Even/Odd* */
|
| 393 |
|
|
|
| 394 |
|
|
#define SYNC_ENAB 0 /* Sync Modes Enable */
|
| 395 |
|
|
#define SB1 0x4 /* 1 stop bit/char */
|
| 396 |
|
|
#define SB15 0x8 /* 1.5 stop bits/char */
|
| 397 |
|
|
#define SB2 0xc /* 2 stop bits/char */
|
| 398 |
|
|
|
| 399 |
|
|
#define MONSYNC 0 /* 8 Bit Sync character */
|
| 400 |
|
|
#define BISYNC 0x10 /* 16 bit sync character */
|
| 401 |
|
|
#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
|
| 402 |
|
|
#define EXTSYNC 0x30 /* External Sync Mode */
|
| 403 |
|
|
|
| 404 |
|
|
#define X1CLK 0x0 /* x1 clock mode */
|
| 405 |
|
|
#define X16CLK 0x40 /* x16 clock mode */
|
| 406 |
|
|
#define X32CLK 0x80 /* x32 clock mode */
|
| 407 |
|
|
#define X64CLK 0xC0 /* x64 clock mode */
|
| 408 |
|
|
|
| 409 |
|
|
/* Write Register 5 */
|
| 410 |
|
|
|
| 411 |
|
|
#define TxCRC_ENAB 0x1 /* Tx CRC Enable */
|
| 412 |
|
|
#define RTS 0x2 /* RTS */
|
| 413 |
|
|
#define SDLC_CRC 0x4 /* SDLC/CRC-16 */
|
| 414 |
|
|
#define TxENAB 0x8 /* Tx Enable */
|
| 415 |
|
|
#define SND_BRK 0x10 /* Send Break */
|
| 416 |
|
|
#define Tx5 0x0 /* Tx 5 bits (or less)/character */
|
| 417 |
|
|
#define Tx7 0x20 /* Tx 7 bits/character */
|
| 418 |
|
|
#define Tx6 0x40 /* Tx 6 bits/character */
|
| 419 |
|
|
#define Tx8 0x60 /* Tx 8 bits/character */
|
| 420 |
|
|
#define DTR 0x80 /* DTR */
|
| 421 |
|
|
|
| 422 |
|
|
/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
|
| 423 |
|
|
|
| 424 |
|
|
/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
|
| 425 |
|
|
|
| 426 |
|
|
/* Write Register 8 (transmit buffer) */
|
| 427 |
|
|
|
| 428 |
|
|
/* Write Register 9 (Master interrupt control) */
|
| 429 |
|
|
#define VIS 1 /* Vector Includes Status */
|
| 430 |
|
|
#define NV 2 /* No Vector */
|
| 431 |
|
|
#define DLC 4 /* Disable Lower Chain */
|
| 432 |
|
|
#define MIE 8 /* Master Interrupt Enable */
|
| 433 |
|
|
#define STATHI 0x10 /* Status high */
|
| 434 |
|
|
#define NORESET 0 /* No reset on write to R9 */
|
| 435 |
|
|
#define CHRB 0x40 /* Reset channel B */
|
| 436 |
|
|
#define CHRA 0x80 /* Reset channel A */
|
| 437 |
|
|
#define FHWRES 0xc0 /* Force hardware reset */
|
| 438 |
|
|
|
| 439 |
|
|
/* Write Register 10 (misc control bits) */
|
| 440 |
|
|
#define BIT6 1 /* 6 bit/8bit sync */
|
| 441 |
|
|
#define LOOPMODE 2 /* SDLC Loop mode */
|
| 442 |
|
|
#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
|
| 443 |
|
|
#define MARKIDLE 8 /* Mark/flag on idle */
|
| 444 |
|
|
#define GAOP 0x10 /* Go active on poll */
|
| 445 |
|
|
#define NRZ 0 /* NRZ mode */
|
| 446 |
|
|
#define NRZI 0x20 /* NRZI mode */
|
| 447 |
|
|
#define FM1 0x40 /* FM1 (transition = 1) */
|
| 448 |
|
|
#define FM0 0x60 /* FM0 (transition = 0) */
|
| 449 |
|
|
#define CRCPS 0x80 /* CRC Preset I/O */
|
| 450 |
|
|
|
| 451 |
|
|
/* Write Register 11 (Clock Mode control) */
|
| 452 |
|
|
#define TRxCXT 0 /* TRxC = Xtal output */
|
| 453 |
|
|
#define TRxCTC 1 /* TRxC = Transmit clock */
|
| 454 |
|
|
#define TRxCBR 2 /* TRxC = BR Generator Output */
|
| 455 |
|
|
#define TRxCDP 3 /* TRxC = DPLL output */
|
| 456 |
|
|
#define TRxCOI 4 /* TRxC O/I */
|
| 457 |
|
|
#define TCRTxCP 0 /* Transmit clock = RTxC pin */
|
| 458 |
|
|
#define TCTRxCP 8 /* Transmit clock = TRxC pin */
|
| 459 |
|
|
#define TCBR 0x10 /* Transmit clock = BR Generator output */
|
| 460 |
|
|
#define TCDPLL 0x18 /* Transmit clock = DPLL output */
|
| 461 |
|
|
#define RCRTxCP 0 /* Receive clock = RTxC pin */
|
| 462 |
|
|
#define RCTRxCP 0x20 /* Receive clock = TRxC pin */
|
| 463 |
|
|
#define RCBR 0x40 /* Receive clock = BR Generator output */
|
| 464 |
|
|
#define RCDPLL 0x60 /* Receive clock = DPLL output */
|
| 465 |
|
|
#define RTxCX 0x80 /* RTxC Xtal/No Xtal */
|
| 466 |
|
|
|
| 467 |
|
|
/* Write Register 12 (lower byte of baud rate generator time constant) */
|
| 468 |
|
|
|
| 469 |
|
|
/* Write Register 13 (upper byte of baud rate generator time constant) */
|
| 470 |
|
|
|
| 471 |
|
|
/* Write Register 14 (Misc control bits) */
|
| 472 |
|
|
#define BRENABL 1 /* Baud rate generator enable */
|
| 473 |
|
|
#define BRSRC 2 /* Baud rate generator source */
|
| 474 |
|
|
#define DTRREQ 4 /* DTR/Request function */
|
| 475 |
|
|
#define AUTOECHO 8 /* Auto Echo */
|
| 476 |
|
|
#define LOOPBAK 0x10 /* Local loopback */
|
| 477 |
|
|
#define SEARCH 0x20 /* Enter search mode */
|
| 478 |
|
|
#define RMC 0x40 /* Reset missing clock */
|
| 479 |
|
|
#define DISDPLL 0x60 /* Disable DPLL */
|
| 480 |
|
|
#define SSBR 0x80 /* Set DPLL source = BR generator */
|
| 481 |
|
|
#define SSRTxC 0xa0 /* Set DPLL source = RTxC */
|
| 482 |
|
|
#define SFMM 0xc0 /* Set FM mode */
|
| 483 |
|
|
#define SNRZI 0xe0 /* Set NRZI mode */
|
| 484 |
|
|
|
| 485 |
|
|
/* Write Register 15 (external/status interrupt control) */
|
| 486 |
|
|
#define ZCIE 2 /* Zero count IE */
|
| 487 |
|
|
#define DCDIE 8 /* DCD IE */
|
| 488 |
|
|
#define SYNCIE 0x10 /* Sync/hunt IE */
|
| 489 |
|
|
#define CTSIE 0x20 /* CTS IE */
|
| 490 |
|
|
#define TxUIE 0x40 /* Tx Underrun/EOM IE */
|
| 491 |
|
|
#define BRKIE 0x80 /* Break/Abort IE */
|
| 492 |
|
|
|
| 493 |
|
|
|
| 494 |
|
|
/* Read Register 0 */
|
| 495 |
|
|
#define Rx_CH_AV 0x1 /* Rx Character Available */
|
| 496 |
|
|
#define ZCOUNT 0x2 /* Zero count */
|
| 497 |
|
|
#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
|
| 498 |
|
|
#define DCD 0x8 /* DCD */
|
| 499 |
|
|
#define SYNC_HUNT 0x10 /* Sync/hunt */
|
| 500 |
|
|
#define CTS 0x20 /* CTS */
|
| 501 |
|
|
#define TxEOM 0x40 /* Tx underrun */
|
| 502 |
|
|
#define BRK_ABRT 0x80 /* Break/Abort */
|
| 503 |
|
|
|
| 504 |
|
|
/* Read Register 1 */
|
| 505 |
|
|
#define ALL_SNT 0x1 /* All sent */
|
| 506 |
|
|
/* Residue Data for 8 Rx bits/char programmed */
|
| 507 |
|
|
#define RES3 0x8 /* 0/3 */
|
| 508 |
|
|
#define RES4 0x4 /* 0/4 */
|
| 509 |
|
|
#define RES5 0xc /* 0/5 */
|
| 510 |
|
|
#define RES6 0x2 /* 0/6 */
|
| 511 |
|
|
#define RES7 0xa /* 0/7 */
|
| 512 |
|
|
#define RES8 0x6 /* 0/8 */
|
| 513 |
|
|
#define RES18 0xe /* 1/8 */
|
| 514 |
|
|
#define RES28 0x0 /* 2/8 */
|
| 515 |
|
|
/* Special Rx Condition Interrupts */
|
| 516 |
|
|
#define PAR_ERR 0x10 /* Parity error */
|
| 517 |
|
|
#define Rx_OVR 0x20 /* Rx Overrun Error */
|
| 518 |
|
|
#define CRC_ERR 0x40 /* CRC/Framing Error */
|
| 519 |
|
|
#define END_FR 0x80 /* End of Frame (SDLC) */
|
| 520 |
|
|
|
| 521 |
|
|
/* Read Register 2 (channel B only) - Interrupt vector */
|
| 522 |
|
|
|
| 523 |
|
|
#define VECTOR_MASK 0x06
|
| 524 |
|
|
|
| 525 |
|
|
#define TXINT 0x00
|
| 526 |
|
|
#define EXINT 0x02
|
| 527 |
|
|
#define RXINT 0x04
|
| 528 |
|
|
#define SPINT 0x06
|
| 529 |
|
|
|
| 530 |
|
|
|
| 531 |
|
|
/* Read Register 3 (interrupt pending register) ch a only */
|
| 532 |
|
|
#define CHBEXT 0x1 /* Channel B Ext/Stat IP */
|
| 533 |
|
|
#define CHBTxIP 0x2 /* Channel B Tx IP */
|
| 534 |
|
|
#define CHBRxIP 0x4 /* Channel B Rx IP */
|
| 535 |
|
|
#define CHAEXT 0x8 /* Channel A Ext/Stat IP */
|
| 536 |
|
|
#define CHATxIP 0x10 /* Channel A Tx IP */
|
| 537 |
|
|
#define CHARxIP 0x20 /* Channel A Rx IP */
|
| 538 |
|
|
|
| 539 |
|
|
/* Read Register 8 (receive data register) */
|
| 540 |
|
|
|
| 541 |
|
|
/* Read Register 10 (misc status bits) */
|
| 542 |
|
|
#define ONLOOP 2 /* On loop */
|
| 543 |
|
|
#define LOOPSEND 0x10 /* Loop sending */
|
| 544 |
|
|
#define CLK2MIS 0x40 /* Two clocks missing */
|
| 545 |
|
|
#define CLK1MIS 0x80 /* One clock missing */
|
| 546 |
|
|
|
| 547 |
|
|
/* Read Register 12 (lower byte of baud rate generator constant) */
|
| 548 |
|
|
|
| 549 |
|
|
/* Read Register 13 (upper byte of baud rate generator constant) */
|
| 550 |
|
|
|
| 551 |
|
|
/* Read Register 15 (value of WR 15) */
|
| 552 |
|
|
|
| 553 |
|
|
|
| 554 |
|
|
/* 8536 register definitions */
|
| 555 |
|
|
|
| 556 |
|
|
#define CIO_MICR 0x00 /* Master interrupt control register */
|
| 557 |
|
|
#define CIO_MCCR 0x01 /* Master configuration control register */
|
| 558 |
|
|
#define CIO_CTMS1 0x1c /* Counter/timer mode specification #1 */
|
| 559 |
|
|
#define CIO_CTMS2 0x1d /* Counter/timer mode specification #2 */
|
| 560 |
|
|
#define CIO_CTMS3 0x1e /* Counter/timer mode specification #3 */
|
| 561 |
|
|
#define CIO_IVR 0x04 /* Interrupt vector register */
|
| 562 |
|
|
|
| 563 |
|
|
#define CIO_CSR1 0x0a /* Command and status register CTC #1 */
|
| 564 |
|
|
#define CIO_CSR2 0x0b /* Command and status register CTC #2 */
|
| 565 |
|
|
#define CIO_CSR3 0x0c /* Command and status register CTC #3 */
|
| 566 |
|
|
|
| 567 |
|
|
#define CIO_CT1MSB 0x16 /* CTC #1 Timer constant - MSB */
|
| 568 |
|
|
#define CIO_CT1LSB 0x17 /* CTC #1 Timer constant - LSB */
|
| 569 |
|
|
#define CIO_CT2MSB 0x18 /* CTC #2 Timer constant - MSB */
|
| 570 |
|
|
#define CIO_CT2LSB 0x19 /* CTC #2 Timer constant - LSB */
|
| 571 |
|
|
#define CIO_CT3MSB 0x1a /* CTC #3 Timer constant - MSB */
|
| 572 |
|
|
#define CIO_CT3LSB 0x1b /* CTC #3 Timer constant - LSB */
|
| 573 |
|
|
#define CIO_PDCA 0x23 /* Port A data direction control */
|
| 574 |
|
|
#define CIO_PDCB 0x2b /* Port B data direction control */
|
| 575 |
|
|
|
| 576 |
|
|
#define CIO_GCB 0x04 /* CTC Gate command bit */
|
| 577 |
|
|
#define CIO_TCB 0x02 /* CTC Trigger command bit */
|
| 578 |
|
|
#define CIO_IE 0xc0 /* CTC Interrupt enable (set) */
|
| 579 |
|
|
#define CIO_CIP 0x20 /* CTC Clear interrupt pending */
|
| 580 |
|
|
#define CIO_IP 0x20 /* CTC Interrupt pending */
|
| 581 |
|
|
|
| 582 |
|
|
|
| 583 |
|
|
/* 8580/85180/85280 Enhanced SCC register definitions */
|
| 584 |
|
|
|
| 585 |
|
|
/* Write Register 7' (SDLC/HDLC Programmable Enhancements) */
|
| 586 |
|
|
#define AUTOTXF 0x01 /* Auto Tx Flag */
|
| 587 |
|
|
#define AUTOEOM 0x02 /* Auto EOM Latch Reset */
|
| 588 |
|
|
#define AUTORTS 0x04 /* Auto RTS */
|
| 589 |
|
|
#define TXDNRZI 0x08 /* TxD Pulled High in SDLC NRZI mode */
|
| 590 |
|
|
#define FASTDTR 0x10 /* Fast DTR/REQ Mode */
|
| 591 |
|
|
#define CRCCBCR 0x20 /* CRC Check Bytes Completely Received */
|
| 592 |
|
|
#define EXTRDEN 0x40 /* Extended Read Enabled */
|
| 593 |
|
|
|
| 594 |
|
|
/* Write Register 15 (external/status interrupt control) */
|
| 595 |
|
|
#define SHDLCE 1 /* SDLC/HDLC Enhancements Enable */
|
| 596 |
|
|
#define FIFOE 4 /* FIFO Enable */
|
| 597 |
|
|
|
| 598 |
|
|
/* Read Register 6 (frame status FIFO) */
|
| 599 |
|
|
#define BCLSB 0xff /* LSB of 14 bits count */
|
| 600 |
|
|
|
| 601 |
|
|
/* Read Register 7 (frame status FIFO) */
|
| 602 |
|
|
#define BCMSB 0x3f /* MSB of 14 bits count */
|
| 603 |
|
|
#define FDA 0x40 /* FIFO Data Available Status */
|
| 604 |
|
|
#define FOY 0x80 /* FIFO Overflow Status */
|
| 605 |
|
|
|
| 606 |
|
|
#endif /* _SCC_H */
|
| 607 |
|
|
|
| 608 |
|
|
/* global functions */
|
| 609 |
|
|
|
| 610 |
|
|
extern int scc_init(void);
|
