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199 |
simons |
#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <asm/segment.h>
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#include "ieee-math.h"
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#define OPC_PAL 0x00
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#define OPC_INTA 0x10
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#define OPC_INTL 0x11
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#define OPC_INTS 0x12
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#define OPC_INTM 0x13
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#define OPC_FLTV 0x15
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#define OPC_FLTI 0x16
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#define OPC_FLTL 0x17
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#define OPC_MISC 0x18
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#define OPC_JSR 0x1a
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/*
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* "Base" function codes for the FLTI-class instructions. These
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* instructions all have opcode 0x16. Note that in most cases these
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* actually correspond to the "chopped" form of the instruction. Not
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* to worry---we extract the qualifier bits separately and deal with
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* them separately. Notice that base function code 0x2c is used for
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* both CVTTS and CVTST. The other bits in the function code are used
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* to distinguish the two.
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*/
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#define FLTI_FUNC_ADDS 0x000
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#define FLTI_FUNC_ADDT 0x020
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#define FLTI_FUNC_CMPTEQ 0x025
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#define FLTI_FUNC_CMPTLT 0x026
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#define FLTI_FUNC_CMPTLE 0x027
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#define FLTI_FUNC_CMPTUN 0x024
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#define FLTI_FUNC_CVTTS_or_CVTST 0x02c
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#define FLTI_FUNC_CVTTQ 0x02f
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#define FLTI_FUNC_CVTQS 0x03c
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#define FLTI_FUNC_CVTQT 0x03e
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#define FLTI_FUNC_DIVS 0x003
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#define FLTI_FUNC_DIVT 0x023
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#define FLTI_FUNC_MULS 0x002
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#define FLTI_FUNC_MULT 0x022
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#define FLTI_FUNC_SUBS 0x001
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#define FLTI_FUNC_SUBT 0x021
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#define FLTI_FUNC_CVTQL 0x030 /* opcode 0x17 */
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#define MISC_TRAPB 0x0000
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#define MISC_EXCB 0x0400
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extern unsigned long rdfpcr (void);
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extern void wrfpcr (unsigned long);
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unsigned long
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alpha_read_fp_reg (unsigned long reg)
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{
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unsigned long r;
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switch (reg) {
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case 0: asm ("stt $f0,%0" : "m="(r)); break;
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case 1: asm ("stt $f1,%0" : "m="(r)); break;
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case 2: asm ("stt $f2,%0" : "m="(r)); break;
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case 3: asm ("stt $f3,%0" : "m="(r)); break;
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case 4: asm ("stt $f4,%0" : "m="(r)); break;
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case 5: asm ("stt $f5,%0" : "m="(r)); break;
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case 6: asm ("stt $f6,%0" : "m="(r)); break;
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case 7: asm ("stt $f7,%0" : "m="(r)); break;
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case 8: asm ("stt $f8,%0" : "m="(r)); break;
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case 9: asm ("stt $f9,%0" : "m="(r)); break;
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case 10: asm ("stt $f10,%0" : "m="(r)); break;
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case 11: asm ("stt $f11,%0" : "m="(r)); break;
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case 12: asm ("stt $f12,%0" : "m="(r)); break;
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case 13: asm ("stt $f13,%0" : "m="(r)); break;
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case 14: asm ("stt $f14,%0" : "m="(r)); break;
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case 15: asm ("stt $f15,%0" : "m="(r)); break;
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case 16: asm ("stt $f16,%0" : "m="(r)); break;
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case 17: asm ("stt $f17,%0" : "m="(r)); break;
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case 18: asm ("stt $f18,%0" : "m="(r)); break;
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case 19: asm ("stt $f19,%0" : "m="(r)); break;
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case 20: asm ("stt $f20,%0" : "m="(r)); break;
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case 21: asm ("stt $f21,%0" : "m="(r)); break;
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case 22: asm ("stt $f22,%0" : "m="(r)); break;
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case 23: asm ("stt $f23,%0" : "m="(r)); break;
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case 24: asm ("stt $f24,%0" : "m="(r)); break;
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case 25: asm ("stt $f25,%0" : "m="(r)); break;
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case 26: asm ("stt $f26,%0" : "m="(r)); break;
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case 27: asm ("stt $f27,%0" : "m="(r)); break;
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case 28: asm ("stt $f28,%0" : "m="(r)); break;
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case 29: asm ("stt $f29,%0" : "m="(r)); break;
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case 30: asm ("stt $f30,%0" : "m="(r)); break;
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case 31: asm ("stt $f31,%0" : "m="(r)); break;
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default:
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break;
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}
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return r;
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}
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#if 0
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/*
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* This is IMHO the better way of implementing LDT(). But it
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* has the disadvantage that gcc 2.7.0 refuses to compile it
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* (invalid operand constraints), so instead, we use the uglier
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* macro below.
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*/
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# define LDT(reg,val) \
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asm volatile ("ldt $f"#reg",%0" :: "m"(val));
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#else
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# define LDT(reg,val) \
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asm volatile ("ldt $f"#reg",0(%0)" :: "r"(&val));
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#endif
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void
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alpha_write_fp_reg (unsigned long reg, unsigned long val)
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{
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switch (reg) {
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case 0: LDT( 0, val); break;
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case 1: LDT( 1, val); break;
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case 2: LDT( 2, val); break;
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case 3: LDT( 3, val); break;
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case 4: LDT( 4, val); break;
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case 5: LDT( 5, val); break;
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case 6: LDT( 6, val); break;
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case 7: LDT( 7, val); break;
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case 8: LDT( 8, val); break;
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case 9: LDT( 9, val); break;
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case 10: LDT(10, val); break;
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case 11: LDT(11, val); break;
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case 12: LDT(12, val); break;
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case 13: LDT(13, val); break;
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case 14: LDT(14, val); break;
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case 15: LDT(15, val); break;
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case 16: LDT(16, val); break;
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case 17: LDT(17, val); break;
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case 18: LDT(18, val); break;
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case 19: LDT(19, val); break;
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case 20: LDT(20, val); break;
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case 21: LDT(21, val); break;
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case 22: LDT(22, val); break;
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case 23: LDT(23, val); break;
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case 24: LDT(24, val); break;
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case 25: LDT(25, val); break;
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case 26: LDT(26, val); break;
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case 27: LDT(27, val); break;
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case 28: LDT(28, val); break;
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case 29: LDT(29, val); break;
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case 30: LDT(30, val); break;
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case 31: LDT(31, val); break;
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default:
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break;
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}
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}
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/*
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* Emulate the floating point instruction at address PC. Returns 0 if
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* emulation fails. Notice that the kernel does not and cannot use FP
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* regs. This is good because it means that instead of
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* saving/restoring all fp regs, we simply stick the result of the
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* operation into the appropriate register.
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*/
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long
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alpha_fp_emul (unsigned long pc)
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{
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unsigned long opcode, fa, fb, fc, func, mode;
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unsigned long fpcw = current->tss.flags;
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unsigned long va, vb, vc, res, fpcr;
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__u32 insn;
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insn = get_user((__u32*)pc);
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fc = (insn >> 0) & 0x1f; /* destination register */
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func = (insn >> 5) & 0x7ff;
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fb = (insn >> 16) & 0x1f;
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fa = (insn >> 21) & 0x1f;
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opcode = insn >> 26;
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va = alpha_read_fp_reg(fa);
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vb = alpha_read_fp_reg(fb);
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fpcr = rdfpcr();
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/*
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* Try the operation in software. First, obtain the rounding
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* mode...
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*/
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mode = func & 0xc0;
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if (mode == 0xc0) {
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/* dynamic---get rounding mode from fpcr: */
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mode = ((fpcr & FPCR_DYN_MASK) >> FPCR_DYN_SHIFT) << ROUND_SHIFT;
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}
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mode |= (fpcw & IEEE_TRAP_ENABLE_MASK);
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if ((IEEE_TRAP_ENABLE_MASK & 0xc0)) {
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extern int something_is_wrong (void);
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something_is_wrong();
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}
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| 203 |
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/* least 6 bits contain operation code: */
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| 204 |
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switch (func & 0x3f) {
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case FLTI_FUNC_CMPTEQ:
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| 206 |
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res = ieee_CMPTEQ(va, vb, &vc);
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| 207 |
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break;
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| 208 |
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| 209 |
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case FLTI_FUNC_CMPTLT:
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| 210 |
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res = ieee_CMPTLT(va, vb, &vc);
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| 211 |
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break;
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| 212 |
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| 213 |
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case FLTI_FUNC_CMPTLE:
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| 214 |
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res = ieee_CMPTLE(va, vb, &vc);
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| 215 |
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break;
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| 216 |
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| 217 |
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case FLTI_FUNC_CMPTUN:
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| 218 |
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res = ieee_CMPTUN(va, vb, &vc);
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| 219 |
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break;
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| 220 |
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| 221 |
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case FLTI_FUNC_CVTQL:
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| 222 |
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/*
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| 223 |
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* Notice: We can get here only due to an integer
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| 224 |
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* overflow. Such overflows are reported as invalid
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| 225 |
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* ops. We return the result the hw would have
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| 226 |
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* computed.
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| 227 |
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*/
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| 228 |
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vc = ((vb & 0xc0000000) << 32 | /* sign and msb */
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| 229 |
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(vb & 0x3fffffff) << 29); /* rest of the integer */
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| 230 |
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res = FPCR_INV;
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| 231 |
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break;
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| 232 |
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| 233 |
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case FLTI_FUNC_CVTQS:
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| 234 |
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res = ieee_CVTQS(mode, vb, &vc);
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| 235 |
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break;
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| 236 |
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| 237 |
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case FLTI_FUNC_CVTQT:
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| 238 |
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res = ieee_CVTQT(mode, vb, &vc);
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| 239 |
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break;
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| 240 |
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| 241 |
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case FLTI_FUNC_CVTTS_or_CVTST:
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| 242 |
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if (func == 0x6ac) {
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| 243 |
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/*
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| 244 |
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* 0x2ac is also CVTST, but if the /S
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| 245 |
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* qualifier isn't set, we wouldn't be here in
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| 246 |
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* the first place...
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| 247 |
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*/
|
| 248 |
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res = ieee_CVTST(mode, vb, &vc);
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| 249 |
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} else {
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| 250 |
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res = ieee_CVTTS(mode, vb, &vc);
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| 251 |
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}
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| 252 |
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break;
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| 253 |
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| 254 |
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case FLTI_FUNC_DIVS:
|
| 255 |
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res = ieee_DIVS(mode, va, vb, &vc);
|
| 256 |
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break;
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| 257 |
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|
| 258 |
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case FLTI_FUNC_DIVT:
|
| 259 |
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res = ieee_DIVT(mode, va, vb, &vc);
|
| 260 |
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break;
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| 261 |
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| 262 |
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case FLTI_FUNC_MULS:
|
| 263 |
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res = ieee_MULS(mode, va, vb, &vc);
|
| 264 |
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break;
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| 265 |
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|
| 266 |
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case FLTI_FUNC_MULT:
|
| 267 |
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res = ieee_MULT(mode, va, vb, &vc);
|
| 268 |
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break;
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| 269 |
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|
| 270 |
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case FLTI_FUNC_SUBS:
|
| 271 |
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res = ieee_SUBS(mode, va, vb, &vc);
|
| 272 |
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break;
|
| 273 |
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|
| 274 |
|
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case FLTI_FUNC_SUBT:
|
| 275 |
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res = ieee_SUBT(mode, va, vb, &vc);
|
| 276 |
|
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break;
|
| 277 |
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|
| 278 |
|
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case FLTI_FUNC_ADDS:
|
| 279 |
|
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res = ieee_ADDS(mode, va, vb, &vc);
|
| 280 |
|
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break;
|
| 281 |
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|
| 282 |
|
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case FLTI_FUNC_ADDT:
|
| 283 |
|
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res = ieee_ADDT(mode, va, vb, &vc);
|
| 284 |
|
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break;
|
| 285 |
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|
| 286 |
|
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case FLTI_FUNC_CVTTQ:
|
| 287 |
|
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res = ieee_CVTTQ(mode, vb, &vc);
|
| 288 |
|
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break;
|
| 289 |
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|
| 290 |
|
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default:
|
| 291 |
|
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printk("alpha_fp_emul: unexpected function code %#lx at %#lx\n",
|
| 292 |
|
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func & 0x3f, pc);
|
| 293 |
|
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return 0;
|
| 294 |
|
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}
|
| 295 |
|
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/*
|
| 296 |
|
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* Take the appropriate action for each possible
|
| 297 |
|
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* floating-point result:
|
| 298 |
|
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*
|
| 299 |
|
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* - Set the appropriate bits in the FPCR
|
| 300 |
|
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* - If the specified exception is enabled in the FPCR,
|
| 301 |
|
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* return. The caller (entArith) will dispatch
|
| 302 |
|
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* the appropriate signal to the translated program.
|
| 303 |
|
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*
|
| 304 |
|
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* In addition, properly track the exception state in software
|
| 305 |
|
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* as described in Alpha Architecture Handbook 4.7.7.3.
|
| 306 |
|
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*/
|
| 307 |
|
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if (res) {
|
| 308 |
|
|
/* record exceptions in software control word. */
|
| 309 |
|
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fpcw |= res >> 35;
|
| 310 |
|
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current->tss.flags = fpcw;
|
| 311 |
|
|
|
| 312 |
|
|
/* update hardware control register, disabling hardware
|
| 313 |
|
|
exceptions for disabled software exceptions for which
|
| 314 |
|
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we have a status. (no, really.) */
|
| 315 |
|
|
fpcr &= (~FPCR_MASK | FPCR_DYN_MASK);
|
| 316 |
|
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fpcr |= ieee_sw_to_fpcr(fpcw | (~fpcw & IEEE_STATUS_MASK)>>16);
|
| 317 |
|
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wrfpcr(fpcr);
|
| 318 |
|
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|
| 319 |
|
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/* Do we generate a signal? */
|
| 320 |
|
|
if (res >> 51 & fpcw & IEEE_TRAP_ENABLE_MASK)
|
| 321 |
|
|
return 0;
|
| 322 |
|
|
}
|
| 323 |
|
|
|
| 324 |
|
|
/*
|
| 325 |
|
|
* Whoo-kay... we got this far, and we're not generating a signal
|
| 326 |
|
|
* to the translated program. All that remains is to write the
|
| 327 |
|
|
* result:
|
| 328 |
|
|
*/
|
| 329 |
|
|
alpha_write_fp_reg(fc, vc);
|
| 330 |
|
|
return 1;
|
| 331 |
|
|
}
|
| 332 |
|
|
|
| 333 |
|
|
|
| 334 |
|
|
long
|
| 335 |
|
|
alpha_fp_emul_imprecise (struct pt_regs *regs, unsigned long write_mask)
|
| 336 |
|
|
{
|
| 337 |
|
|
unsigned long trigger_pc = regs->pc - 4;
|
| 338 |
|
|
unsigned long insn, opcode, rc;
|
| 339 |
|
|
/*
|
| 340 |
|
|
* Turn off the bits corresponding to registers that are the
|
| 341 |
|
|
* target of instructions that set bits in the exception
|
| 342 |
|
|
* summary register. We have some slack doing this because a
|
| 343 |
|
|
* register that is the target of a trapping instruction can
|
| 344 |
|
|
* be written at most once in the trap shadow.
|
| 345 |
|
|
*
|
| 346 |
|
|
* Branches, jumps, TRAPBs, EXCBs and calls to PALcode all
|
| 347 |
|
|
* bound the trap shadow, so we need not look any further than
|
| 348 |
|
|
* up to the first occurrence of such an instruction.
|
| 349 |
|
|
*/
|
| 350 |
|
|
while (write_mask) {
|
| 351 |
|
|
insn = get_user((__u32*)(trigger_pc));
|
| 352 |
|
|
opcode = insn >> 26;
|
| 353 |
|
|
rc = insn & 0x1f;
|
| 354 |
|
|
|
| 355 |
|
|
switch (opcode) {
|
| 356 |
|
|
case OPC_PAL:
|
| 357 |
|
|
case OPC_JSR:
|
| 358 |
|
|
case 0x30 ... 0x3f: /* branches */
|
| 359 |
|
|
return 0;
|
| 360 |
|
|
|
| 361 |
|
|
case OPC_MISC:
|
| 362 |
|
|
switch (insn & 0xffff) {
|
| 363 |
|
|
case MISC_TRAPB:
|
| 364 |
|
|
case MISC_EXCB:
|
| 365 |
|
|
return 0;
|
| 366 |
|
|
|
| 367 |
|
|
default:
|
| 368 |
|
|
break;
|
| 369 |
|
|
}
|
| 370 |
|
|
break;
|
| 371 |
|
|
|
| 372 |
|
|
case OPC_INTA:
|
| 373 |
|
|
case OPC_INTL:
|
| 374 |
|
|
case OPC_INTS:
|
| 375 |
|
|
case OPC_INTM:
|
| 376 |
|
|
write_mask &= ~(1UL << rc);
|
| 377 |
|
|
break;
|
| 378 |
|
|
|
| 379 |
|
|
case OPC_FLTV:
|
| 380 |
|
|
case OPC_FLTI:
|
| 381 |
|
|
case OPC_FLTL:
|
| 382 |
|
|
write_mask &= ~(1UL << (rc + 32));
|
| 383 |
|
|
break;
|
| 384 |
|
|
}
|
| 385 |
|
|
if (!write_mask) {
|
| 386 |
|
|
if ((opcode == OPC_FLTI || opcode == OPC_FLTL)
|
| 387 |
|
|
&& alpha_fp_emul(trigger_pc))
|
| 388 |
|
|
{
|
| 389 |
|
|
/* re-execute insns in trap-shadow: */
|
| 390 |
|
|
regs->pc = trigger_pc + 4;
|
| 391 |
|
|
return 1;
|
| 392 |
|
|
}
|
| 393 |
|
|
break;
|
| 394 |
|
|
}
|
| 395 |
|
|
trigger_pc -= 4;
|
| 396 |
|
|
}
|
| 397 |
|
|
return 0;
|
| 398 |
|
|
}
|
