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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [arch/] [armnommu/] [kernel/] [head-armv.S] - Blame information for rev 199

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/*
 * linux/arch/arm/kernel/head32.S
 *
 * Copyright (C) 1994, 1995, 1996, 1997 Russell King
 *
 * Kernel 32 bit startup code for ARM6 / ARM7 / StrongARM
 */
#include 
                .text
                .align
 
                .globl  _swapper_pg_dir
                .equ    _swapper_pg_dir,        0xc0004000
 
                .globl  __entry
                .globl  __stext
/*
 * Entry point and restart point.  Entry *must* be called with r0 == 0,
 * MMU off.
 *
 *  r1 = 0 -> ebsa  (Ram @ 0x00000000)
 *  r1 = 1 -> RPC   (Ram @ 0x10000000)
 *  r1 = 2 -> ebsit (???)
 */
__stext:
__entry:
                teq     r0, #0                                  @ check for illegal entry...
                bne     Lerror                                  @ loop indefinitely
                cmp     r1, #2                                  @ Unknown machine architecture
                bge     Lerror
@
@ First thing to do is to get the page tables set up so that we can call the kernel
@ in the correct place.  This is relocatable code...
@
                mrc     p15, 0, r9, c0, c0                      @ get Processor ID
@
@ Read processor ID register (CP#15, CR0).
@ NOTE: ARM2 & ARM250 cause an undefined instruction exception...
@ Values are:
@               XX01XXXX = ARMv4 architecture (StrongARM)
@               XX00XXXX = ARMv3 architecture
@               4156061X = ARM 610
@               4156030X = ARM 3
@               4156025X = ARM 250
@               4156020X = ARM 2
@
                adr     r10, LCProcTypes
1:              ldmia   r10!, {r5, r6, r8}                      @ Get Set, Mask, MMU Flags
                teq     r5, #0                                  @ End of list?
                beq     Lerror
                eor     r5, r5, r9
                tst     r5, r6
                addne   r10, r10, #8
                bne     1b
 
                adr     r4, LCMachTypes
                add     r4, r4, r1, lsl #4
                ldmia   r4, {r4, r5, r6}                        @ r4 = page dir in physical ram
 
                mov     r0, r4
                mov     r1, #0
                add     r2, r0, #0x4000
1:              str     r1, [r0], #4                            @ Clear page table
                teq     r0, r2
                bne     1b
@
@ Add enough entries to allow the kernel to be called.
@ It will sort out the real mapping in paging_init
@
                add     r0, r4, #0x3000
                mov     r1, #0x0000000c                         @ SECT_CACHEABLE | SECT_BUFFERABLE
                orr     r1, r1, r8
                add     r1, r1, r5
                str     r1, [r0], #4
                add     r1, r1, #1 << 20
                str     r1, [r0], #4
                add     r1, r1, #1 << 20
@
@ Map in IO space
@
                add     r0, r4, #0x3800
                orr     r1, r6, r8
                add     r2, r0, #0x0800
1:              str     r1, [r0], #4
                add     r1, r1, #1 << 20
                teq     r0, r2
                bne     1b
@
@ Map in screen at 0x02000000 & SCREEN2_BASE
@
                teq     r5, #0
                addne   r0, r4, #0x80                           @ 02000000
                movne   r1, #0x02000000
                orrne   r1, r1, r8
                strne   r1, [r0]
                addne   r0, r4, #0x3600                         @ d8000000
                strne   r1, [r0]
@
@ The following should work on both v3 and v4 implementations
@
                mov     lr, pc
                mov     pc, r10                                 @ Call processor flush (returns ctrl reg)
                adr     r5, __entry
                sub     r10, r10, r5                            @ Make r10 PIC
 
                ldr     lr, Lbranch
                mcr     p15, 0, r0, c1, c0                      @ Enable MMU & caches.  In 3 instructions
                                                                @ we loose this page!
                mov     pc, lr
 
Lerror:         mov     r0, #0x02000000
                mov     r1, #0x11
                orr     r1, r1, r1, lsl #8
                orr     r1, r1, r1, lsl #16
                str     r1, [r0], #4
                str     r1, [r0], #4
                str     r1, [r0], #4
                str     r1, [r0], #4
                b       Lerror
 
Lbranch:        .long   Lalready_done_mmap                      @ Real address of routine
 
                @ EBSA (pg dir phys, phys ram start, phys i/o)
LCMachTypes:    .long   _swapper_pg_dir - 0xc0000000            @ Address of page tables (physical)
                .long   0                                        @ Address of RAM
                .long   0xe0000000                              @ I/O address
                .long   0
 
                @ RPC
                .long   _swapper_pg_dir - 0xc0000000 + 0x10000000
                .long   0x10000000
                .long   0x03000000
                .long   0
 
                @ EBSIT ???
                .long   _swapper_pg_dir - 0xc0000000
                .long   0
                .long   0xe0000000
                .long   0
 
LCProcTypes:    @ ARM6 / 610
                .long   0x41560600
                .long   0xffffff00
                .long   0x00000c12
                b       Larmv3_flush_early                      @ arm v3 flush & ctrl early setup
                mov     pc, lr
 
                @ ARM7
                .long   0x41007000
                .long   0xfffff000
                .long   0x00000c12
                b       Larmv3_flush_late                       @ arm v3 flush & ctrl late setup
                mov     pc, lr
 
                @ ARM710
                .long   0x41007000
                .long   0xfff8f000                              @ ARM710 does not follow spec
                .long   0x00000c12
                b       Larmv3_flush_late                       @ arm v3 flush & ctrl late setup
                mov     pc, lr
 
                @ StrongARM
                .long   0x4401a100
                .long   0xfffffff0
                .long   0x00000c02
                b       Larmv4_flush_early
                b       Lsa_fastclock
 
                .long   0
 
LC0:            .long   _edata
                .long   _arm_id
                .long   _end
                .long   _init_user_stack + 4096
                .align
 
Larmv3_flush_early:
                mov     r0, #0
                mcr     p15, 0, r0, c7, c0                      @ flush caches on v3
                mcr     p15, 0, r0, c5, c0                      @ flush TLBs on v3
                mcr     p15, 0, r4, c2, c0                      @ load page table pointer
                mov     r0, #5                                  @ Domains 0, 1 = client
                mcr     p15, 0, r0, c3, c0                      @ load domain access register
                mov     r0, #0x3d                               @ ....DPWCAM
                mov     pc, lr
 
Larmv3_flush_late:
                mov     r0, #0
                mcr     p15, 0, r0, c7, c0                      @ flush caches on v3
                mcr     p15, 0, r0, c5, c0                      @ flush TLBs on v3
                mcr     p15, 0, r4, c2, c0                      @ load page table pointer
                mov     r0, #5                                  @ Domains 0, 1 = client
                mcr     p15, 0, r0, c3, c0                      @ load domain access register
                mov     r0, #0x7d                               @ ...LDPWCAM
                mov     pc, lr
 
Larmv4_flush_early:
                mov     r0, #0
                mcr     p15, 0, r0, c7, c7                      @ flush I,D caches on v4
                mcr     p15, 0, r0, c7, c10, 4                  @ drain write buffer on v4
                mcr     p15, 0, r0, c8, c7                      @ flush I,D TLBs on v4
                mcr     p15, 0, r4, c2, c0                      @ load page table pointer
                mov     r0, #5                                  @ Domains 0, 1 = client
                mcr     p15, 0, r0, c3, c0                      @ load domain access register
                mrc     p15, 0, r0, c1, c0                      @ get control register v4
                orr     r0, r0, #0x3d                           @ I......DPWCAM
                orr     r0, r0, #1 << 12                        @ v4 supports separate I cache
                mov     pc, lr
 
Lsa_fastclock:  mcr     p15, 0, r4, c15, c1, 2                  @ Enable clock switching
                mov     pc, lr
 
Lalready_done_mmap:
                adr     r5, __entry                             @ Add base back in
                add     r10, r10, r5
 
                adr     r5, LC0
                ldmia   r5, {r5, r6, r8, sp}                    @ Setup stack
                mov     r4, #0
1:              cmp     r5, r8                                  @ Clear BSS
                strcc   r4, [r5],#4
                bcc     1b
 
                str     r9, [r6]                                @ Save processor ID
                mov     lr, pc
                add     pc, r10, #4                             @ Call post-processor init
 
                mov     fp, #0
                b       _start_kernel
 
#if 1
/*
 * Useful debugging routines
 */
                .globl  _printhex8
_printhex8:     mov     r1, #8
                b       printhex
 
                .globl  _printhex4
_printhex4:     mov     r1, #4
                b       printhex
 
                .globl  _printhex2
_printhex2:     mov     r1, #2
printhex:       ldr     r2, =hexbuf
                add     r3, r2, r1
                mov     r1, #0
                strb    r1, [r3]
1:              and     r1, r0, #15
                mov     r0, r0, lsr #4
                cmp     r1, #10
                addlt   r1, r1, #'0'
                addge   r1, r1, #'a' - 10
                strb    r1, [r3, #-1]!
                teq     r3, r2
                bne     1b
                mov     r0, r2
 
                .globl  _printascii
_printascii:
#ifdef CONFIG_ARCH_RPC
                mov     r3, #0xe0000000
                orr     r3, r3, #0x00010000
                orr     r3, r3, #0x00000fe0
#else
                mov     r3, #0xf0000000
                orr     r3, r3, #0x0be0
#endif
                b       3f
1:              ldrb    r2, [r3, #0x18]
                tst     r2, #0x10
                beq     1b
                strb    r1, [r3]
2:              ldrb    r2, [r3, #0x14]
                and     r2, r2, #0x60
                teq     r2, #0x60
                bne     2b
                teq     r1, #'\n'
                moveq   r1, #'\r'
                beq     1b
3:              teq     r0, #0
                ldrneb  r1, [r0], #1
                teqne   r1, #0
                bne     1b
                mov     pc, lr
 
                .globl  _printch
_printch:
#ifdef CONFIG_ARCH_RPC
                mov     r3, #0xe0000000
                orr     r3, r3, #0x00010000
                orr     r3, r3, #0x00000fe0
#else
                mov     r3, #0xf0000000
                orr     r3, r3, #0x0be0
#endif
                mov     r1, r0
                mov     r0, #0
                b       1b
 
                .bss
hexbuf:         .space 16
 
#endif
 

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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [arch/] [armnommu/] [kernel/] [head-armv.S] - Blame information for rev 199

Line No.	Rev	Author	Line
1	199	simons	`/*`
2			`* linux/arch/arm/kernel/head32.S`
3			`*`
4			`* Copyright (C) 1994, 1995, 1996, 1997 Russell King`
5			`*`
6			`* Kernel 32 bit startup code for ARM6 / ARM7 / StrongARM`
7			`*/`
8			`#include`
9			`.text`
10			`.align`
11
12			`.globl _swapper_pg_dir`
13			`.equ _swapper_pg_dir, 0xc0004000`
14
15			`.globl __entry`
16			`.globl __stext`
17			`/*`
18			`* Entry point and restart point. Entry must be called with r0 == 0,`
19			`* MMU off.`
20			`*`
21			`* r1 = 0 -> ebsa (Ram @ 0x00000000)`
22			`* r1 = 1 -> RPC (Ram @ 0x10000000)`
23			`* r1 = 2 -> ebsit (???)`
24			`*/`
25			`__stext:`
26			`__entry:`
27			`teq r0, #0 @ check for illegal entry...`
28			`bne Lerror @ loop indefinitely`
29			`cmp r1, #2 @ Unknown machine architecture`
30			`bge Lerror`
31			`@`
32			`@ First thing to do is to get the page tables set up so that we can call the kernel`
33			`@ in the correct place. This is relocatable code...`
34			`@`
35			`mrc p15, 0, r9, c0, c0 @ get Processor ID`
36			`@`
37			`@ Read processor ID register (CP#15, CR0).`
38			`@ NOTE: ARM2 & ARM250 cause an undefined instruction exception...`
39			`@ Values are:`
40			`@ XX01XXXX = ARMv4 architecture (StrongARM)`
41			`@ XX00XXXX = ARMv3 architecture`
42			`@ 4156061X = ARM 610`
43			`@ 4156030X = ARM 3`
44			`@ 4156025X = ARM 250`
45			`@ 4156020X = ARM 2`
46			`@`
47			`adr r10, LCProcTypes`
48			`1: ldmia r10!, {r5, r6, r8} @ Get Set, Mask, MMU Flags`
49			`teq r5, #0 @ End of list?`
50			`beq Lerror`
51			`eor r5, r5, r9`
52			`tst r5, r6`
53			`addne r10, r10, #8`
54			`bne 1b`
55
56			`adr r4, LCMachTypes`
57			`add r4, r4, r1, lsl #4`
58			`ldmia r4, {r4, r5, r6} @ r4 = page dir in physical ram`
59
60			`mov r0, r4`
61			`mov r1, #0`
62			`add r2, r0, #0x4000`
63			`1: str r1, [r0], #4 @ Clear page table`
64			`teq r0, r2`
65			`bne 1b`
66			`@`
67			`@ Add enough entries to allow the kernel to be called.`
68			`@ It will sort out the real mapping in paging_init`
69			`@`
70			`add r0, r4, #0x3000`
71			`mov r1, #0x0000000c @ SECT_CACHEABLE \| SECT_BUFFERABLE`
72			`orr r1, r1, r8`
73			`add r1, r1, r5`
74			`str r1, [r0], #4`
75			`add r1, r1, #1 << 20`
76			`str r1, [r0], #4`
77			`add r1, r1, #1 << 20`
78			`@`
79			`@ Map in IO space`
80			`@`
81			`add r0, r4, #0x3800`
82			`orr r1, r6, r8`
83			`add r2, r0, #0x0800`
84			`1: str r1, [r0], #4`
85			`add r1, r1, #1 << 20`
86			`teq r0, r2`
87			`bne 1b`
88			`@`
89			`@ Map in screen at 0x02000000 & SCREEN2_BASE`
90			`@`
91			`teq r5, #0`
92			`addne r0, r4, #0x80 @ 02000000`
93			`movne r1, #0x02000000`
94			`orrne r1, r1, r8`
95			`strne r1, [r0]`
96			`addne r0, r4, #0x3600 @ d8000000`
97			`strne r1, [r0]`
98			`@`
99			`@ The following should work on both v3 and v4 implementations`
100			`@`
101			`mov lr, pc`
102			`mov pc, r10 @ Call processor flush (returns ctrl reg)`
103			`adr r5, __entry`
104			`sub r10, r10, r5 @ Make r10 PIC`
105
106			`ldr lr, Lbranch`
107			`mcr p15, 0, r0, c1, c0 @ Enable MMU & caches. In 3 instructions`
108			`@ we loose this page!`
109			`mov pc, lr`
110
111			`Lerror: mov r0, #0x02000000`
112			`mov r1, #0x11`
113			`orr r1, r1, r1, lsl #8`
114			`orr r1, r1, r1, lsl #16`
115			`str r1, [r0], #4`
116			`str r1, [r0], #4`
117			`str r1, [r0], #4`
118			`str r1, [r0], #4`
119			`b Lerror`
120
121			`Lbranch: .long Lalready_done_mmap @ Real address of routine`
122
123			`@ EBSA (pg dir phys, phys ram start, phys i/o)`
124			`LCMachTypes: .long _swapper_pg_dir - 0xc0000000 @ Address of page tables (physical)`
125			`.long 0 @ Address of RAM`
126			`.long 0xe0000000 @ I/O address`
127			`.long 0`
128
129			`@ RPC`
130			`.long _swapper_pg_dir - 0xc0000000 + 0x10000000`
131			`.long 0x10000000`
132			`.long 0x03000000`
133			`.long 0`
134
135			`@ EBSIT ???`
136			`.long _swapper_pg_dir - 0xc0000000`
137			`.long 0`
138			`.long 0xe0000000`
139			`.long 0`
140
141			`LCProcTypes: @ ARM6 / 610`
142			`.long 0x41560600`
143			`.long 0xffffff00`
144			`.long 0x00000c12`
145			`b Larmv3_flush_early @ arm v3 flush & ctrl early setup`
146			`mov pc, lr`
147
148			`@ ARM7`
149			`.long 0x41007000`
150			`.long 0xfffff000`
151			`.long 0x00000c12`
152			`b Larmv3_flush_late @ arm v3 flush & ctrl late setup`
153			`mov pc, lr`
154
155			`@ ARM710`
156			`.long 0x41007000`
157			`.long 0xfff8f000 @ ARM710 does not follow spec`
158			`.long 0x00000c12`
159			`b Larmv3_flush_late @ arm v3 flush & ctrl late setup`
160			`mov pc, lr`
161
162			`@ StrongARM`
163			`.long 0x4401a100`
164			`.long 0xfffffff0`
165			`.long 0x00000c02`
166			`b Larmv4_flush_early`
167			`b Lsa_fastclock`
168
169			`.long 0`
170
171			`LC0: .long _edata`
172			`.long _arm_id`
173			`.long _end`
174			`.long _init_user_stack + 4096`
175			`.align`
176
177			`Larmv3_flush_early:`
178			`mov r0, #0`
179			`mcr p15, 0, r0, c7, c0 @ flush caches on v3`
180			`mcr p15, 0, r0, c5, c0 @ flush TLBs on v3`
181			`mcr p15, 0, r4, c2, c0 @ load page table pointer`
182			`mov r0, #5 @ Domains 0, 1 = client`
183			`mcr p15, 0, r0, c3, c0 @ load domain access register`
184			`mov r0, #0x3d @ ....DPWCAM`
185			`mov pc, lr`
186
187			`Larmv3_flush_late:`
188			`mov r0, #0`
189			`mcr p15, 0, r0, c7, c0 @ flush caches on v3`
190			`mcr p15, 0, r0, c5, c0 @ flush TLBs on v3`
191			`mcr p15, 0, r4, c2, c0 @ load page table pointer`
192			`mov r0, #5 @ Domains 0, 1 = client`
193			`mcr p15, 0, r0, c3, c0 @ load domain access register`
194			`mov r0, #0x7d @ ...LDPWCAM`
195			`mov pc, lr`
196
197			`Larmv4_flush_early:`
198			`mov r0, #0`
199			`mcr p15, 0, r0, c7, c7 @ flush I,D caches on v4`
200			`mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4`
201			`mcr p15, 0, r0, c8, c7 @ flush I,D TLBs on v4`
202			`mcr p15, 0, r4, c2, c0 @ load page table pointer`
203			`mov r0, #5 @ Domains 0, 1 = client`
204			`mcr p15, 0, r0, c3, c0 @ load domain access register`
205			`mrc p15, 0, r0, c1, c0 @ get control register v4`
206			`orr r0, r0, #0x3d @ I......DPWCAM`
207			`orr r0, r0, #1 << 12 @ v4 supports separate I cache`
208			`mov pc, lr`
209
210			`Lsa_fastclock: mcr p15, 0, r4, c15, c1, 2 @ Enable clock switching`
211			`mov pc, lr`
212
213			`Lalready_done_mmap:`
214			`adr r5, __entry @ Add base back in`
215			`add r10, r10, r5`
216
217			`adr r5, LC0`
218			`ldmia r5, {r5, r6, r8, sp} @ Setup stack`
219			`mov r4, #0`
220			`1: cmp r5, r8 @ Clear BSS`
221			`strcc r4, [r5],#4`
222			`bcc 1b`
223
224			`str r9, [r6] @ Save processor ID`
225			`mov lr, pc`
226			`add pc, r10, #4 @ Call post-processor init`
227
228			`mov fp, #0`
229			`b _start_kernel`
230
231			`#if 1`
232			`/*`
233			`* Useful debugging routines`
234			`*/`
235			`.globl _printhex8`
236			`_printhex8: mov r1, #8`
237			`b printhex`
238
239			`.globl _printhex4`
240			`_printhex4: mov r1, #4`
241			`b printhex`
242
243			`.globl _printhex2`
244			`_printhex2: mov r1, #2`
245			`printhex: ldr r2, =hexbuf`
246			`add r3, r2, r1`
247			`mov r1, #0`
248			`strb r1, [r3]`
249			`1: and r1, r0, #15`
250			`mov r0, r0, lsr #4`
251			`cmp r1, #10`
252			`addlt r1, r1, #'0'`
253			`addge r1, r1, #'a' - 10`
254			`strb r1, [r3, #-1]!`
255			`teq r3, r2`
256			`bne 1b`
257			`mov r0, r2`
258
259			`.globl _printascii`
260			`_printascii:`
261			`#ifdef CONFIG_ARCH_RPC`
262			`mov r3, #0xe0000000`
263			`orr r3, r3, #0x00010000`
264			`orr r3, r3, #0x00000fe0`
265			`#else`
266			`mov r3, #0xf0000000`
267			`orr r3, r3, #0x0be0`
268			`#endif`
269			`b 3f`
270			`1: ldrb r2, [r3, #0x18]`
271			`tst r2, #0x10`
272			`beq 1b`
273			`strb r1, [r3]`
274			`2: ldrb r2, [r3, #0x14]`
275			`and r2, r2, #0x60`
276			`teq r2, #0x60`
277			`bne 2b`
278			`teq r1, #'\n'`
279			`moveq r1, #'\r'`
280			`beq 1b`
281			`3: teq r0, #0`
282			`ldrneb r1, [r0], #1`
283			`teqne r1, #0`
284			`bne 1b`
285			`mov pc, lr`
286
287			`.globl _printch`
288			`_printch:`
289			`#ifdef CONFIG_ARCH_RPC`
290			`mov r3, #0xe0000000`
291			`orr r3, r3, #0x00010000`
292			`orr r3, r3, #0x00000fe0`
293			`#else`
294			`mov r3, #0xf0000000`
295			`orr r3, r3, #0x0be0`
296			`#endif`
297			`mov r1, r0`
298			`mov r0, #0`
299			`b 1b`
300
301			`.bss`
302			`hexbuf: .space 16`
303
304			`#endif`
305