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/*
 * linux/arch/arm/mm/arm6.S: MMU functions for ARM6
 *
 * (C) 1997 Russell King
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the ARM6 & ARM7.
 */
 
#include 
#include "../lib/constants.h"
#define current current_set
 
/*
 * Function: arm6_7_flush_cache_all (void)
 *         : arm6_7_flush_cache_page (unsigned long address, int size, int flags)
 *
 * Params  : address    Area start address
 *         : size       size of area
 *         : flags      b0 = I cache as well
 *
 * Purpose : Flush all cache lines
 */
arm6_7_flush_cache:
                mov     r0, #0
#ifndef NO_MM
                mcr     p15, 0, r0, c7, c0, 0           @ flush cache
#endif
arm6_7_null:
                mov     pc, lr
 
/*
 * Function: arm6_7_flush_tlb_all (void)
 *
 * Purpose : flush all TLB entries in all caches
 */
arm6_7_flush_tlb_all:
                mov     r0, #0
#ifndef NO_MM
                mcr     p15, 0, r0, c5, c0, 0           @ flush TLB
#endif
                mov     pc, lr
 
/*
 * Function: arm6_7_flush_tlb_page (unsigned long address, int end, int flags)
 *
 * Params  : address    Area start address
 *         : end        Area end address
 *         : flags      b0 = I cache as well
 *
 * Purpose : flush a TLB entry
*/
arm6_7_flush_tlb_area:
#ifndef NO_MM
1:              mcr     p15, 0, r0, c6, c0, 0           @ flush TLB
                add     r0, r0, #4096
                cmp     r0, r1
                blt     1b
#endif
                mov     pc, lr
 
LC0:            .word   current
 
 
/*
 * Function: arm6_7_switch_to (struct task_struct *prev, struct task_struct *next)
 *
 * Params  : prev       Old task structure
 *         : next       New task structure for process to run
 *
 * Purpose : Perform a task switch, saving the old processes state, and restoring
 *           the new.
 *
 * Notes   : We don't fiddle with the FP registers here - we postpone this until
 *           the new task actually uses FP.  This way, we don't swap FP for tasks
 *           that do not require it.
 */
arm6_7_switch_to:
                stmfd   sp!, {r4 - r10, fp, lr}         @ Store most regs on stack
                mrs     ip, cpsr
                stmfd   sp!, {ip}                       @ Save cpsr_SVC
                str     sp, [r0, #TSS_SAVE]             @ Save sp_SVC
                ldr     r2, LC0
                str     r1, [r2]
                ldr     sp, [r1, #TSS_SAVE]             @ Get saved sp_SVC
#ifndef NO_MM
                ldr     r0, [r1, #TSS_MEMMAP]           @ Page table pointer
                mov     r1, #0
                mcr     p15, 0, r1, c7, c0, 0           @ flush cache
                mcr     p15, 0, r0, c2, c0, 0           @ update page table ptr
                mcr     p15, 0, r1, c5, c0, 0           @ flush TLBs
#endif
                ldmfd   sp!, {ip}
                msr     spsr, ip                        @ Save tasks CPSR into SPSR for this return
                ldmfd   sp!, {r4 - r10, fp, pc}^                @ Load all regs saved previously
 
/*
 * Function: arm6_7_data_abort ()
 *
 * Params  : r0 = address of aborted instruction
 *
 * Purpose : obtain information about current aborted instruction
 *
 * Returns : r0 = address of abort
 *         : r1 = FSR
 *         : r2 != 0 if writing
 *         : sp = pointer to registers
 *
 * Notes   : data abort *** NEEDS WORK ***
 */
 
Lukabttxt:      .ascii  "Unknown data abort code %d [pc=%p, *pc=%p] LR=%p\0"
                .align
 
msg:            .ascii  "DA*%p=%p\n\0"
                .align
 
arm6_data_abort:
                ldr     r4, [r0]                        @ read instruction causing problem
                mov     r2, r4, lsr #19                 @ r2 b1 = L
                and     r1, r4, #15 << 24
                add     pc, pc, r1, lsr #22             @ Now branch to the relevent processing routine
                movs    pc, lr
                b       Ldata_unknown
                b       Ldata_unknown
                b       Ldata_unknown
                b       Ldata_unknown
                b       Ldata_earlyldrpost              @ ldr   rd, [rn], #m
                b       Ldata_simple                    @ ldr   rd, [rn, #m]    @ RegVal
                b       Ldata_earlyldrpost              @ ldr   rd, [rn], rm
                b       Ldata_simple                    @ ldr   rd, [rn, rm]
                b       Ldata_ldmstm                    @ ldm*a rn, 
                b       Ldata_ldmstm                    @ ldm*b rn, 
                b       Ldata_unknown
                b       Ldata_unknown
                b       Ldata_simple                    @ ldc   rd, [rn], #m    @ Same as ldr   rd, [rn], #m
                b       Ldata_simple                    @ ldc   rd, [rn, #m]
                b       Ldata_unknown
Ldata_unknown:  @ Part of jumptable
                ldr     r3, [sp, #15 * 4]               @ Get PC
                str     r3, [sp, #-4]!
                mov     r1, r1, lsr #2
                mov     r3, r4
                mov     r2, r0
                adr     r0, Lukabttxt
                bl      panic
Lstop:          b       Lstop
 
arm7_data_abort:
                ldr     r4, [r0]                        @ read instruction causing problem
                mov     r2, r4, lsr #19                 @ r2 b1 = L
                and     r1, r4, #15 << 24
                add     pc, pc, r1, lsr #22             @ Now branch to the relevent processing routine
                movs    pc, lr
                b       Ldata_unknown
                b       Ldata_unknown
                b       Ldata_unknown
                b       Ldata_unknown
                b       Ldata_lateldrpostconst          @ ldr   rd, [rn], #m
                b       Ldata_lateldrpreconst           @ ldr   rd, [rn, #m]    @ RegVal
                b       Ldata_lateldrpostreg            @ ldr   rd, [rn], rm
                b       Ldata_lateldrprereg             @ ldr   rd, [rn, rm]
                b       Ldata_ldmstm                    @ ldm*a rn, 
                b       Ldata_ldmstm                    @ ldm*b rn, 
                b       Ldata_unknown
                b       Ldata_unknown
                b       Ldata_simple                    @ ldc   rd, [rn], #m    @ Same as ldr   rd, [rn], #m
                b       Ldata_simple                    @ ldc   rd, [rn, #m]
                b       Ldata_unknown
                b       Ldata_unknown
 
Ldata_ldmstm:   tst     r4, #1 << 21                    @ check writeback bit
                beq     Ldata_simple
 
                mov     r7, #0x11
                orr     r7, r7, r7, lsl #8
                and     r0, r4, r7
                and     r1, r4, r7, lsl #1
                add     r0, r0, r1, lsr #1
                and     r1, r4, r7, lsl #2
                add     r0, r0, r1, lsr #2
                and     r1, r4, r7, lsl #3
                add     r0, r0, r1, lsr #3
                add     r0, r0, r0, lsr #8
                add     r0, r0, r0, lsr #4
                and     r7, r0, #15                     @ r7 = no. of registers to transfer.
                and     r5, r4, #15 << 16               @ Get Rn
                ldr     r0, [sp, r5, lsr #14]           @ Get register
                eor     r6, r4, r4, lsl #2
                tst     r6, #1 << 23                    @ Check inc/dec ^ writeback
                rsbeq   r7, r7, #0
                add     r7, r0, r7, lsl #2              @ Do correction (signed)
                str     r7, [sp, r5, lsr #14]           @ Put register
 
Ldata_simple:   and     r2, r2, #2                      @ check read/write bit
                mrc     p15, 0, r0, c6, c0, 0           @ get FAR
                mrc     p15, 0, r1, c5, c0, 0           @ get FSR
                and     r1, r1, #15
                mov     pc, lr
 
Ldata_earlyldrpost:
                tst     r2, #4
                and     r2, r2, #2                      @ check read/write bit
                orrne   r2, r2, #1                      @ T bit
                mrc     p15, 0, r0, c6, c0, 0           @ get FAR
                mrc     p15, 0, r1, c5, c0, 0           @ get FSR
                and     r1, r1, #15
                mov     pc, lr
 
Ldata_lateldrpostconst:
                movs    r1, r4, lsl #20                 @ Get offset
                beq     Ldata_earlyldrpost              @ if offset is zero, no effect
                and     r5, r4, #15 << 16               @ Get Rn
                ldr     r0, [sp, r5, lsr #14]
                tst     r4, #1 << 23                    @ U bit
                subne   r0, r0, r1, lsr #20
                addeq   r0, r0, r1, lsr #20
                str     r0, [sp, r5, lsr #14]           @ Put register
                b       Ldata_earlyldrpost
 
Ldata_lateldrpreconst:
                tst     r4, #1 << 21                    @ check writeback bit
                movnes  r1, r4, lsl #20                 @ Get offset
                beq     Ldata_simple
                and     r5, r4, #15 << 16               @ Get Rn
                ldr     r0, [sp, r5, lsr #14]
                tst     r4, #1 << 23                    @ U bit
                subne   r0, r0, r1, lsr #20
                addeq   r0, r0, r1, lsr #20
                str     r0, [sp, r5, lsr #14]           @ Put register
                b       Ldata_simple
 
Ldata_lateldrpostreg:
                and     r5, r4, #15
                ldr     r1, [sp, r5, lsl #2]            @ Get Rm
                mov     r3, r4, lsr #7
                ands    r3, r3, #31
                and     r6, r4, #0x70
                orreq   r6, r6, #8
                add     pc, pc, r6
                mov     r0, r0
 
                mov     r1, r1, lsl r3                  @ 0: LSL #!0
                b       1f
                b       1f                              @ 1: LSL #0
                mov     r0, r0
                b       1f                              @ 2: MUL?
                mov     r0, r0
                b       1f                              @ 3: MUL?
                mov     r0, r0
                mov     r1, r1, lsr r3                  @ 4: LSR #!0
                b       1f
                mov     r1, r1, lsr #32                 @ 5: LSR #32
                b       1f
                b       1f                              @ 6: MUL?
                mov     r0, r0
                b       1f                              @ 7: MUL?
                mov     r0, r0
                mov     r1, r1, asr r3                  @ 8: ASR #!0
                b       1f
                mov     r1, r1, asr #32                 @ 9: ASR #32
                b       1f
                b       1f                              @ A: MUL?
                mov     r0, r0
                b       1f                              @ B: MUL?
                mov     r0, r0
                mov     r1, r1, ror r3                  @ C: ROR #!0
                b       1f
                mov     r1, r1, rrx                     @ D: RRX
                b       1f
                mov     r0, r0                          @ E: MUL?
                mov     r0, r0
                mov     r0, r0                          @ F: MUL?
 
 
1:              and     r5, r4, #15 << 16               @ Get Rn
                ldr     r0, [sp, r5, lsr #14]
                tst     r4, #1 << 23                    @ U bit
                subne   r0, r0, r1
                addeq   r0, r0, r1
                str     r0, [sp, r5, lsr #14]           @ Put register
                b       Ldata_earlyldrpost
 
Ldata_lateldrprereg:
                tst     r4, #1 << 21                    @ check writeback bit
                beq     Ldata_simple
                and     r5, r4, #15
                ldr     r1, [sp, r5, lsl #2]            @ Get Rm
                mov     r3, r4, lsr #7
                ands    r3, r3, #31
                and     r6, r4, #0x70
                orreq   r6, r6, #8
                add     pc, pc, r6
                mov     r0, r0
 
                mov     r1, r1, lsl r3                  @ 0: LSL #!0
                b       1f
                b       1f                              @ 1: LSL #0
                mov     r0, r0
                b       1f                              @ 2: MUL?
                mov     r0, r0
                b       1f                              @ 3: MUL?
                mov     r0, r0
                mov     r1, r1, lsr r3                  @ 4: LSR #!0
                b       1f
                mov     r1, r1, lsr #32                 @ 5: LSR #32
                b       1f
                b       1f                              @ 6: MUL?
                mov     r0, r0
                b       1f                              @ 7: MUL?
                mov     r0, r0
                mov     r1, r1, asr r3                  @ 8: ASR #!0
                b       1f
                mov     r1, r1, asr #32                 @ 9: ASR #32
                b       1f
                b       1f                              @ A: MUL?
                mov     r0, r0
                b       1f                              @ B: MUL?
                mov     r0, r0
                mov     r1, r1, ror r3                  @ C: ROR #!0
                b       1f
                mov     r1, r1, rrx                     @ D: RRX
                b       1f
                mov     r0, r0                          @ E: MUL?
                mov     r0, r0
                mov     r0, r0                          @ F: MUL?
 
 
1:              and     r5, r4, #15 << 16               @ Get Rn
                ldr     r0, [sp, r5, lsr #14]
                tst     r4, #1 << 23                    @ U bit
                subne   r0, r0, r1
                addeq   r0, r0, r1
                str     r0, [sp, r5, lsr #14]           @ Put register
                b       Ldata_simple
 
/*
 * Function: arm6_7_check_bugs (void)
 *         : arm6_7_proc_init (void)
 *         : arm6_7_proc_fin (void)
 *
 * Notes   : This processor does not require these
 */
arm6_7_check_bugs:
                mrs     ip, cpsr
                bic     ip, ip, #F_BIT
                msr     cpsr, ip
arm6_7_proc_init:
arm6_7_proc_fin:
                mov     pc, lr
 
/*
 * Function: arm6_set_pmd ()
 *
 * Params  : r0 = Address to set
 *         : r1 = value to set
 *
 * Purpose : Set a PMD and flush it out of any WB cache
 */
arm6_set_pmd:   and     r2, r1, #3
                teq     r2, #2
                andeq   r2, r1, #8
                orreq   r1, r1, r2, lsl #1              @ Updatable = Cachable
                teq     r2, #1
                orreq   r1, r1, #16                     @ Updatable = 1 if Page table
                str     r1, [r0]
                mov     pc, lr
 
/*
 * Function: arm7_set_pmd ()
 *
 * Params  : r0 = Address to set
 *         : r1 = value to set
 *
 * Purpose : Set a PMD and flush it out of any WB cache
 */
arm7_set_pmd:
#ifndef NO_MM
        orr     r1, r1, #16                     @ Updatable bit is always set on ARM7
                str     r1, [r0]
#endif
                mov     pc, lr
 
/*
 * Function: arm6_7_reset
 *
 * Notes   : This sets up everything for a reset
 */
arm6_7_reset:   mrs     r1, cpsr
                orr     r1, r1, #F_BIT|I_BIT
                msr     cpsr, r1
                mov     r0, #0
#ifndef NO_MM
                mcr     p15, 0, r0, c7, c0, 0           @ flush cache
                mcr     p15, 0, r0, c5, c0, 0           @ flush TLB
#endif
                mov     r1, #F_BIT | I_BIT | 3
                mov     pc, lr
 
/*
 * Purpose : Function pointers used to access above functions - all calls
 *           come through these
 */
arm6_name:      .ascii  "arm6\0"
                .align
 
                .globl  arm6_processor_functions
arm6_processor_functions:
                .word   arm6_name                       @  0
                .word   arm6_7_switch_to                @  4
                .word   arm6_data_abort         @  8
                .word   arm6_7_check_bugs               @ 12
                .word   arm6_7_proc_init                @ 16
                .word   arm6_7_proc_fin         @ 20
 
                .word   arm6_7_flush_cache              @ 24
                .word   arm6_7_flush_cache              @ 28
                .word   arm6_7_flush_cache              @ 32
                .word   arm6_7_null                     @ 36
                .word   arm6_7_flush_cache              @ 40
                .word   arm6_7_flush_tlb_all            @ 44
                .word   arm6_7_flush_tlb_area           @ 48
                .word   arm6_set_pmd                    @ 52
                .word   arm6_7_reset                    @ 54
 
/*
 * Purpose : Function pointers used to access above functions - all calls
 *           come through these
 */
arm7_name:      .ascii  "arm7\0"
                .align
 
                .globl  arm7_processor_functions
arm7_processor_functions:
                .word   arm7_name                       @  0
                .word   arm6_7_switch_to                @  4
                .word   arm7_data_abort         @  8
                .word   arm6_7_check_bugs               @ 12
                .word   arm6_7_proc_init                @ 16
                .word   arm6_7_proc_fin         @ 20
                .word   arm6_7_flush_cache              @ 24
                .word   arm6_7_flush_cache              @ 28
                .word   arm6_7_flush_cache              @ 32
                .word   arm6_7_null                     @ 36
                .word   arm6_7_flush_cache              @ 40
                .word   arm6_7_flush_tlb_all            @ 44
                .word   arm6_7_flush_tlb_area           @ 48
                .word   arm7_set_pmd                    @ 52
                .word   arm6_7_reset                    @ 54

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[/] [or1k/] [trunk/] [uclinux/] [uClinux-2.0.x/] [arch/] [armnommu/] [mm/] [proc-arm6,7.S] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	199	simons	`/*`
2			`* linux/arch/arm/mm/arm6.S: MMU functions for ARM6`
3			`*`
4			`* (C) 1997 Russell King`
5			`*`
6			`* These are the low level assembler for performing cache and TLB`
7			`* functions on the ARM6 & ARM7.`
8			`*/`
9
10			`#include`
11			`#include "../lib/constants.h"`
12			`#define current current_set`
13
14			`/*`
15			`* Function: arm6_7_flush_cache_all (void)`
16			`* : arm6_7_flush_cache_page (unsigned long address, int size, int flags)`
17			`*`
18			`* Params : address Area start address`
19			`* : size size of area`
20			`* : flags b0 = I cache as well`
21			`*`
22			`* Purpose : Flush all cache lines`
23			`*/`
24			`arm6_7_flush_cache:`
25			`mov r0, #0`
26			`#ifndef NO_MM`
27			`mcr p15, 0, r0, c7, c0, 0 @ flush cache`
28			`#endif`
29			`arm6_7_null:`
30			`mov pc, lr`
31
32			`/*`
33			`* Function: arm6_7_flush_tlb_all (void)`
34			`*`
35			`* Purpose : flush all TLB entries in all caches`
36			`*/`
37			`arm6_7_flush_tlb_all:`
38			`mov r0, #0`
39			`#ifndef NO_MM`
40			`mcr p15, 0, r0, c5, c0, 0 @ flush TLB`
41			`#endif`
42			`mov pc, lr`
43
44			`/*`
45			`* Function: arm6_7_flush_tlb_page (unsigned long address, int end, int flags)`
46			`*`
47			`* Params : address Area start address`
48			`* : end Area end address`
49			`* : flags b0 = I cache as well`
50			`*`
51			`* Purpose : flush a TLB entry`
52			`*/`
53			`arm6_7_flush_tlb_area:`
54			`#ifndef NO_MM`
55			`1: mcr p15, 0, r0, c6, c0, 0 @ flush TLB`
56			`add r0, r0, #4096`
57			`cmp r0, r1`
58			`blt 1b`
59			`#endif`
60			`mov pc, lr`
61
62			`LC0: .word current`
63
64
65			`/*`
66			`* Function: arm6_7_switch_to (struct task_struct prev, struct task_struct next)`
67			`*`
68			`* Params : prev Old task structure`
69			`* : next New task structure for process to run`
70			`*`
71			`* Purpose : Perform a task switch, saving the old processes state, and restoring`
72			`* the new.`
73			`*`
74			`* Notes : We don't fiddle with the FP registers here - we postpone this until`
75			`* the new task actually uses FP. This way, we don't swap FP for tasks`
76			`* that do not require it.`
77			`*/`
78			`arm6_7_switch_to:`
79			`stmfd sp!, {r4 - r10, fp, lr} @ Store most regs on stack`
80			`mrs ip, cpsr`
81			`stmfd sp!, {ip} @ Save cpsr_SVC`
82			`str sp, [r0, #TSS_SAVE] @ Save sp_SVC`
83			`ldr r2, LC0`
84			`str r1, [r2]`
85			`ldr sp, [r1, #TSS_SAVE] @ Get saved sp_SVC`
86			`#ifndef NO_MM`
87			`ldr r0, [r1, #TSS_MEMMAP] @ Page table pointer`
88			`mov r1, #0`
89			`mcr p15, 0, r1, c7, c0, 0 @ flush cache`
90			`mcr p15, 0, r0, c2, c0, 0 @ update page table ptr`
91			`mcr p15, 0, r1, c5, c0, 0 @ flush TLBs`
92			`#endif`
93			`ldmfd sp!, {ip}`
94			`msr spsr, ip @ Save tasks CPSR into SPSR for this return`
95			`ldmfd sp!, {r4 - r10, fp, pc}^ @ Load all regs saved previously`
96
97			`/*`
98			`* Function: arm6_7_data_abort ()`
99			`*`
100			`* Params : r0 = address of aborted instruction`
101			`*`
102			`* Purpose : obtain information about current aborted instruction`
103			`*`
104			`* Returns : r0 = address of abort`
105			`* : r1 = FSR`
106			`* : r2 != 0 if writing`
107			`* : sp = pointer to registers`
108			`*`
109			`* Notes : data abort * NEEDS WORK *`
110			`*/`
111
112			`Lukabttxt: .ascii "Unknown data abort code %d [pc=%p, *pc=%p] LR=%p\0"`
113			`.align`
114
115			`msg: .ascii "DA*%p=%p\n\0"`
116			`.align`
117
118			`arm6_data_abort:`
119			`ldr r4, [r0] @ read instruction causing problem`
120			`mov r2, r4, lsr #19 @ r2 b1 = L`
121			`and r1, r4, #15 << 24`
122			`add pc, pc, r1, lsr #22 @ Now branch to the relevent processing routine`
123			`movs pc, lr`
124			`b Ldata_unknown`
125			`b Ldata_unknown`
126			`b Ldata_unknown`
127			`b Ldata_unknown`
128			`b Ldata_earlyldrpost @ ldr rd, [rn], #m`
129			`b Ldata_simple @ ldr rd, [rn, #m] @ RegVal`
130			`b Ldata_earlyldrpost @ ldr rd, [rn], rm`
131			`b Ldata_simple @ ldr rd, [rn, rm]`
132			`b Ldata_ldmstm @ ldm*a rn,`
133			`b Ldata_ldmstm @ ldm*b rn,`
134			`b Ldata_unknown`
135			`b Ldata_unknown`
136			`b Ldata_simple @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m`
137			`b Ldata_simple @ ldc rd, [rn, #m]`
138			`b Ldata_unknown`
139			`Ldata_unknown: @ Part of jumptable`
140			`ldr r3, [sp, #15 * 4] @ Get PC`
141			`str r3, [sp, #-4]!`
142			`mov r1, r1, lsr #2`
143			`mov r3, r4`
144			`mov r2, r0`
145			`adr r0, Lukabttxt`
146			`bl panic`
147			`Lstop: b Lstop`
148
149			`arm7_data_abort:`
150			`ldr r4, [r0] @ read instruction causing problem`
151			`mov r2, r4, lsr #19 @ r2 b1 = L`
152			`and r1, r4, #15 << 24`
153			`add pc, pc, r1, lsr #22 @ Now branch to the relevent processing routine`
154			`movs pc, lr`
155			`b Ldata_unknown`
156			`b Ldata_unknown`
157			`b Ldata_unknown`
158			`b Ldata_unknown`
159			`b Ldata_lateldrpostconst @ ldr rd, [rn], #m`
160			`b Ldata_lateldrpreconst @ ldr rd, [rn, #m] @ RegVal`
161			`b Ldata_lateldrpostreg @ ldr rd, [rn], rm`
162			`b Ldata_lateldrprereg @ ldr rd, [rn, rm]`
163			`b Ldata_ldmstm @ ldm*a rn,`
164			`b Ldata_ldmstm @ ldm*b rn,`
165			`b Ldata_unknown`
166			`b Ldata_unknown`
167			`b Ldata_simple @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m`
168			`b Ldata_simple @ ldc rd, [rn, #m]`
169			`b Ldata_unknown`
170			`b Ldata_unknown`
171
172			`Ldata_ldmstm: tst r4, #1 << 21 @ check writeback bit`
173			`beq Ldata_simple`
174
175			`mov r7, #0x11`
176			`orr r7, r7, r7, lsl #8`
177			`and r0, r4, r7`
178			`and r1, r4, r7, lsl #1`
179			`add r0, r0, r1, lsr #1`
180			`and r1, r4, r7, lsl #2`
181			`add r0, r0, r1, lsr #2`
182			`and r1, r4, r7, lsl #3`
183			`add r0, r0, r1, lsr #3`
184			`add r0, r0, r0, lsr #8`
185			`add r0, r0, r0, lsr #4`
186			`and r7, r0, #15 @ r7 = no. of registers to transfer.`
187			`and r5, r4, #15 << 16 @ Get Rn`
188			`ldr r0, [sp, r5, lsr #14] @ Get register`
189			`eor r6, r4, r4, lsl #2`
190			`tst r6, #1 << 23 @ Check inc/dec ^ writeback`
191			`rsbeq r7, r7, #0`
192			`add r7, r0, r7, lsl #2 @ Do correction (signed)`
193			`str r7, [sp, r5, lsr #14] @ Put register`
194
195			`Ldata_simple: and r2, r2, #2 @ check read/write bit`
196			`mrc p15, 0, r0, c6, c0, 0 @ get FAR`
197			`mrc p15, 0, r1, c5, c0, 0 @ get FSR`
198			`and r1, r1, #15`
199			`mov pc, lr`
200
201			`Ldata_earlyldrpost:`
202			`tst r2, #4`
203			`and r2, r2, #2 @ check read/write bit`
204			`orrne r2, r2, #1 @ T bit`
205			`mrc p15, 0, r0, c6, c0, 0 @ get FAR`
206			`mrc p15, 0, r1, c5, c0, 0 @ get FSR`
207			`and r1, r1, #15`
208			`mov pc, lr`
209
210			`Ldata_lateldrpostconst:`
211			`movs r1, r4, lsl #20 @ Get offset`
212			`beq Ldata_earlyldrpost @ if offset is zero, no effect`
213			`and r5, r4, #15 << 16 @ Get Rn`
214			`ldr r0, [sp, r5, lsr #14]`
215			`tst r4, #1 << 23 @ U bit`
216			`subne r0, r0, r1, lsr #20`
217			`addeq r0, r0, r1, lsr #20`
218			`str r0, [sp, r5, lsr #14] @ Put register`
219			`b Ldata_earlyldrpost`
220
221			`Ldata_lateldrpreconst:`
222			`tst r4, #1 << 21 @ check writeback bit`
223			`movnes r1, r4, lsl #20 @ Get offset`
224			`beq Ldata_simple`
225			`and r5, r4, #15 << 16 @ Get Rn`
226			`ldr r0, [sp, r5, lsr #14]`
227			`tst r4, #1 << 23 @ U bit`
228			`subne r0, r0, r1, lsr #20`
229			`addeq r0, r0, r1, lsr #20`
230			`str r0, [sp, r5, lsr #14] @ Put register`
231			`b Ldata_simple`
232
233			`Ldata_lateldrpostreg:`
234			`and r5, r4, #15`
235			`ldr r1, [sp, r5, lsl #2] @ Get Rm`
236			`mov r3, r4, lsr #7`
237			`ands r3, r3, #31`
238			`and r6, r4, #0x70`
239			`orreq r6, r6, #8`
240			`add pc, pc, r6`
241			`mov r0, r0`
242
243			`mov r1, r1, lsl r3 @ 0: LSL #!0`
244			`b 1f`
245			`b 1f @ 1: LSL #0`
246			`mov r0, r0`
247			`b 1f @ 2: MUL?`
248			`mov r0, r0`
249			`b 1f @ 3: MUL?`
250			`mov r0, r0`
251			`mov r1, r1, lsr r3 @ 4: LSR #!0`
252			`b 1f`
253			`mov r1, r1, lsr #32 @ 5: LSR #32`
254			`b 1f`
255			`b 1f @ 6: MUL?`
256			`mov r0, r0`
257			`b 1f @ 7: MUL?`
258			`mov r0, r0`
259			`mov r1, r1, asr r3 @ 8: ASR #!0`
260			`b 1f`
261			`mov r1, r1, asr #32 @ 9: ASR #32`
262			`b 1f`
263			`b 1f @ A: MUL?`
264			`mov r0, r0`
265			`b 1f @ B: MUL?`
266			`mov r0, r0`
267			`mov r1, r1, ror r3 @ C: ROR #!0`
268			`b 1f`
269			`mov r1, r1, rrx @ D: RRX`
270			`b 1f`
271			`mov r0, r0 @ E: MUL?`
272			`mov r0, r0`
273			`mov r0, r0 @ F: MUL?`
274
275
276			`1: and r5, r4, #15 << 16 @ Get Rn`
277			`ldr r0, [sp, r5, lsr #14]`
278			`tst r4, #1 << 23 @ U bit`
279			`subne r0, r0, r1`
280			`addeq r0, r0, r1`
281			`str r0, [sp, r5, lsr #14] @ Put register`
282			`b Ldata_earlyldrpost`
283
284			`Ldata_lateldrprereg:`
285			`tst r4, #1 << 21 @ check writeback bit`
286			`beq Ldata_simple`
287			`and r5, r4, #15`
288			`ldr r1, [sp, r5, lsl #2] @ Get Rm`
289			`mov r3, r4, lsr #7`
290			`ands r3, r3, #31`
291			`and r6, r4, #0x70`
292			`orreq r6, r6, #8`
293			`add pc, pc, r6`
294			`mov r0, r0`
295
296			`mov r1, r1, lsl r3 @ 0: LSL #!0`
297			`b 1f`
298			`b 1f @ 1: LSL #0`
299			`mov r0, r0`
300			`b 1f @ 2: MUL?`
301			`mov r0, r0`
302			`b 1f @ 3: MUL?`
303			`mov r0, r0`
304			`mov r1, r1, lsr r3 @ 4: LSR #!0`
305			`b 1f`
306			`mov r1, r1, lsr #32 @ 5: LSR #32`
307			`b 1f`
308			`b 1f @ 6: MUL?`
309			`mov r0, r0`
310			`b 1f @ 7: MUL?`
311			`mov r0, r0`
312			`mov r1, r1, asr r3 @ 8: ASR #!0`
313			`b 1f`
314			`mov r1, r1, asr #32 @ 9: ASR #32`
315			`b 1f`
316			`b 1f @ A: MUL?`
317			`mov r0, r0`
318			`b 1f @ B: MUL?`
319			`mov r0, r0`
320			`mov r1, r1, ror r3 @ C: ROR #!0`
321			`b 1f`
322			`mov r1, r1, rrx @ D: RRX`
323			`b 1f`
324			`mov r0, r0 @ E: MUL?`
325			`mov r0, r0`
326			`mov r0, r0 @ F: MUL?`
327
328
329			`1: and r5, r4, #15 << 16 @ Get Rn`
330			`ldr r0, [sp, r5, lsr #14]`
331			`tst r4, #1 << 23 @ U bit`
332			`subne r0, r0, r1`
333			`addeq r0, r0, r1`
334			`str r0, [sp, r5, lsr #14] @ Put register`
335			`b Ldata_simple`
336
337			`/*`
338			`* Function: arm6_7_check_bugs (void)`
339			`* : arm6_7_proc_init (void)`
340			`* : arm6_7_proc_fin (void)`
341			`*`
342			`* Notes : This processor does not require these`
343			`*/`
344			`arm6_7_check_bugs:`
345			`mrs ip, cpsr`
346			`bic ip, ip, #F_BIT`
347			`msr cpsr, ip`
348			`arm6_7_proc_init:`
349			`arm6_7_proc_fin:`
350			`mov pc, lr`
351
352			`/*`
353			`* Function: arm6_set_pmd ()`
354			`*`
355			`* Params : r0 = Address to set`
356			`* : r1 = value to set`
357			`*`
358			`* Purpose : Set a PMD and flush it out of any WB cache`
359			`*/`
360			`arm6_set_pmd: and r2, r1, #3`
361			`teq r2, #2`
362			`andeq r2, r1, #8`
363			`orreq r1, r1, r2, lsl #1 @ Updatable = Cachable`
364			`teq r2, #1`
365			`orreq r1, r1, #16 @ Updatable = 1 if Page table`
366			`str r1, [r0]`
367			`mov pc, lr`
368
369			`/*`
370			`* Function: arm7_set_pmd ()`
371			`*`
372			`* Params : r0 = Address to set`
373			`* : r1 = value to set`
374			`*`
375			`* Purpose : Set a PMD and flush it out of any WB cache`
376			`*/`
377			`arm7_set_pmd:`
378			`#ifndef NO_MM`
379			`orr r1, r1, #16 @ Updatable bit is always set on ARM7`
380			`str r1, [r0]`
381			`#endif`
382			`mov pc, lr`
383
384			`/*`
385			`* Function: arm6_7_reset`
386			`*`
387			`* Notes : This sets up everything for a reset`
388			`*/`
389			`arm6_7_reset: mrs r1, cpsr`
390			`orr r1, r1, #F_BIT\|I_BIT`
391			`msr cpsr, r1`
392			`mov r0, #0`
393			`#ifndef NO_MM`
394			`mcr p15, 0, r0, c7, c0, 0 @ flush cache`
395			`mcr p15, 0, r0, c5, c0, 0 @ flush TLB`
396			`#endif`
397			`mov r1, #F_BIT \| I_BIT \| 3`
398			`mov pc, lr`
399
400			`/*`
401			`* Purpose : Function pointers used to access above functions - all calls`
402			`* come through these`
403			`*/`
404			`arm6_name: .ascii "arm6\0"`
405			`.align`
406
407			`.globl arm6_processor_functions`
408			`arm6_processor_functions:`
409			`.word arm6_name @ 0`
410			`.word arm6_7_switch_to @ 4`
411			`.word arm6_data_abort @ 8`
412			`.word arm6_7_check_bugs @ 12`
413			`.word arm6_7_proc_init @ 16`
414			`.word arm6_7_proc_fin @ 20`
415
416			`.word arm6_7_flush_cache @ 24`
417			`.word arm6_7_flush_cache @ 28`
418			`.word arm6_7_flush_cache @ 32`
419			`.word arm6_7_null @ 36`
420			`.word arm6_7_flush_cache @ 40`
421			`.word arm6_7_flush_tlb_all @ 44`
422			`.word arm6_7_flush_tlb_area @ 48`
423			`.word arm6_set_pmd @ 52`
424			`.word arm6_7_reset @ 54`
425
426			`/*`
427			`* Purpose : Function pointers used to access above functions - all calls`
428			`* come through these`
429			`*/`
430			`arm7_name: .ascii "arm7\0"`
431			`.align`
432
433			`.globl arm7_processor_functions`
434			`arm7_processor_functions:`
435			`.word arm7_name @ 0`
436			`.word arm6_7_switch_to @ 4`
437			`.word arm7_data_abort @ 8`
438			`.word arm6_7_check_bugs @ 12`
439			`.word arm6_7_proc_init @ 16`
440			`.word arm6_7_proc_fin @ 20`
441			`.word arm6_7_flush_cache @ 24`
442			`.word arm6_7_flush_cache @ 28`
443			`.word arm6_7_flush_cache @ 32`
444			`.word arm6_7_null @ 36`
445			`.word arm6_7_flush_cache @ 40`
446			`.word arm6_7_flush_tlb_all @ 44`
447			`.word arm6_7_flush_tlb_area @ 48`
448			`.word arm7_set_pmd @ 52`
449			`.word arm6_7_reset @ 54`